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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32 |
29 | /** @addtogroup mips32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/cpu.h> |
35 | #include <arch/cpu.h> |
36 | #include <cpu.h> |
36 | #include <cpu.h> |
37 | #include <arch.h> |
37 | #include <arch.h> |
38 | #include <arch/cp0.h> |
38 | #include <arch/cp0.h> |
39 | #include <print.h> |
39 | #include <print.h> |
40 | 40 | ||
41 | struct data_t { |
41 | struct data_t { |
42 | char *vendor; |
42 | char *vendor; |
43 | char *model; |
43 | char *model; |
44 | }; |
44 | }; |
45 | 45 | ||
46 | static struct data_t imp_data[] = { |
46 | static struct data_t imp_data[] = { |
47 | { "Invalid", "Invalid" }, /* 0x00 */ |
47 | { "Invalid", "Invalid" }, /* 0x00 */ |
48 | { "MIPS", "R2000" }, /* 0x01 */ |
48 | { "MIPS", "R2000" }, /* 0x01 */ |
49 | { "MIPS", "R3000" }, /* 0x02 */ |
49 | { "MIPS", "R3000" }, /* 0x02 */ |
50 | { "MIPS", "R6000" }, /* 0x03 */ |
50 | { "MIPS", "R6000" }, /* 0x03 */ |
51 | { "MIPS", " R4000/R4400" }, /* 0x04 */ |
51 | { "MIPS", " R4000/R4400" }, /* 0x04 */ |
52 | { "LSI Logic", "R3000" }, /* 0x05 */ |
52 | { "LSI Logic", "R3000" }, /* 0x05 */ |
53 | { "MIPS", "R6000A" }, /* 0x06 */ |
53 | { "MIPS", "R6000A" }, /* 0x06 */ |
54 | { "IDT", "3051/3052" }, /* 0x07 */ |
54 | { "IDT", "3051/3052" }, /* 0x07 */ |
55 | { "Invalid", "Invalid" }, /* 0x08 */ |
55 | { "Invalid", "Invalid" }, /* 0x08 */ |
56 | { "MIPS", "R10000/T5" }, /* 0x09 */ |
56 | { "MIPS", "R10000/T5" }, /* 0x09 */ |
57 | { "MIPS", "R4200" }, /* 0x0a */ |
57 | { "MIPS", "R4200" }, /* 0x0a */ |
58 | { "Unknown", "Unknown" }, /* 0x0b */ |
58 | { "Unknown", "Unknown" }, /* 0x0b */ |
59 | { "Unknown", "Unknown" }, /* 0x0c */ |
59 | { "Unknown", "Unknown" }, /* 0x0c */ |
60 | { "Invalid", "Invalid" }, /* 0x0d */ |
60 | { "Invalid", "Invalid" }, /* 0x0d */ |
61 | { "Invalid", "Invalid" }, /* 0x0e */ |
61 | { "Invalid", "Invalid" }, /* 0x0e */ |
62 | { "Invalid", "Invalid" }, /* 0x0f */ |
62 | { "Invalid", "Invalid" }, /* 0x0f */ |
63 | { "MIPS", "R8000" }, /* 0x10 */ |
63 | { "MIPS", "R8000" }, /* 0x10 */ |
64 | { "Invalid", "Invalid" }, /* 0x11 */ |
64 | { "Invalid", "Invalid" }, /* 0x11 */ |
65 | { "Invalid", "Invalid" }, /* 0x12 */ |
65 | { "Invalid", "Invalid" }, /* 0x12 */ |
66 | { "Invalid", "Invalid" }, /* 0x13 */ |
66 | { "Invalid", "Invalid" }, /* 0x13 */ |
67 | { "Invalid", "Invalid" }, /* 0x14 */ |
67 | { "Invalid", "Invalid" }, /* 0x14 */ |
68 | { "Invalid", "Invalid" }, /* 0x15 */ |
68 | { "Invalid", "Invalid" }, /* 0x15 */ |
69 | { "Invalid", "Invalid" }, /* 0x16 */ |
69 | { "Invalid", "Invalid" }, /* 0x16 */ |
70 | { "Invalid", "Invalid" }, /* 0x17 */ |
70 | { "Invalid", "Invalid" }, /* 0x17 */ |
71 | { "Invalid", "Invalid" }, /* 0x18 */ |
71 | { "Invalid", "Invalid" }, /* 0x18 */ |
72 | { "Invalid", "Invalid" }, /* 0x19 */ |
72 | { "Invalid", "Invalid" }, /* 0x19 */ |
73 | { "Invalid", "Invalid" }, /* 0x1a */ |
73 | { "Invalid", "Invalid" }, /* 0x1a */ |
74 | { "Invalid", "Invalid" }, /* 0x1b */ |
74 | { "Invalid", "Invalid" }, /* 0x1b */ |
75 | { "Invalid", "Invalid" }, /* 0x1c */ |
75 | { "Invalid", "Invalid" }, /* 0x1c */ |
76 | { "Invalid", "Invalid" }, /* 0x1d */ |
76 | { "Invalid", "Invalid" }, /* 0x1d */ |
77 | { "Invalid", "Invalid" }, /* 0x1e */ |
77 | { "Invalid", "Invalid" }, /* 0x1e */ |
78 | { "Invalid", "Invalid" }, /* 0x1f */ |
78 | { "Invalid", "Invalid" }, /* 0x1f */ |
79 | { "QED", "R4600" }, /* 0x20 */ |
79 | { "QED", "R4600" }, /* 0x20 */ |
80 | { "Sony", "R3000" }, /* 0x21 */ |
80 | { "Sony", "R3000" }, /* 0x21 */ |
81 | { "Toshiba", "R3000" }, /* 0x22 */ |
81 | { "Toshiba", "R3000" }, /* 0x22 */ |
82 | { "NKK", "R3000" }, /* 0x23 */ |
82 | { "NKK", "R3000" }, /* 0x23 */ |
83 | { NULL, NULL } |
83 | { NULL, NULL } |
84 | }; |
84 | }; |
85 | 85 | ||
86 | static struct data_t imp_data80[] = { |
86 | static struct data_t imp_data80[] = { |
87 | { "MIPS", "4Kc" }, /* 0x80 */ |
87 | { "MIPS", "4Kc" }, /* 0x80 */ |
88 | {"Invalid","Invalid"}, /* 0x81 */ |
88 | {"Invalid","Invalid"}, /* 0x81 */ |
89 | {"Invalid","Invalid"}, /* 0x82 */ |
89 | {"Invalid","Invalid"}, /* 0x82 */ |
90 | {"MIPS","4Km & 4Kp"}, /* 0x83 */ |
90 | {"MIPS","4Km & 4Kp"}, /* 0x83 */ |
91 | { NULL, NULL} |
91 | { NULL, NULL} |
92 | }; |
92 | }; |
93 | 93 | ||
94 | void cpu_arch_init(void) |
94 | void cpu_arch_init(void) |
95 | { |
95 | { |
96 | } |
96 | } |
97 | 97 | ||
98 | void cpu_identify(void) |
98 | void cpu_identify(void) |
99 | { |
99 | { |
100 | CPU->arch.rev_num = cp0_prid_read() & 0xff; |
100 | CPU->arch.rev_num = cp0_prid_read() & 0xff; |
101 | CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff; |
101 | CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff; |
102 | } |
102 | } |
103 | 103 | ||
104 | void cpu_print_report(cpu_t *m) |
104 | void cpu_print_report(cpu_t *m) |
105 | { |
105 | { |
106 | struct data_t *data; |
106 | struct data_t *data; |
107 | int i; |
107 | unsigned int i; |
108 | 108 | ||
109 | if (m->arch.imp_num & 0x80) { |
109 | if (m->arch.imp_num & 0x80) { |
110 | /* Count records */ |
110 | /* Count records */ |
111 | for (i=0;imp_data80[i].vendor;i++) |
111 | for (i = 0; imp_data80[i].vendor; i++); |
112 | ; |
- | |
113 | if ((m->arch.imp_num & 0x7f) >= i) { |
112 | if ((m->arch.imp_num & 0x7f) >= i) { |
114 | printf("imp=%d\n",m->arch.imp_num); |
113 | printf("imp=%d\n", m->arch.imp_num); |
115 | return; |
114 | return; |
116 | } |
115 | } |
117 | data = &imp_data80[m->arch.imp_num & 0x7f]; |
116 | data = &imp_data80[m->arch.imp_num & 0x7f]; |
118 | } else { |
117 | } else { |
119 | for (i=0;imp_data[i].vendor;i++) |
118 | for (i = 0; imp_data[i].vendor; i++); |
120 | ; |
- | |
121 | if (m->arch.imp_num >= i) { |
119 | if (m->arch.imp_num >= i) { |
122 | printf("imp=%d\n",m->arch.imp_num); |
120 | printf("imp=%d\n", m->arch.imp_num); |
123 | return; |
121 | return; |
124 | } |
122 | } |
125 | data = &imp_data[m->arch.imp_num]; |
123 | data = &imp_data[m->arch.imp_num]; |
126 | } |
124 | } |
127 | 125 | ||
128 | printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
126 | printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
129 | m->id, data->vendor, data->model, m->arch.rev_num >> 4, |
127 | m->id, data->vendor, data->model, m->arch.rev_num >> 4, |
130 | m->arch.rev_num & 0xf, m->arch.imp_num); |
128 | m->arch.rev_num & 0xf, m->arch.imp_num); |
131 | } |
129 | } |
132 | 130 | ||
133 | /** @} |
131 | /** @} |
134 | */ |
132 | */ |
135 | 133 |