WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/include/mm/page.h


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm   
 * @{
 */
/** @file
 */
 
#ifndef KERN_mips32_PAGE_H_
#define KERN_mips32_PAGE_H_
 
#include <arch/mm/frame.h>
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
 
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
#ifdef KERNEL
 
/*
 * Implementation of generic 4-level page table interface.
 *
 * Page table layout:
 * - 32-bit virtual addresses
 * - Offset is 14 bits => pages are 16K long
 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
 *   4 bytes long
 * - PTE's replace EntryLo v (valid) bit with p (present) bit
 * - PTE's use only one bit to distinguish between cacheable and uncacheable
 *   mappings
 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
 *   the p bit is cleared
 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
 *   and bit A (accessed)
 * - PTL0 has 64 entries (6 bits)
 * - PTL1 is not used
 * - PTL2 is not used
 * - PTL3 has 4096 entries (12 bits)
 */
 
/* Macros describing number of entries in each level. */
#define PTL0_ENTRIES_ARCH   64
#define PTL1_ENTRIES_ARCH   0
#define PTL2_ENTRIES_ARCH   0
#define PTL3_ENTRIES_ARCH   4096
 
/* Macros describing size of page tables in each level. */
#define PTL0_SIZE_ARCH      ONE_FRAME
#define PTL1_SIZE_ARCH      0
#define PTL2_SIZE_ARCH      0
#define PTL3_SIZE_ARCH      ONE_FRAME
 
/* Macros calculating entry indices for each level. */
#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
#define PTL1_INDEX_ARCH(vaddr)  0
#define PTL2_INDEX_ARCH(vaddr)  0
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
/* Set accessor for PTL0 address. */
#define SET_PTL0_ADDRESS_ARCH(ptl0)
 
/* Get PTE address accessors for each level. */
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    (((pte_t *) (ptl0))[(i)].pfn << 12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    (((pte_t *) (ptl3))[(i)].pfn << 12)
 
/* Set PTE address accessors for each level. */
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
 
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
 
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
 
/* Last-level info macros. */
#define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
#define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
#define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
#define PTE_EXECUTABLE_ARCH(pte)        1
 
#ifndef __ASM__
 
#include <mm/mm.h>
#include <arch/exception.h>
 
static inline int get_pt_flags(pte_t *pt, index_t i)
{
    pte_t *p = &pt[i];
   
    return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
        ((!p->p) << PAGE_PRESENT_SHIFT) |
        (1 << PAGE_USER_SHIFT) |
        (1 << PAGE_READ_SHIFT) |
        ((p->w) << PAGE_WRITE_SHIFT) |
        (1 << PAGE_EXEC_SHIFT) |
        (p->g << PAGE_GLOBAL_SHIFT));
}
 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
    pte_t *p = &pt[i];
   
    p->cacheable = (flags & PAGE_CACHEABLE) != 0;
    p->p = !(flags & PAGE_NOT_PRESENT);
    p->g = (flags & PAGE_GLOBAL) != 0;
    p->w = (flags & PAGE_WRITE) != 0;
   
    /*
     * Ensure that valid entries have at least one bit set.
     */
    p->soft_valid = 1;
}
 
extern void page_arch_init(void);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/include/mm/page.h – Rev 2467 → 3233

Rev 2467		Rev 3233
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_mips32_PAGE_H_	35	#ifndef KERN_mips32_PAGE_H_
36	#define KERN_mips32_PAGE_H_	36	#define KERN_mips32_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39		39
40	#define PAGE_WIDTH FRAME_WIDTH	40	#define PAGE_WIDTH FRAME_WIDTH
41	#define PAGE_SIZE FRAME_SIZE	41	#define PAGE_SIZE FRAME_SIZE
42		42
43	#define PAGE_COLOR_BITS 0 /* dummy */	-
44		-
45	#ifndef __ASM__	43	#ifndef __ASM__
46	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	44	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
47	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	45	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
48	#else	46	#else
49	# define KA2PA(x) ((x) - 0x80000000)	47	# define KA2PA(x) ((x) - 0x80000000)
50	# define PA2KA(x) ((x) + 0x80000000)	48	# define PA2KA(x) ((x) + 0x80000000)
51	#endif	49	#endif
52		50
53	#ifdef KERNEL	51	#ifdef KERNEL
54		52
55	/*	53	/*
56	* Implementation of generic 4-level page table interface.	54	* Implementation of generic 4-level page table interface.
57	*	55	*
58	* Page table layout:	56	* Page table layout:
59	* - 32-bit virtual addresses	57	* - 32-bit virtual addresses
60	* - Offset is 14 bits => pages are 16K long	58	* - Offset is 14 bits => pages are 16K long
61	* - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore	59	* - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
62	* 4 bytes long	60	* 4 bytes long
63	* - PTE's replace EntryLo v (valid) bit with p (present) bit	61	* - PTE's replace EntryLo v (valid) bit with p (present) bit
64	* - PTE's use only one bit to distinguish between cacheable and uncacheable	62	* - PTE's use only one bit to distinguish between cacheable and uncacheable
65	* mappings	63	* mappings
66	* - PTE's define soft_valid field to ensure there is at least one 1 bit even if	64	* - PTE's define soft_valid field to ensure there is at least one 1 bit even if
67	* the p bit is cleared	65	* the p bit is cleared
68	* - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)	66	* - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
69	* and bit A (accessed)	67	* and bit A (accessed)
70	* - PTL0 has 64 entries (6 bits)	68	* - PTL0 has 64 entries (6 bits)
71	* - PTL1 is not used	69	* - PTL1 is not used
72	* - PTL2 is not used	70	* - PTL2 is not used
73	* - PTL3 has 4096 entries (12 bits)	71	* - PTL3 has 4096 entries (12 bits)
74	*/	72	*/
75		73
76	/* Macros describing number of entries in each level. */	74	/* Macros describing number of entries in each level. */
77	#define PTL0_ENTRIES_ARCH 64	75	#define PTL0_ENTRIES_ARCH 64
78	#define PTL1_ENTRIES_ARCH 0	76	#define PTL1_ENTRIES_ARCH 0
79	#define PTL2_ENTRIES_ARCH 0	77	#define PTL2_ENTRIES_ARCH 0
80	#define PTL3_ENTRIES_ARCH 4096	78	#define PTL3_ENTRIES_ARCH 4096
81		79
82	/* Macros describing size of page tables in each level. */	80	/* Macros describing size of page tables in each level. */
83	#define PTL0_SIZE_ARCH ONE_FRAME	81	#define PTL0_SIZE_ARCH ONE_FRAME
84	#define PTL1_SIZE_ARCH 0	82	#define PTL1_SIZE_ARCH 0
85	#define PTL2_SIZE_ARCH 0	83	#define PTL2_SIZE_ARCH 0
86	#define PTL3_SIZE_ARCH ONE_FRAME	84	#define PTL3_SIZE_ARCH ONE_FRAME
87		85
88	/* Macros calculating entry indices for each level. */	86	/* Macros calculating entry indices for each level. */
89	#define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26)	87	#define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26)
90	#define PTL1_INDEX_ARCH(vaddr) 0	88	#define PTL1_INDEX_ARCH(vaddr) 0
91	#define PTL2_INDEX_ARCH(vaddr) 0	89	#define PTL2_INDEX_ARCH(vaddr) 0
92	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff)	90	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff)
93		91
94	/* Set accessor for PTL0 address. */	92	/* Set accessor for PTL0 address. */
95	#define SET_PTL0_ADDRESS_ARCH(ptl0)	93	#define SET_PTL0_ADDRESS_ARCH(ptl0)
96		94
97	/* Get PTE address accessors for each level. */	95	/* Get PTE address accessors for each level. */
98	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \	96	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
99	(((pte_t *) (ptl0))[(i)].pfn << 12)	97	(((pte_t *) (ptl0))[(i)].pfn << 12)
100	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \	98	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
101	(ptl1)	99	(ptl1)
102	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \	100	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
103	(ptl2)	101	(ptl2)
104	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \	102	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
105	(((pte_t *) (ptl3))[(i)].pfn << 12)	103	(((pte_t *) (ptl3))[(i)].pfn << 12)
106		104
107	/* Set PTE address accessors for each level. */	105	/* Set PTE address accessors for each level. */
108	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \	106	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
109	(((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)	107	(((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
110	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	108	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
111	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	109	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
112	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \	110	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
113	(((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)	111	(((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
114		112
115	/* Get PTE flags accessors for each level. */	113	/* Get PTE flags accessors for each level. */
116	#define GET_PTL1_FLAGS_ARCH(ptl0, i) \	114	#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
117	get_pt_flags((pte_t *) (ptl0), (index_t) (i))	115	get_pt_flags((pte_t *) (ptl0), (index_t) (i))
118	#define GET_PTL2_FLAGS_ARCH(ptl1, i) \	116	#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
119	PAGE_PRESENT	117	PAGE_PRESENT
120	#define GET_PTL3_FLAGS_ARCH(ptl2, i) \	118	#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
121	PAGE_PRESENT	119	PAGE_PRESENT
122	#define GET_FRAME_FLAGS_ARCH(ptl3, i) \	120	#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
123	get_pt_flags((pte_t *) (ptl3), (index_t) (i))	121	get_pt_flags((pte_t *) (ptl3), (index_t) (i))
124		122
125	/* Set PTE flags accessors for each level. */	123	/* Set PTE flags accessors for each level. */
126	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \	124	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
127	set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))	125	set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
128	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	126	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
129	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	127	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
130	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \	128	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
131	set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))	129	set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
132		130
133	/* Last-level info macros. */	131	/* Last-level info macros. */
134	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	132	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
135	#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)	133	#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
136	#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12)	134	#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12)
137	#define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0)	135	#define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0)
138	#define PTE_EXECUTABLE_ARCH(pte) 1	136	#define PTE_EXECUTABLE_ARCH(pte) 1
139		137
140	#ifndef __ASM__	138	#ifndef __ASM__
141		139
142	#include <mm/mm.h>	140	#include <mm/mm.h>
143	#include <arch/exception.h>	141	#include <arch/exception.h>
144		142
145	static inline int get_pt_flags(pte_t *pt, index_t i)	143	static inline int get_pt_flags(pte_t *pt, index_t i)
146	{	144	{
147	pte_t *p = &pt[i];	145	pte_t *p = &pt[i];
148		146
149	return ((p->cacheable << PAGE_CACHEABLE_SHIFT) \|	147	return ((p->cacheable << PAGE_CACHEABLE_SHIFT) \|
150	((!p->p) << PAGE_PRESENT_SHIFT) \|	148	((!p->p) << PAGE_PRESENT_SHIFT) \|
151	(1 << PAGE_USER_SHIFT) \|	149	(1 << PAGE_USER_SHIFT) \|
152	(1 << PAGE_READ_SHIFT) \|	150	(1 << PAGE_READ_SHIFT) \|
153	((p->w) << PAGE_WRITE_SHIFT) \|	151	((p->w) << PAGE_WRITE_SHIFT) \|
154	(1 << PAGE_EXEC_SHIFT) \|	152	(1 << PAGE_EXEC_SHIFT) \|
155	(p->g << PAGE_GLOBAL_SHIFT));	153	(p->g << PAGE_GLOBAL_SHIFT));
156	}	154	}
157		155
158	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)	156	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
159	{	157	{
160	pte_t *p = &pt[i];	158	pte_t *p = &pt[i];
161		159
162	p->cacheable = (flags & PAGE_CACHEABLE) != 0;	160	p->cacheable = (flags & PAGE_CACHEABLE) != 0;
163	p->p = !(flags & PAGE_NOT_PRESENT);	161	p->p = !(flags & PAGE_NOT_PRESENT);
164	p->g = (flags & PAGE_GLOBAL) != 0;	162	p->g = (flags & PAGE_GLOBAL) != 0;
165	p->w = (flags & PAGE_WRITE) != 0;	163	p->w = (flags & PAGE_WRITE) != 0;
166		164
167	/*	165	/*
168	* Ensure that valid entries have at least one bit set.	166	* Ensure that valid entries have at least one bit set.
169	*/	167	*/
170	p->soft_valid = 1;	168	p->soft_valid = 1;
171	}	169	}
172		170
173	extern void page_arch_init(void);	171	extern void page_arch_init(void);
174		172
175	#endif /* __ASM__ */	173	#endif /* __ASM__ */
176		174
177	#endif /* KERNEL */	175	#endif /* KERNEL */
178		176
179	#endif	177	#endif
180		178
181	/** @}	179	/** @}
182	*/	180	*/
183		181