WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/include/cp0.h


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CP0_H__
#define __CP0_H__
 
#include <arch/types.h>
 
#define cp0_status_ie_enabled_bit   (1<<0)
#define cp0_status_exl_exception_bit    (1<<1)
#define cp0_status_erl_error_bit    (1<<2)
#define cp0_status_um_bit           (1<<4)
#define cp0_status_bev_bootstrap_bit    (1<<22)
#define cp0_status_fpu_bit              (1<<29)
 
#define cp0_status_im_shift     8
#define cp0_status_im_mask              0xff00
 
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
 
#define fpu_cop_id 1
 
/*
 * Magic value for use in msim.
 * On AMD Duron 800Mhz, this roughly seems like one us.
 */
#define cp0_compare_value       10000
 
static inline void tlbp(void)
{
    __asm__ volatile ("tlbp");
}
 
static inline void tlbr(void)
{
    __asm__ volatile ("tlbr");
}
static inline void tlbwi(void)
{
    __asm__ volatile ("tlbwi");
}
static inline void tlbwr(void)
{
    __asm__ volatile ("tlbwr");
}
 
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
 
extern  __u32 cp0_index_read(void);
extern void cp0_idnex_write(__u32 val);
 
extern __u32 cp0_random_read(void);
 
extern __u32 cp0_entry_lo0_read(void);
extern void cp0_entry_lo0_write(__u32 val);
 
extern __u32 cp0_entry_lo1_read(void);
extern void cp0_entry_lo1_write(__u32 val);
 
extern __u32 cp0_context_read(void);
extern void cp0_context_write(__u32 val);
 
extern __u32 cp0_pagemask_read(void);
extern void cp0_pagemask_write(__u32 val);
 
extern __u32 cp0_wired_read(void);
extern void cp0_wired_write(__u32 val);
 
extern __u32 cp0_badvaddr_read(void);
 
extern volatile __u32 cp0_count_read(void);
extern void cp0_count_write(__u32 val);
 
extern volatile __u32 cp0_entry_hi_read(void);
extern void cp0_entry_hi_write(__u32 val);
 
extern volatile __u32 cp0_compare_read(void);
extern void cp0_compare_write(__u32 val);
 
extern __u32 cp0_status_read(void);
extern void cp0_status_write(__u32 val);
 
extern __u32 cp0_cause_read(void);
extern void cp0_cause_write(__u32 val);
 
extern __u32 cp0_epc_read(void);
extern void cp0_epc_write(__u32 val);
 
extern __u32 cp0_prid_read(void);
 
#endif
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/include/cp0.h @ 2071 – Rev 329 → 330

Rev 329		Rev 330
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __CP0_H__	29	#ifndef __CP0_H__
30	#define __CP0_H__	30	#define __CP0_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33		33
34	#define cp0_status_ie_enabled_bit (1<<0)	34	#define cp0_status_ie_enabled_bit (1<<0)
35	#define cp0_status_exl_exception_bit (1<<1)	35	#define cp0_status_exl_exception_bit (1<<1)
36	#define cp0_status_erl_error_bit (1<<2)	36	#define cp0_status_erl_error_bit (1<<2)
37	#define cp0_status_um_bit (1<<4)	37	#define cp0_status_um_bit (1<<4)
38	#define cp0_status_bev_bootstrap_bit (1<<22)	38	#define cp0_status_bev_bootstrap_bit (1<<22)
39	#define cp0_status_fpu_bit (1<<29)	39	#define cp0_status_fpu_bit (1<<29)
40		40
41	#define cp0_status_im_shift 8	41	#define cp0_status_im_shift 8
42	#define cp0_status_im_mask 0xff00	42	#define cp0_status_im_mask 0xff00
43		43
-		44	#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
-		45	#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
-		46
-		47	#define fpu_cop_id 1
-		48
44	/*	49	/*
45	* Magic value for use in msim.	50	* Magic value for use in msim.
46	* On AMD Duron 800Mhz, this roughly seems like one us.	51	* On AMD Duron 800Mhz, this roughly seems like one us.
47	*/	52	*/
48	#define cp0_compare_value 10000	53	#define cp0_compare_value 10000
49		54
50	static inline void tlbp(void)	55	static inline void tlbp(void)
51	{	56	{
52	__asm__ volatile ("tlbp");	57	__asm__ volatile ("tlbp");
53	}	58	}
54		59
55	static inline void tlbr(void)	60	static inline void tlbr(void)
56	{	61	{
57	__asm__ volatile ("tlbr");	62	__asm__ volatile ("tlbr");
58	}	63	}
59	static inline void tlbwi(void)	64	static inline void tlbwi(void)
60	{	65	{
61	__asm__ volatile ("tlbwi");	66	__asm__ volatile ("tlbwi");
62	}	67	}
63	static inline void tlbwr(void)	68	static inline void tlbwr(void)
64	{	69	{
65	__asm__ volatile ("tlbwr");	70	__asm__ volatile ("tlbwr");
66	}	71	}
67		72
68	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))	73	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
69	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)	74	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)
70	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))	75	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
71	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))	76	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))
72		77
73		78
74	extern __u32 cp0_index_read(void);	79	extern __u32 cp0_index_read(void);
75	extern void cp0_idnex_write(__u32 val);	80	extern void cp0_idnex_write(__u32 val);
76		81
77	extern __u32 cp0_random_read(void);	82	extern __u32 cp0_random_read(void);
78		83
79	extern __u32 cp0_entry_lo0_read(void);	84	extern __u32 cp0_entry_lo0_read(void);
80	extern void cp0_entry_lo0_write(__u32 val);	85	extern void cp0_entry_lo0_write(__u32 val);
81		86
82	extern __u32 cp0_entry_lo1_read(void);	87	extern __u32 cp0_entry_lo1_read(void);
83	extern void cp0_entry_lo1_write(__u32 val);	88	extern void cp0_entry_lo1_write(__u32 val);
84		89
85	extern __u32 cp0_context_read(void);	90	extern __u32 cp0_context_read(void);
86	extern void cp0_context_write(__u32 val);	91	extern void cp0_context_write(__u32 val);
87		92
88	extern __u32 cp0_pagemask_read(void);	93	extern __u32 cp0_pagemask_read(void);
89	extern void cp0_pagemask_write(__u32 val);	94	extern void cp0_pagemask_write(__u32 val);
90		95
91	extern __u32 cp0_wired_read(void);	96	extern __u32 cp0_wired_read(void);
92	extern void cp0_wired_write(__u32 val);	97	extern void cp0_wired_write(__u32 val);
93		98
94	extern __u32 cp0_badvaddr_read(void);	99	extern __u32 cp0_badvaddr_read(void);
95		100
96	extern volatile __u32 cp0_count_read(void);	101	extern volatile __u32 cp0_count_read(void);
97	extern void cp0_count_write(__u32 val);	102	extern void cp0_count_write(__u32 val);
98		103
99	extern volatile __u32 cp0_entry_hi_read(void);	104	extern volatile __u32 cp0_entry_hi_read(void);
100	extern void cp0_entry_hi_write(__u32 val);	105	extern void cp0_entry_hi_write(__u32 val);
101		106
102	extern volatile __u32 cp0_compare_read(void);	107	extern volatile __u32 cp0_compare_read(void);
103	extern void cp0_compare_write(__u32 val);	108	extern void cp0_compare_write(__u32 val);
104		109
105	extern __u32 cp0_status_read(void);	110	extern __u32 cp0_status_read(void);
106	extern void cp0_status_write(__u32 val);	111	extern void cp0_status_write(__u32 val);
107		112
108	extern __u32 cp0_cause_read(void);	113	extern __u32 cp0_cause_read(void);
109	extern void cp0_cause_write(__u32 val);	114	extern void cp0_cause_write(__u32 val);
110		115
111	extern __u32 cp0_epc_read(void);	116	extern __u32 cp0_epc_read(void);
112	extern void cp0_epc_write(__u32 val);	117	extern void cp0_epc_write(__u32 val);
113		118
114	extern __u32 cp0_prid_read(void);	119	extern __u32 cp0_prid_read(void);
115		120
116	#endif	121	#endif
117		122