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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __mips32_CP0_H__ |
29 | #ifndef __mips32_CP0_H__ |
30 | #define __mips32_CP0_H__ |
30 | #define __mips32_CP0_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <arch/mm/tlb.h> |
33 | #include <arch/mm/tlb.h> |
34 | 34 | ||
35 | #define cp0_status_ie_enabled_bit (1<<0) |
35 | #define cp0_status_ie_enabled_bit (1<<0) |
36 | #define cp0_status_exl_exception_bit (1<<1) |
36 | #define cp0_status_exl_exception_bit (1<<1) |
37 | #define cp0_status_erl_error_bit (1<<2) |
37 | #define cp0_status_erl_error_bit (1<<2) |
38 | #define cp0_status_um_bit (1<<4) |
38 | #define cp0_status_um_bit (1<<4) |
39 | #define cp0_status_bev_bootstrap_bit (1<<22) |
39 | #define cp0_status_bev_bootstrap_bit (1<<22) |
40 | #define cp0_status_fpu_bit (1<<29) |
40 | #define cp0_status_fpu_bit (1<<29) |
41 | 41 | ||
42 | #define cp0_status_im_shift 8 |
42 | #define cp0_status_im_shift 8 |
43 | #define cp0_status_im_mask 0xff00 |
43 | #define cp0_status_im_mask 0xff00 |
44 | 44 | ||
45 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
45 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
46 | #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
46 | #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
47 | 47 | ||
48 | #define fpu_cop_id 1 |
48 | #define fpu_cop_id 1 |
49 | 49 | ||
50 | /* |
50 | /* |
51 | * Magic value for use in msim. |
51 | * Magic value for use in msim. |
52 | * On AMD Duron 800Mhz, this roughly seems like one us. |
- | |
53 | */ |
52 | */ |
54 | #define cp0_compare_value 10000 |
53 | #define cp0_compare_value 100000 |
55 | 54 | ||
56 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
55 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
57 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
56 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
58 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
57 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
59 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
58 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
60 | 59 | ||
61 | #define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \ |
60 | #define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \ |
62 | { \ |
61 | { \ |
63 | __u32 retval; \ |
62 | __u32 retval; \ |
64 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |
63 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |
65 | return retval; \ |
64 | return retval; \ |
66 | } |
65 | } |
67 | 66 | ||
68 | #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \ |
67 | #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \ |
69 | { \ |
68 | { \ |
70 | asm("mtc0 %0, $" #reg : : "r"(val) ); \ |
69 | asm("mtc0 %0, $" #reg : : "r"(val) ); \ |
71 | } |
70 | } |
72 | 71 | ||
73 | GEN_READ_CP0(index, 0); |
72 | GEN_READ_CP0(index, 0); |
74 | GEN_WRITE_CP0(index, 0); |
73 | GEN_WRITE_CP0(index, 0); |
75 | 74 | ||
76 | GEN_READ_CP0(random, 1); |
75 | GEN_READ_CP0(random, 1); |
77 | 76 | ||
78 | GEN_READ_CP0(entry_lo0, 2); |
77 | GEN_READ_CP0(entry_lo0, 2); |
79 | GEN_WRITE_CP0(entry_lo0, 2); |
78 | GEN_WRITE_CP0(entry_lo0, 2); |
80 | 79 | ||
81 | GEN_READ_CP0(entry_lo1, 3); |
80 | GEN_READ_CP0(entry_lo1, 3); |
82 | GEN_WRITE_CP0(entry_lo1, 3); |
81 | GEN_WRITE_CP0(entry_lo1, 3); |
83 | 82 | ||
84 | GEN_READ_CP0(context, 4); |
83 | GEN_READ_CP0(context, 4); |
85 | GEN_WRITE_CP0(context, 4); |
84 | GEN_WRITE_CP0(context, 4); |
86 | 85 | ||
87 | GEN_READ_CP0(pagemask, 5); |
86 | GEN_READ_CP0(pagemask, 5); |
88 | GEN_WRITE_CP0(pagemask, 5); |
87 | GEN_WRITE_CP0(pagemask, 5); |
89 | 88 | ||
90 | GEN_READ_CP0(wired, 6); |
89 | GEN_READ_CP0(wired, 6); |
91 | GEN_WRITE_CP0(wired, 6); |
90 | GEN_WRITE_CP0(wired, 6); |
92 | 91 | ||
93 | GEN_READ_CP0(badvaddr, 8); |
92 | GEN_READ_CP0(badvaddr, 8); |
94 | 93 | ||
95 | GEN_READ_CP0(count, 9); |
94 | GEN_READ_CP0(count, 9); |
96 | GEN_WRITE_CP0(count, 9); |
95 | GEN_WRITE_CP0(count, 9); |
97 | 96 | ||
98 | GEN_READ_CP0(entry_hi, 10); |
97 | GEN_READ_CP0(entry_hi, 10); |
99 | GEN_WRITE_CP0(entry_hi, 10); |
98 | GEN_WRITE_CP0(entry_hi, 10); |
100 | 99 | ||
101 | GEN_READ_CP0(compare, 11); |
100 | GEN_READ_CP0(compare, 11); |
102 | GEN_WRITE_CP0(compare, 11); |
101 | GEN_WRITE_CP0(compare, 11); |
103 | 102 | ||
104 | GEN_READ_CP0(status, 12); |
103 | GEN_READ_CP0(status, 12); |
105 | GEN_WRITE_CP0(status, 12); |
104 | GEN_WRITE_CP0(status, 12); |
106 | 105 | ||
107 | GEN_READ_CP0(cause, 13); |
106 | GEN_READ_CP0(cause, 13); |
108 | GEN_WRITE_CP0(cause, 13); |
107 | GEN_WRITE_CP0(cause, 13); |
109 | 108 | ||
110 | GEN_READ_CP0(epc, 14); |
109 | GEN_READ_CP0(epc, 14); |
111 | GEN_WRITE_CP0(epc, 14); |
110 | GEN_WRITE_CP0(epc, 14); |
112 | 111 | ||
113 | GEN_READ_CP0(prid, 15); |
112 | GEN_READ_CP0(prid, 15); |
114 | 113 | ||
115 | #endif |
114 | #endif |
116 | 115 |