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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __CP0_H__ |
29 | #ifndef __CP0_H__ |
30 | #define __CP0_H__ |
30 | #define __CP0_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | 33 | ||
34 | #define cp0_status_ie_enabled_bit (1<<0) |
34 | #define cp0_status_ie_enabled_bit (1<<0) |
35 | #define cp0_status_exl_exception_bit (1<<1) |
35 | #define cp0_status_exl_exception_bit (1<<1) |
36 | #define cp0_status_erl_error_bit (1<<2) |
36 | #define cp0_status_erl_error_bit (1<<2) |
37 | #define cp0_status_bev_bootstrap_bit (1<<22) |
- | |
38 | #define cp0_status_um_bit (1<<4) |
37 | #define cp0_status_um_bit (1<<4) |
- | 38 | #define cp0_status_bev_bootstrap_bit (1<<22) |
|
- | 39 | #define cp0_status_fpu_bit (1<<29) |
|
39 | 40 | ||
40 | #define cp0_status_im7_shift 15 |
41 | #define cp0_status_im7_shift 15 |
41 | /* |
42 | /* |
42 | * Magic value for use in msim. |
43 | * Magic value for use in msim. |
43 | * On AMD Duron 800Mhz, this roughly seems like one us. |
44 | * On AMD Duron 800Mhz, this roughly seems like one us. |
44 | */ |
45 | */ |
45 | #define cp0_compare_value 10000 |
46 | #define cp0_compare_value 10000 |
46 | 47 | ||
- | 48 | static inline void tlbp(void) |
|
- | 49 | { |
|
- | 50 | __asm__ volatile ("tlbp"); |
|
- | 51 | } |
|
- | 52 | ||
- | 53 | static inline void tlbr(void) |
|
- | 54 | { |
|
- | 55 | __asm__ volatile ("tlbr"); |
|
- | 56 | } |
|
- | 57 | static inline void tlbwi(void) |
|
- | 58 | { |
|
- | 59 | __asm__ volatile ("tlbwi"); |
|
- | 60 | } |
|
- | 61 | static inline void tlbwr(void) |
|
- | 62 | { |
|
- | 63 | __asm__ volatile ("tlbwr"); |
|
- | 64 | } |
|
- | 65 | ||
- | 66 | ||
- | 67 | ||
47 | extern __u32 cp0_index_read(void); |
68 | extern __u32 cp0_index_read(void); |
48 | extern void cp0_idnex_write(__u32 val); |
69 | extern void cp0_idnex_write(__u32 val); |
49 | 70 | ||
50 | extern __u32 cp0_random_read(void); |
71 | extern __u32 cp0_random_read(void); |
51 | 72 | ||
52 | extern __u32 cp0_entry_lo0_read(void); |
73 | extern __u32 cp0_entry_lo0_read(void); |
53 | extern void cp0_entry_lo0_write(__u32 val); |
74 | extern void cp0_entry_lo0_write(__u32 val); |
54 | 75 | ||
55 | extern __u32 cp0_entry_lo1_read(void); |
76 | extern __u32 cp0_entry_lo1_read(void); |
56 | extern void cp0_entry_lo1_write(__u32 val); |
77 | extern void cp0_entry_lo1_write(__u32 val); |
57 | 78 | ||
58 | extern __u32 cp0_context_read(void); |
79 | extern __u32 cp0_context_read(void); |
59 | extern void cp0_context_write(__u32 val); |
80 | extern void cp0_context_write(__u32 val); |
60 | 81 | ||
61 | extern __u32 cp0_pagemask_read(void); |
82 | extern __u32 cp0_pagemask_read(void); |
62 | extern void cp0_pagemask_write(__u32 val); |
83 | extern void cp0_pagemask_write(__u32 val); |
63 | 84 | ||
64 | extern __u32 cp0_wired_read(void); |
85 | extern __u32 cp0_wired_read(void); |
65 | extern void cp0_wired_write(__u32 val); |
86 | extern void cp0_wired_write(__u32 val); |
66 | 87 | ||
67 | extern __u32 cp0_badvaddr_read(void); |
88 | extern __u32 cp0_badvaddr_read(void); |
68 | 89 | ||
69 | extern volatile __u32 cp0_count_read(void); |
90 | extern volatile __u32 cp0_count_read(void); |
70 | extern void cp0_count_write(__u32 val); |
91 | extern void cp0_count_write(__u32 val); |
71 | 92 | ||
72 | extern volatile __u32 cp0_entry_hi_read(void); |
93 | extern volatile __u32 cp0_entry_hi_read(void); |
73 | extern void cp0_entry_hi_write(__u32 val); |
94 | extern void cp0_entry_hi_write(__u32 val); |
74 | 95 | ||
75 | extern volatile __u32 cp0_compare_read(void); |
96 | extern volatile __u32 cp0_compare_read(void); |
76 | extern void cp0_compare_write(__u32 val); |
97 | extern void cp0_compare_write(__u32 val); |
77 | 98 | ||
78 | extern __u32 cp0_status_read(void); |
99 | extern __u32 cp0_status_read(void); |
79 | extern void cp0_status_write(__u32 val); |
100 | extern void cp0_status_write(__u32 val); |
80 | 101 | ||
81 | extern __u32 cp0_cause_read(void); |
102 | extern __u32 cp0_cause_read(void); |
82 | extern void cp0_cause_write(__u32 val); |
103 | extern void cp0_cause_write(__u32 val); |
83 | 104 | ||
84 | extern __u32 cp0_epc_read(void); |
105 | extern __u32 cp0_epc_read(void); |
85 | extern void cp0_epc_write(__u32 val); |
106 | extern void cp0_epc_write(__u32 val); |
86 | 107 | ||
87 | extern __u32 cp0_prid_read(void); |
108 | extern __u32 cp0_prid_read(void); |
88 | 109 | ||
89 | extern void tlbp(void); |
- | |
90 | extern void tlbr(void); |
- | |
91 | extern void tlbwi(void); |
- | |
92 | extern void tlbwr(void); |
- | |
93 | - | ||
94 | #endif |
110 | #endif |
95 | 111 |