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#
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#
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# Copyright (c) 2005 Jakub Jermar
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# Copyright (c) 2005 Jakub Jermar
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <arch/mm/asid.h>
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#include <arch/mm/asid.h>
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#include <mm/asid.h>
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#include <mm/asid.h>
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#define RR_MASK (0xFFFFFFFF00000002)
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#define RR_MASK (0xFFFFFFFF00000002)
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#define RID_SHIFT 8
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#define RID_SHIFT 8
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#define PS_SHIFT 2
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#define PS_SHIFT 2
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#define KERNEL_TRANSLATION_I 0x0010000000000661
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#define KERNEL_TRANSLATION_I  0x0010000000000661
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#define KERNEL_TRANSLATION_D 0x0010000000000661
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#define KERNEL_TRANSLATION_D  0x0010000000000661
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#define KERNEL_TRANSLATION_VIO 0x0010000000000671
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#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
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#define VIO_OFFSET            0x0002000000000000
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- 
 
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#define IO_OFFSET             0x0001000000000000
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- 
 
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.section K_TEXT_START, "ax"
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.section K_TEXT_START, "ax"
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.global kernel_image_start
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.global kernel_image_start
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 51 
 
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stack0:
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stack0:
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kernel_image_start:
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kernel_image_start:
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	.auto
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	.auto
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- 
 
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	mov psr.l = r0
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	srlz.i
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	srlz.d
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 59 
 
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	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
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	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
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 61 
 
- 
 
 62 
 
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	movl r8 = (VRN_KERNEL << VRN_SHIFT)
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	movl r8 = (VRN_KERNEL << VRN_SHIFT)
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	mov r9 = rr[r8]
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	mov r9 = rr[r8]
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 65 
 
- 
 
 66 
 
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	movl r10 = (RR_MASK)
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	movl r10 = (RR_MASK)
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	and r9 = r10, r9
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	and r9 = r10, r9
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	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
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	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
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	or  r9 = r10, r9
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	or  r9 = r10, r9
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- 
 
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	mov rr[r8] = r9
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	mov rr[r8] = r9
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- 
 
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- 
 
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	movl r8 = (VRN_KERNEL << VRN_SHIFT)
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	movl r8 = (VRN_KERNEL << VRN_SHIFT)
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	mov cr.ifa = r8
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	mov cr.ifa = r8
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- 
 
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	mov r11 = cr.itir ;;
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	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
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	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
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	or r10 =r10 , r11  ;;
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	mov cr.itir = r10
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	mov cr.itir = r10;;
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	movl r10 = (KERNEL_TRANSLATION_I)
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	movl r10 = (KERNEL_TRANSLATION_I)
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	itr.i itr[r0] = r10
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	itr.i itr[r0] = r10
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	movl r10 = (KERNEL_TRANSLATION_D)
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	movl r10 = (KERNEL_TRANSLATION_D)
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	itr.d dtr[r0] = r10
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	itr.d dtr[r0] = r10
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- 
 
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	movl r7 = 1
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	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
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	mov cr.ifa = r8
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	movl r10 = (KERNEL_TRANSLATION_VIO)
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	itr.d dtr[r7] = r10
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	mov r11 = cr.itir ;;
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	movl r10 = ~0xfc;;
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	and r10 =r10 , r11  ;;
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	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
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	or r10 =r10 , r11  ;;
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	mov cr.itir = r10;;
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	movl r7 = 2
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	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
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	mov cr.ifa = r8
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	movl r10 = (KERNEL_TRANSLATION_IO)
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	itr.d dtr[r7] = r10
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	# initialize PSR
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	# initialize PSR
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	mov psr.l = r0
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	srlz.i
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	srlz.d
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	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
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	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
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	mov r9 = psr
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	mov r9 = psr
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	or r10 = r10, r9
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	or r10 = r10, r9
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	mov cr.ipsr = r10
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	mov cr.ipsr = r10
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	mov cr.ifs = r0
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	mov cr.ifs = r0
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	movl r8 = paging_start
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	movl r8 = paging_start
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	mov cr.iip = r8
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	mov cr.iip = r8
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	srlz.d
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	srlz.d
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	srlz.i
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	srlz.i
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	.explicit
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	.explicit
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	/*
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	/*
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	 * Return From Interupt is the only the way to fill upper half word of PSR.
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	 * Return From Interupt is the only the way to fill upper half word of PSR.
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	 */
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	 */
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	rfi;;
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	rfi;;
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.global paging_start
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.global paging_start
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paging_start:
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paging_start:
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	/*
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	/*
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	 * Now we are paging.
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	 * Now we are paging.
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	 */
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	 */
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	# switch to register bank 1
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	# switch to register bank 1
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	bsw.1
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	bsw.1
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	# initialize register stack
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	# initialize register stack
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	mov ar.rsc = r0
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	mov ar.rsc = r0
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	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
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	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
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	mov ar.bspstore = r8
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	mov ar.bspstore = r8
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	loadrs
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	loadrs
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	# initialize memory stack to some sane value
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	# initialize memory stack to some sane value
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	movl r12 = stack0 ;;
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	movl r12 = stack0 ;;
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	add r12 = -16, r12	/* allocate a scratch area on the stack */
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	add r12 = -16, r12	/* allocate a scratch area on the stack */
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	# initialize gp (Global Pointer) register
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	# initialize gp (Global Pointer) register
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	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
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	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
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	or r20 = r20,r1;;
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	or r20 = r20,r1;;
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	movl r1 = _hardcoded_load_address
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	movl r1 = _hardcoded_load_address
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	/*
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	/*
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	 * Initialize hardcoded_* variables.
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	 * Initialize hardcoded_* variables.
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	 */
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	 */
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	movl r14 = _hardcoded_ktext_size
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	movl r14 = _hardcoded_ktext_size
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	movl r15 = _hardcoded_kdata_size
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	movl r15 = _hardcoded_kdata_size
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	movl r16 = _hardcoded_load_address ;;
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	movl r16 = _hardcoded_load_address ;;
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	addl r17 = @gprel(hardcoded_ktext_size), gp
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	addl r17 = @gprel(hardcoded_ktext_size), gp
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	addl r18 = @gprel(hardcoded_kdata_size), gp
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	addl r18 = @gprel(hardcoded_kdata_size), gp
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	addl r19 = @gprel(hardcoded_load_address), gp
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	addl r19 = @gprel(hardcoded_load_address), gp
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	addl r21 = @gprel(bootinfo), gp
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	addl r21 = @gprel(bootinfo), gp
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	;;
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	;;
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	st8 [r17] = r14
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	st8 [r17] = r14
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	st8 [r18] = r15
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	st8 [r18] = r15
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	st8 [r19] = r16
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	st8 [r19] = r16
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	st8 [r21] = r20
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	st8 [r21] = r20
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	ssm (1 << 19) ;; /* Disable f32 - f127 */
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	ssm (1 << 19) ;; /* Disable f32 - f127 */
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	srlz.i
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	srlz.i
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	srlz.d ;;
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	srlz.d ;;
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134 
	br.call.sptk.many b0 = arch_pre_main
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	br.call.sptk.many b0 = arch_pre_main
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	movl r18 = main_bsp ;;
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	movl r18 = main_bsp ;;
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	mov b1 = r18 ;;
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	mov b1 = r18 ;;
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	br.call.sptk.many b0 = b1
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	br.call.sptk.many b0 = b1
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0:
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0:
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	br 0b
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	br 0b
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