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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ia64mm |
29 | /** @addtogroup ia64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | /* |
35 | /* |
36 | * TLB management. |
36 | * TLB management. |
37 | */ |
37 | */ |
38 | 38 | ||
39 | #include <mm/tlb.h> |
39 | #include <mm/tlb.h> |
40 | #include <mm/asid.h> |
40 | #include <mm/asid.h> |
41 | #include <mm/page.h> |
41 | #include <mm/page.h> |
42 | #include <mm/as.h> |
42 | #include <mm/as.h> |
43 | #include <arch/mm/tlb.h> |
43 | #include <arch/mm/tlb.h> |
44 | #include <arch/mm/page.h> |
44 | #include <arch/mm/page.h> |
45 | #include <arch/mm/vhpt.h> |
45 | #include <arch/mm/vhpt.h> |
46 | #include <arch/barrier.h> |
46 | #include <arch/barrier.h> |
47 | #include <arch/interrupt.h> |
47 | #include <arch/interrupt.h> |
48 | #include <arch/pal/pal.h> |
48 | #include <arch/pal/pal.h> |
49 | #include <arch/asm.h> |
49 | #include <arch/asm.h> |
50 | #include <panic.h> |
50 | #include <panic.h> |
51 | #include <print.h> |
51 | #include <print.h> |
52 | #include <arch.h> |
52 | #include <arch.h> |
53 | #include <interrupt.h> |
53 | #include <interrupt.h> |
54 | 54 | ||
55 | /** Invalidate all TLB entries. */ |
55 | /** Invalidate all TLB entries. */ |
56 | void tlb_invalidate_all(void) |
56 | void tlb_invalidate_all(void) |
57 | { |
57 | { |
58 | ipl_t ipl; |
58 | ipl_t ipl; |
59 | uintptr_t adr; |
59 | uintptr_t adr; |
60 | uint32_t count1, count2, stride1, stride2; |
60 | uint32_t count1, count2, stride1, stride2; |
61 | 61 | ||
62 | unsigned int i, j; |
62 | unsigned int i, j; |
63 | 63 | ||
64 | adr = PAL_PTCE_INFO_BASE(); |
64 | adr = PAL_PTCE_INFO_BASE(); |
65 | count1 = PAL_PTCE_INFO_COUNT1(); |
65 | count1 = PAL_PTCE_INFO_COUNT1(); |
66 | count2 = PAL_PTCE_INFO_COUNT2(); |
66 | count2 = PAL_PTCE_INFO_COUNT2(); |
67 | stride1 = PAL_PTCE_INFO_STRIDE1(); |
67 | stride1 = PAL_PTCE_INFO_STRIDE1(); |
68 | stride2 = PAL_PTCE_INFO_STRIDE2(); |
68 | stride2 = PAL_PTCE_INFO_STRIDE2(); |
69 | 69 | ||
70 | ipl = interrupts_disable(); |
70 | ipl = interrupts_disable(); |
71 | 71 | ||
72 | for (i = 0; i < count1; i++) { |
72 | for (i = 0; i < count1; i++) { |
73 | for (j = 0; j < count2; j++) { |
73 | for (j = 0; j < count2; j++) { |
74 | asm volatile ( |
74 | asm volatile ( |
75 | "ptc.e %0 ;;" |
75 | "ptc.e %0 ;;" |
76 | : |
76 | : |
77 | : "r" (adr) |
77 | : "r" (adr) |
78 | ); |
78 | ); |
79 | adr += stride2; |
79 | adr += stride2; |
80 | } |
80 | } |
81 | adr += stride1; |
81 | adr += stride1; |
82 | } |
82 | } |
83 | 83 | ||
84 | interrupts_restore(ipl); |
84 | interrupts_restore(ipl); |
85 | 85 | ||
86 | srlz_d(); |
86 | srlz_d(); |
87 | srlz_i(); |
87 | srlz_i(); |
88 | #ifdef CONFIG_VHPT |
88 | #ifdef CONFIG_VHPT |
89 | vhpt_invalidate_all(); |
89 | vhpt_invalidate_all(); |
90 | #endif |
90 | #endif |
91 | } |
91 | } |
92 | 92 | ||
93 | /** Invalidate entries belonging to an address space. |
93 | /** Invalidate entries belonging to an address space. |
94 | * |
94 | * |
95 | * @param asid Address space identifier. |
95 | * @param asid Address space identifier. |
96 | */ |
96 | */ |
97 | void tlb_invalidate_asid(asid_t asid) |
97 | void tlb_invalidate_asid(asid_t asid) |
98 | { |
98 | { |
99 | tlb_invalidate_all(); |
99 | tlb_invalidate_all(); |
100 | } |
100 | } |
101 | 101 | ||
102 | 102 | ||
103 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
103 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
104 | { |
104 | { |
105 | region_register rr; |
105 | region_register rr; |
106 | bool restore_rr = false; |
106 | bool restore_rr = false; |
107 | int b = 0; |
107 | int b = 0; |
108 | int c = cnt; |
108 | int c = cnt; |
109 | 109 | ||
110 | uintptr_t va; |
110 | uintptr_t va; |
111 | va = page; |
111 | va = page; |
112 | 112 | ||
113 | rr.word = rr_read(VA2VRN(va)); |
113 | rr.word = rr_read(VA2VRN(va)); |
114 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
114 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
115 | /* |
115 | /* |
116 | * The selected region register does not contain required RID. |
116 | * The selected region register does not contain required RID. |
117 | * Save the old content of the register and replace the RID. |
117 | * Save the old content of the register and replace the RID. |
118 | */ |
118 | */ |
119 | region_register rr0; |
119 | region_register rr0; |
120 | 120 | ||
121 | rr0 = rr; |
121 | rr0 = rr; |
122 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
122 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
123 | rr_write(VA2VRN(va), rr0.word); |
123 | rr_write(VA2VRN(va), rr0.word); |
124 | srlz_d(); |
124 | srlz_d(); |
125 | srlz_i(); |
125 | srlz_i(); |
126 | } |
126 | } |
127 | 127 | ||
128 | while(c >>= 1) |
128 | while(c >>= 1) |
129 | b++; |
129 | b++; |
130 | b >>= 1; |
130 | b >>= 1; |
131 | uint64_t ps; |
131 | uint64_t ps; |
132 | 132 | ||
133 | switch (b) { |
133 | switch (b) { |
134 | case 0: /*cnt 1-3*/ |
134 | case 0: /* cnt 1 - 3 */ |
135 | ps = PAGE_WIDTH; |
135 | ps = PAGE_WIDTH; |
136 | break; |
136 | break; |
137 | case 1: /*cnt 4-15*/ |
137 | case 1: /* cnt 4 - 15 */ |
138 | ps = PAGE_WIDTH+2; |
138 | ps = PAGE_WIDTH + 2; |
139 | va &= ~((1<<ps)-1); |
139 | va &= ~((1 << ps) - 1); |
140 | break; |
140 | break; |
141 | case 2: /*cnt 16-63*/ |
141 | case 2: /* cnt 16 - 63 */ |
142 | ps = PAGE_WIDTH+4; |
142 | ps = PAGE_WIDTH + 4; |
143 | va &= ~((1<<ps)-1); |
143 | va &= ~((1 << ps) - 1); |
144 | break; |
144 | break; |
145 | case 3: /*cnt 64-255*/ |
145 | case 3: /* cnt 64 - 255 */ |
146 | ps = PAGE_WIDTH+6; |
146 | ps = PAGE_WIDTH + 6; |
147 | va &= ~((1<<ps)-1); |
147 | va &= ~((1 << ps) - 1); |
148 | break; |
148 | break; |
149 | case 4: /*cnt 256-1023*/ |
149 | case 4: /* cnt 256 - 1023 */ |
150 | ps = PAGE_WIDTH+8; |
150 | ps = PAGE_WIDTH + 8; |
151 | va &= ~((1<<ps)-1); |
151 | va &= ~((1 << ps) - 1); |
152 | break; |
152 | break; |
153 | case 5: /*cnt 1024-4095*/ |
153 | case 5: /* cnt 1024 - 4095 */ |
154 | ps = PAGE_WIDTH+10; |
154 | ps = PAGE_WIDTH + 10; |
155 | va &= ~((1<<ps)-1); |
155 | va &= ~((1 << ps) - 1); |
156 | break; |
156 | break; |
157 | case 6: /*cnt 4096-16383*/ |
157 | case 6: /* cnt 4096 - 16383 */ |
158 | ps = PAGE_WIDTH+12; |
158 | ps = PAGE_WIDTH + 12; |
159 | va &= ~((1<<ps)-1); |
159 | va &= ~((1 << ps) - 1); |
160 | break; |
160 | break; |
161 | case 7: /*cnt 16384-65535*/ |
161 | case 7: /* cnt 16384 - 65535 */ |
162 | case 8: /*cnt 65536-(256K-1)*/ |
162 | case 8: /* cnt 65536 - (256K - 1) */ |
163 | ps = PAGE_WIDTH+14; |
163 | ps = PAGE_WIDTH + 14; |
164 | va &= ~((1<<ps)-1); |
164 | va &= ~((1 << ps) - 1); |
165 | break; |
165 | break; |
166 | default: |
166 | default: |
167 | ps=PAGE_WIDTH+18; |
167 | ps = PAGE_WIDTH + 18; |
168 | va&=~((1<<ps)-1); |
168 | va &= ~((1 << ps) - 1); |
169 | break; |
169 | break; |
170 | } |
170 | } |
171 | for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { |
171 | for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) |
172 | asm volatile ( |
- | |
173 | "ptc.l %0,%1;;" |
- | |
174 | : |
- | |
175 | : "r" (va), "r" (ps<<2) |
172 | asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2)); |
176 | ); |
- | |
177 | } |
- | |
178 | srlz_d(); |
173 | srlz_d(); |
179 | srlz_i(); |
174 | srlz_i(); |
180 | 175 | ||
181 | if (restore_rr) { |
176 | if (restore_rr) { |
182 | rr_write(VA2VRN(va), rr.word); |
177 | rr_write(VA2VRN(va), rr.word); |
183 | srlz_d(); |
178 | srlz_d(); |
184 | srlz_i(); |
179 | srlz_i(); |
185 | } |
180 | } |
186 | } |
181 | } |
187 | 182 | ||
188 | /** Insert data into data translation cache. |
183 | /** Insert data into data translation cache. |
189 | * |
184 | * |
190 | * @param va Virtual page address. |
185 | * @param va Virtual page address. |
191 | * @param asid Address space identifier. |
186 | * @param asid Address space identifier. |
192 | * @param entry The rest of TLB entry as required by TLB insertion format. |
187 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 188 | * format. |
|
193 | */ |
189 | */ |
194 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
190 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
195 | { |
191 | { |
196 | tc_mapping_insert(va, asid, entry, true); |
192 | tc_mapping_insert(va, asid, entry, true); |
197 | } |
193 | } |
198 | 194 | ||
199 | /** Insert data into instruction translation cache. |
195 | /** Insert data into instruction translation cache. |
200 | * |
196 | * |
201 | * @param va Virtual page address. |
197 | * @param va Virtual page address. |
202 | * @param asid Address space identifier. |
198 | * @param asid Address space identifier. |
203 | * @param entry The rest of TLB entry as required by TLB insertion format. |
199 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 200 | * format. |
|
204 | */ |
201 | */ |
205 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
202 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
206 | { |
203 | { |
207 | tc_mapping_insert(va, asid, entry, false); |
204 | tc_mapping_insert(va, asid, entry, false); |
208 | } |
205 | } |
209 | 206 | ||
210 | /** Insert data into instruction or data translation cache. |
207 | /** Insert data into instruction or data translation cache. |
211 | * |
208 | * |
212 | * @param va Virtual page address. |
209 | * @param va Virtual page address. |
213 | * @param asid Address space identifier. |
210 | * @param asid Address space identifier. |
214 | * @param entry The rest of TLB entry as required by TLB insertion format. |
211 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 212 | * format. |
|
215 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
213 | * @param dtc If true, insert into data translation cache, use |
- | 214 | * instruction translation cache otherwise. |
|
216 | */ |
215 | */ |
217 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
216 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
218 | { |
217 | { |
219 | region_register rr; |
218 | region_register rr; |
220 | bool restore_rr = false; |
219 | bool restore_rr = false; |
221 | 220 | ||
222 | rr.word = rr_read(VA2VRN(va)); |
221 | rr.word = rr_read(VA2VRN(va)); |
223 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
222 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
224 | /* |
223 | /* |
225 | * The selected region register does not contain required RID. |
224 | * The selected region register does not contain required RID. |
226 | * Save the old content of the register and replace the RID. |
225 | * Save the old content of the register and replace the RID. |
227 | */ |
226 | */ |
228 | region_register rr0; |
227 | region_register rr0; |
229 | 228 | ||
230 | rr0 = rr; |
229 | rr0 = rr; |
231 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
230 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
232 | rr_write(VA2VRN(va), rr0.word); |
231 | rr_write(VA2VRN(va), rr0.word); |
233 | srlz_d(); |
232 | srlz_d(); |
234 | srlz_i(); |
233 | srlz_i(); |
235 | } |
234 | } |
236 | 235 | ||
237 | asm volatile ( |
236 | asm volatile ( |
238 | "mov r8=psr;;\n" |
237 | "mov r8 = psr;;\n" |
239 | "rsm %0;;\n" /* PSR_IC_MASK */ |
238 | "rsm %0;;\n" /* PSR_IC_MASK */ |
240 | "srlz.d;;\n" |
239 | "srlz.d;;\n" |
241 | "srlz.i;;\n" |
240 | "srlz.i;;\n" |
242 | "mov cr.ifa=%1\n" /* va */ |
241 | "mov cr.ifa = %1\n" /* va */ |
243 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
242 | "mov cr.itir = %2;;\n" /* entry.word[1] */ |
244 | "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
243 | "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
245 | "(p6) itc.i %3;;\n" |
244 | "(p6) itc.i %3;;\n" |
246 | "(p7) itc.d %3;;\n" |
245 | "(p7) itc.d %3;;\n" |
247 | "mov psr.l=r8;;\n" |
246 | "mov psr.l = r8;;\n" |
248 | "srlz.d;;\n" |
247 | "srlz.d;;\n" |
249 | : |
248 | : |
250 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc) |
249 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
- | 250 | "r" (entry.word[0]), "r" (dtc) |
|
251 | : "p6", "p7", "r8" |
251 | : "p6", "p7", "r8" |
252 | ); |
252 | ); |
253 | 253 | ||
254 | if (restore_rr) { |
254 | if (restore_rr) { |
255 | rr_write(VA2VRN(va), rr.word); |
255 | rr_write(VA2VRN(va), rr.word); |
256 | srlz_d(); |
256 | srlz_d(); |
257 | srlz_i(); |
257 | srlz_i(); |
258 | } |
258 | } |
259 | } |
259 | } |
260 | 260 | ||
261 | /** Insert data into instruction translation register. |
261 | /** Insert data into instruction translation register. |
262 | * |
262 | * |
263 | * @param va Virtual page address. |
263 | * @param va Virtual page address. |
264 | * @param asid Address space identifier. |
264 | * @param asid Address space identifier. |
265 | * @param entry The rest of TLB entry as required by TLB insertion format. |
265 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 266 | * format. |
|
266 | * @param tr Translation register. |
267 | * @param tr Translation register. |
267 | */ |
268 | */ |
- | 269 | void |
|
268 | void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
270 | itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
269 | { |
271 | { |
270 | tr_mapping_insert(va, asid, entry, false, tr); |
272 | tr_mapping_insert(va, asid, entry, false, tr); |
271 | } |
273 | } |
272 | 274 | ||
273 | /** Insert data into data translation register. |
275 | /** Insert data into data translation register. |
274 | * |
276 | * |
275 | * @param va Virtual page address. |
277 | * @param va Virtual page address. |
276 | * @param asid Address space identifier. |
278 | * @param asid Address space identifier. |
277 | * @param entry The rest of TLB entry as required by TLB insertion format. |
279 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 280 | * format. |
|
278 | * @param tr Translation register. |
281 | * @param tr Translation register. |
279 | */ |
282 | */ |
- | 283 | void |
|
280 | void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
284 | dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
281 | { |
285 | { |
282 | tr_mapping_insert(va, asid, entry, true, tr); |
286 | tr_mapping_insert(va, asid, entry, true, tr); |
283 | } |
287 | } |
284 | 288 | ||
285 | /** Insert data into instruction or data translation register. |
289 | /** Insert data into instruction or data translation register. |
286 | * |
290 | * |
287 | * @param va Virtual page address. |
291 | * @param va Virtual page address. |
288 | * @param asid Address space identifier. |
292 | * @param asid Address space identifier. |
289 | * @param entry The rest of TLB entry as required by TLB insertion format. |
293 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 294 | * format. |
|
290 | * @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
295 | * @param dtr If true, insert into data translation register, use |
- | 296 | * instruction translation register otherwise. |
|
291 | * @param tr Translation register. |
297 | * @param tr Translation register. |
292 | */ |
298 | */ |
- | 299 | void |
|
293 | void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
300 | tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, |
- | 301 | index_t tr) |
|
294 | { |
302 | { |
295 | region_register rr; |
303 | region_register rr; |
296 | bool restore_rr = false; |
304 | bool restore_rr = false; |
297 | 305 | ||
298 | rr.word = rr_read(VA2VRN(va)); |
306 | rr.word = rr_read(VA2VRN(va)); |
299 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
307 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
300 | /* |
308 | /* |
301 | * The selected region register does not contain required RID. |
309 | * The selected region register does not contain required RID. |
302 | * Save the old content of the register and replace the RID. |
310 | * Save the old content of the register and replace the RID. |
303 | */ |
311 | */ |
304 | region_register rr0; |
312 | region_register rr0; |
305 | 313 | ||
306 | rr0 = rr; |
314 | rr0 = rr; |
307 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
315 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
308 | rr_write(VA2VRN(va), rr0.word); |
316 | rr_write(VA2VRN(va), rr0.word); |
309 | srlz_d(); |
317 | srlz_d(); |
310 | srlz_i(); |
318 | srlz_i(); |
311 | } |
319 | } |
312 | 320 | ||
313 | asm volatile ( |
321 | asm volatile ( |
314 | "mov r8=psr;;\n" |
322 | "mov r8 = psr;;\n" |
315 | "rsm %0;;\n" /* PSR_IC_MASK */ |
323 | "rsm %0;;\n" /* PSR_IC_MASK */ |
316 | "srlz.d;;\n" |
324 | "srlz.d;;\n" |
317 | "srlz.i;;\n" |
325 | "srlz.i;;\n" |
318 | "mov cr.ifa=%1\n" /* va */ |
326 | "mov cr.ifa = %1\n" /* va */ |
319 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
327 | "mov cr.itir = %2;;\n" /* entry.word[1] */ |
320 | "cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */ |
328 | "cmp.eq p6,p7 = %5,r0;;\n" /* decide between itr and dtr */ |
321 | "(p6) itr.i itr[%4]=%3;;\n" |
329 | "(p6) itr.i itr[%4] = %3;;\n" |
322 | "(p7) itr.d dtr[%4]=%3;;\n" |
330 | "(p7) itr.d dtr[%4] = %3;;\n" |
323 | "mov psr.l=r8;;\n" |
331 | "mov psr.l = r8;;\n" |
324 | "srlz.d;;\n" |
332 | "srlz.d;;\n" |
325 | : |
333 | : |
326 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr) |
334 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
- | 335 | "r" (entry.word[0]), "r" (tr), "r" (dtr) |
|
327 | : "p6", "p7", "r8" |
336 | : "p6", "p7", "r8" |
328 | ); |
337 | ); |
329 | 338 | ||
330 | if (restore_rr) { |
339 | if (restore_rr) { |
331 | rr_write(VA2VRN(va), rr.word); |
340 | rr_write(VA2VRN(va), rr.word); |
332 | srlz_d(); |
341 | srlz_d(); |
333 | srlz_i(); |
342 | srlz_i(); |
334 | } |
343 | } |
335 | } |
344 | } |
336 | 345 | ||
337 | /** Insert data into DTLB. |
346 | /** Insert data into DTLB. |
338 | * |
347 | * |
339 | * @param page Virtual page address including VRN bits. |
348 | * @param page Virtual page address including VRN bits. |
340 | * @param frame Physical frame address. |
349 | * @param frame Physical frame address. |
341 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
350 | * @param dtr If true, insert into data translation register, use data |
- | 351 | * translation cache otherwise. |
|
342 | * @param tr Translation register if dtr is true, ignored otherwise. |
352 | * @param tr Translation register if dtr is true, ignored otherwise. |
343 | */ |
353 | */ |
- | 354 | void |
|
344 | void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr) |
355 | dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, |
- | 356 | index_t tr) |
|
345 | { |
357 | { |
346 | tlb_entry_t entry; |
358 | tlb_entry_t entry; |
347 | 359 | ||
348 | entry.word[0] = 0; |
360 | entry.word[0] = 0; |
349 | entry.word[1] = 0; |
361 | entry.word[1] = 0; |
350 | 362 | ||
351 | entry.p = true; /* present */ |
363 | entry.p = true; /* present */ |
352 | entry.ma = MA_WRITEBACK; |
364 | entry.ma = MA_WRITEBACK; |
353 | entry.a = true; /* already accessed */ |
365 | entry.a = true; /* already accessed */ |
354 | entry.d = true; /* already dirty */ |
366 | entry.d = true; /* already dirty */ |
355 | entry.pl = PL_KERNEL; |
367 | entry.pl = PL_KERNEL; |
356 | entry.ar = AR_READ | AR_WRITE; |
368 | entry.ar = AR_READ | AR_WRITE; |
357 | entry.ppn = frame >> PPN_SHIFT; |
369 | entry.ppn = frame >> PPN_SHIFT; |
358 | entry.ps = PAGE_WIDTH; |
370 | entry.ps = PAGE_WIDTH; |
359 | 371 | ||
360 | if (dtr) |
372 | if (dtr) |
361 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr); |
373 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr); |
362 | else |
374 | else |
363 | dtc_mapping_insert(page, ASID_KERNEL, entry); |
375 | dtc_mapping_insert(page, ASID_KERNEL, entry); |
364 | } |
376 | } |
365 | 377 | ||
366 | /** Purge kernel entries from DTR. |
378 | /** Purge kernel entries from DTR. |
367 | * |
379 | * |
368 | * Purge DTR entries used by the kernel. |
380 | * Purge DTR entries used by the kernel. |
369 | * |
381 | * |
370 | * @param page Virtual page address including VRN bits. |
382 | * @param page Virtual page address including VRN bits. |
371 | * @param width Width of the purge in bits. |
383 | * @param width Width of the purge in bits. |
372 | */ |
384 | */ |
373 | void dtr_purge(uintptr_t page, count_t width) |
385 | void dtr_purge(uintptr_t page, count_t width) |
374 | { |
386 | { |
375 | asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
387 | asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2)); |
376 | } |
388 | } |
377 | 389 | ||
378 | 390 | ||
379 | /** Copy content of PTE into data translation cache. |
391 | /** Copy content of PTE into data translation cache. |
380 | * |
392 | * |
381 | * @param t PTE. |
393 | * @param t PTE. |
382 | */ |
394 | */ |
383 | void dtc_pte_copy(pte_t *t) |
395 | void dtc_pte_copy(pte_t *t) |
384 | { |
396 | { |
385 | tlb_entry_t entry; |
397 | tlb_entry_t entry; |
386 | 398 | ||
387 | entry.word[0] = 0; |
399 | entry.word[0] = 0; |
388 | entry.word[1] = 0; |
400 | entry.word[1] = 0; |
389 | 401 | ||
390 | entry.p = t->p; |
402 | entry.p = t->p; |
391 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; |
403 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; |
392 | entry.a = t->a; |
404 | entry.a = t->a; |
393 | entry.d = t->d; |
405 | entry.d = t->d; |
394 | entry.pl = t->k ? PL_KERNEL : PL_USER; |
406 | entry.pl = t->k ? PL_KERNEL : PL_USER; |
395 | entry.ar = t->w ? AR_WRITE : AR_READ; |
407 | entry.ar = t->w ? AR_WRITE : AR_READ; |
396 | entry.ppn = t->frame >> PPN_SHIFT; |
408 | entry.ppn = t->frame >> PPN_SHIFT; |
397 | entry.ps = PAGE_WIDTH; |
409 | entry.ps = PAGE_WIDTH; |
398 | 410 | ||
399 | dtc_mapping_insert(t->page, t->as->asid, entry); |
411 | dtc_mapping_insert(t->page, t->as->asid, entry); |
400 | #ifdef CONFIG_VHPT |
412 | #ifdef CONFIG_VHPT |
401 | vhpt_mapping_insert(t->page, t->as->asid, entry); |
413 | vhpt_mapping_insert(t->page, t->as->asid, entry); |
402 | #endif |
414 | #endif |
403 | } |
415 | } |
404 | 416 | ||
405 | /** Copy content of PTE into instruction translation cache. |
417 | /** Copy content of PTE into instruction translation cache. |
406 | * |
418 | * |
407 | * @param t PTE. |
419 | * @param t PTE. |
408 | */ |
420 | */ |
409 | void itc_pte_copy(pte_t *t) |
421 | void itc_pte_copy(pte_t *t) |
410 | { |
422 | { |
411 | tlb_entry_t entry; |
423 | tlb_entry_t entry; |
412 | 424 | ||
413 | entry.word[0] = 0; |
425 | entry.word[0] = 0; |
414 | entry.word[1] = 0; |
426 | entry.word[1] = 0; |
415 | 427 | ||
416 | ASSERT(t->x); |
428 | ASSERT(t->x); |
417 | 429 | ||
418 | entry.p = t->p; |
430 | entry.p = t->p; |
419 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; |
431 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; |
420 | entry.a = t->a; |
432 | entry.a = t->a; |
421 | entry.pl = t->k ? PL_KERNEL : PL_USER; |
433 | entry.pl = t->k ? PL_KERNEL : PL_USER; |
422 | entry.ar = t->x ? (AR_EXECUTE | AR_READ) : AR_READ; |
434 | entry.ar = t->x ? (AR_EXECUTE | AR_READ) : AR_READ; |
423 | entry.ppn = t->frame >> PPN_SHIFT; |
435 | entry.ppn = t->frame >> PPN_SHIFT; |
424 | entry.ps = PAGE_WIDTH; |
436 | entry.ps = PAGE_WIDTH; |
425 | 437 | ||
426 | itc_mapping_insert(t->page, t->as->asid, entry); |
438 | itc_mapping_insert(t->page, t->as->asid, entry); |
427 | #ifdef CONFIG_VHPT |
439 | #ifdef CONFIG_VHPT |
428 | vhpt_mapping_insert(t->page, t->as->asid, entry); |
440 | vhpt_mapping_insert(t->page, t->as->asid, entry); |
429 | #endif |
441 | #endif |
430 | } |
442 | } |
431 | 443 | ||
432 | /** Instruction TLB fault handler for faults with VHPT turned off. |
444 | /** Instruction TLB fault handler for faults with VHPT turned off. |
433 | * |
445 | * |
434 | * @param vector Interruption vector. |
446 | * @param vector Interruption vector. |
435 | * @param istate Structure with saved interruption state. |
447 | * @param istate Structure with saved interruption state. |
436 | */ |
448 | */ |
437 | void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) |
449 | void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) |
438 | { |
450 | { |
439 | region_register rr; |
451 | region_register rr; |
440 | rid_t rid; |
452 | rid_t rid; |
441 | uintptr_t va; |
453 | uintptr_t va; |
442 | pte_t *t; |
454 | pte_t *t; |
443 | 455 | ||
444 | va = istate->cr_ifa; /* faulting address */ |
456 | va = istate->cr_ifa; /* faulting address */ |
445 | rr.word = rr_read(VA2VRN(va)); |
457 | rr.word = rr_read(VA2VRN(va)); |
446 | rid = rr.map.rid; |
458 | rid = rr.map.rid; |
447 | 459 | ||
448 | page_table_lock(AS, true); |
460 | page_table_lock(AS, true); |
449 | t = page_mapping_find(AS, va); |
461 | t = page_mapping_find(AS, va); |
450 | if (t) { |
462 | if (t) { |
451 | /* |
463 | /* |
452 | * The mapping was found in software page hash table. |
464 | * The mapping was found in software page hash table. |
453 | * Insert it into data translation cache. |
465 | * Insert it into data translation cache. |
454 | */ |
466 | */ |
455 | itc_pte_copy(t); |
467 | itc_pte_copy(t); |
456 | page_table_unlock(AS, true); |
468 | page_table_unlock(AS, true); |
457 | } else { |
469 | } else { |
458 | /* |
470 | /* |
459 | * Forward the page fault to address space page fault handler. |
471 | * Forward the page fault to address space page fault handler. |
460 | */ |
472 | */ |
461 | page_table_unlock(AS, true); |
473 | page_table_unlock(AS, true); |
462 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
474 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
463 | fault_if_from_uspace(istate,"Page fault at %p",va); |
475 | fault_if_from_uspace(istate,"Page fault at %p",va); |
464 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
476 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
- | 477 | istate->cr_iip); |
|
465 | } |
478 | } |
466 | } |
479 | } |
467 | } |
480 | } |
468 | 481 | ||
469 | - | ||
470 | - | ||
471 | static int is_io_page_accessible(int page) |
482 | static int is_io_page_accessible(int page) |
472 | { |
483 | { |
- | 484 | if (TASK->arch.iomap) |
|
473 | if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page); |
485 | return bitmap_get(TASK->arch.iomap,page); |
- | 486 | else |
|
474 | else return 0; |
487 | return 0; |
475 | } |
488 | } |
476 | 489 | ||
477 | #define IO_FRAME_BASE 0xFFFFC000000 |
490 | #define IO_FRAME_BASE 0xFFFFC000000 |
478 | 491 | ||
- | 492 | /** |
|
479 | /** There is special handling of memmaped lagacy io, because |
493 | * There is special handling of memory mapped legacy io, because of 4KB sized |
480 | * of 4KB sized access |
- | |
481 | * only for userspace |
494 | * access for userspace. |
482 | * |
- | |
483 | * @param va virtual address of page fault |
- | |
484 | * @param istate Structure with saved interruption state. |
- | |
485 | * |
495 | * |
- | 496 | * @param va Virtual address of page fault. |
|
- | 497 | * @param istate Structure with saved interruption state. |
|
486 | * |
498 | * |
487 | * @return 1 on success, 0 on fail |
499 | * @return One on success, zero on failure. |
488 | */ |
500 | */ |
489 | static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) |
501 | static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) |
490 | { |
502 | { |
491 | if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH))) |
503 | if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) { |
492 | if(TASK){ |
504 | if (TASK) { |
493 | - | ||
494 | uint64_t io_page=(va & ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH); |
505 | uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >> |
- | 506 | USPACE_IO_PAGE_WIDTH; |
|
- | 507 | ||
495 | if(is_io_page_accessible(io_page)){ |
508 | if (is_io_page_accessible(io_page)) { |
496 | uint64_t page,frame; |
509 | uint64_t page, frame; |
497 | 510 | ||
- | 511 | page = IO_OFFSET + |
|
498 | page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
512 | (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
- | 513 | frame = IO_FRAME_BASE + |
|
499 | frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
514 | (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
500 | - | ||
501 | 515 | ||
502 | tlb_entry_t entry; |
516 | tlb_entry_t entry; |
503 | 517 | ||
504 | entry.word[0] = 0; |
518 | entry.word[0] = 0; |
505 | entry.word[1] = 0; |
519 | entry.word[1] = 0; |
506 | 520 | ||
507 | entry.p = true; /* present */ |
521 | entry.p = true; /* present */ |
508 | entry.ma = MA_UNCACHEABLE; |
522 | entry.ma = MA_UNCACHEABLE; |
509 | entry.a = true; /* already accessed */ |
523 | entry.a = true; /* already accessed */ |
510 | entry.d = true; /* already dirty */ |
524 | entry.d = true; /* already dirty */ |
511 | entry.pl = PL_USER; |
525 | entry.pl = PL_USER; |
512 | entry.ar = AR_READ | AR_WRITE; |
526 | entry.ar = AR_READ | AR_WRITE; |
513 | entry.ppn = frame >> PPN_SHIFT; |
527 | entry.ppn = frame >> PPN_SHIFT; |
514 | entry.ps = USPACE_IO_PAGE_WIDTH; |
528 | entry.ps = USPACE_IO_PAGE_WIDTH; |
515 | 529 | ||
516 | dtc_mapping_insert(page, TASK->as->asid, entry); |
530 | dtc_mapping_insert(page, TASK->as->asid, entry); |
517 | return 1; |
531 | return 1; |
518 | }else { |
532 | } else { |
519 | fault_if_from_uspace(istate,"IO access fault at %p",va); |
533 | fault_if_from_uspace(istate, |
520 | return 0; |
534 | "IO access fault at %p", va); |
521 | } |
535 | } |
522 | } else |
536 | } |
523 | return 0; |
- | |
524 | else |
537 | } |
525 | return 0; |
- | |
526 | 538 | ||
527 | return 0; |
539 | return 0; |
528 | - | ||
529 | } |
540 | } |
530 | 541 | ||
531 | - | ||
532 | - | ||
533 | - | ||
534 | /** Data TLB fault handler for faults with VHPT turned off. |
542 | /** Data TLB fault handler for faults with VHPT turned off. |
535 | * |
543 | * |
536 | * @param vector Interruption vector. |
544 | * @param vector Interruption vector. |
537 | * @param istate Structure with saved interruption state. |
545 | * @param istate Structure with saved interruption state. |
538 | */ |
546 | */ |
539 | void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) |
547 | void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) |
540 | { |
548 | { |
541 | region_register rr; |
549 | region_register rr; |
542 | rid_t rid; |
550 | rid_t rid; |
543 | uintptr_t va; |
551 | uintptr_t va; |
544 | pte_t *t; |
552 | pte_t *t; |
545 | 553 | ||
546 | va = istate->cr_ifa; /* faulting address */ |
554 | va = istate->cr_ifa; /* faulting address */ |
547 | rr.word = rr_read(VA2VRN(va)); |
555 | rr.word = rr_read(VA2VRN(va)); |
548 | rid = rr.map.rid; |
556 | rid = rr.map.rid; |
549 | if (RID2ASID(rid) == ASID_KERNEL) { |
557 | if (RID2ASID(rid) == ASID_KERNEL) { |
550 | if (VA2VRN(va) == VRN_KERNEL) { |
558 | if (VA2VRN(va) == VRN_KERNEL) { |
551 | /* |
559 | /* |
552 | * Provide KA2PA(identity) mapping for faulting piece of |
560 | * Provide KA2PA(identity) mapping for faulting piece of |
553 | * kernel address space. |
561 | * kernel address space. |
554 | */ |
562 | */ |
555 | dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0); |
563 | dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0); |
556 | return; |
564 | return; |
557 | } |
565 | } |
558 | } |
566 | } |
559 | 567 | ||
560 | page_table_lock(AS, true); |
568 | page_table_lock(AS, true); |
561 | t = page_mapping_find(AS, va); |
569 | t = page_mapping_find(AS, va); |
562 | if (t) { |
570 | if (t) { |
563 | /* |
571 | /* |
564 | * The mapping was found in the software page hash table. |
572 | * The mapping was found in the software page hash table. |
565 | * Insert it into data translation cache. |
573 | * Insert it into data translation cache. |
566 | */ |
574 | */ |
567 | dtc_pte_copy(t); |
575 | dtc_pte_copy(t); |
568 | page_table_unlock(AS, true); |
576 | page_table_unlock(AS, true); |
569 | } else { |
577 | } else { |
570 | page_table_unlock(AS, true); |
578 | page_table_unlock(AS, true); |
571 | if (try_memmap_io_insertion(va,istate)) return; |
579 | if (try_memmap_io_insertion(va, istate)) |
- | 580 | return; |
|
572 | /* |
581 | /* |
573 | * Forward the page fault to the address space page fault handler. |
582 | * Forward the page fault to the address space page fault |
- | 583 | * handler. |
|
574 | */ |
584 | */ |
575 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
585 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
576 | fault_if_from_uspace(istate,"Page fault at %p",va); |
586 | fault_if_from_uspace(istate,"Page fault at %p",va); |
577 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
587 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
- | 588 | istate->cr_iip); |
|
578 | } |
589 | } |
579 | } |
590 | } |
580 | } |
591 | } |
581 | 592 | ||
582 | /** Data nested TLB fault handler. |
593 | /** Data nested TLB fault handler. |
583 | * |
594 | * |
584 | * This fault should not occur. |
595 | * This fault should not occur. |
585 | * |
596 | * |
586 | * @param vector Interruption vector. |
597 | * @param vector Interruption vector. |
587 | * @param istate Structure with saved interruption state. |
598 | * @param istate Structure with saved interruption state. |
588 | */ |
599 | */ |
589 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
600 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
590 | { |
601 | { |
591 | panic("%s\n", __func__); |
602 | panic("%s\n", __func__); |
592 | } |
603 | } |
593 | 604 | ||
594 | /** Data Dirty bit fault handler. |
605 | /** Data Dirty bit fault handler. |
595 | * |
606 | * |
596 | * @param vector Interruption vector. |
607 | * @param vector Interruption vector. |
597 | * @param istate Structure with saved interruption state. |
608 | * @param istate Structure with saved interruption state. |
598 | */ |
609 | */ |
599 | void data_dirty_bit_fault(uint64_t vector, istate_t *istate) |
610 | void data_dirty_bit_fault(uint64_t vector, istate_t *istate) |
600 | { |
611 | { |
601 | region_register rr; |
612 | region_register rr; |
602 | rid_t rid; |
613 | rid_t rid; |
603 | uintptr_t va; |
614 | uintptr_t va; |
604 | pte_t *t; |
615 | pte_t *t; |
605 | 616 | ||
606 | va = istate->cr_ifa; /* faulting address */ |
617 | va = istate->cr_ifa; /* faulting address */ |
607 | rr.word = rr_read(VA2VRN(va)); |
618 | rr.word = rr_read(VA2VRN(va)); |
608 | rid = rr.map.rid; |
619 | rid = rr.map.rid; |
609 | 620 | ||
610 | page_table_lock(AS, true); |
621 | page_table_lock(AS, true); |
611 | t = page_mapping_find(AS, va); |
622 | t = page_mapping_find(AS, va); |
612 | ASSERT(t && t->p); |
623 | ASSERT(t && t->p); |
613 | if (t && t->p && t->w) { |
624 | if (t && t->p && t->w) { |
614 | /* |
625 | /* |
615 | * Update the Dirty bit in page tables and reinsert |
626 | * Update the Dirty bit in page tables and reinsert |
616 | * the mapping into DTC. |
627 | * the mapping into DTC. |
617 | */ |
628 | */ |
618 | t->d = true; |
629 | t->d = true; |
619 | dtc_pte_copy(t); |
630 | dtc_pte_copy(t); |
620 | } else { |
631 | } else { |
621 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
632 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
622 | fault_if_from_uspace(istate,"Page fault at %p",va); |
633 | fault_if_from_uspace(istate,"Page fault at %p",va); |
623 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
634 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
624 | t->d = true; |
- | |
625 | dtc_pte_copy(t); |
635 | istate->cr_iip); |
626 | } |
636 | } |
627 | } |
637 | } |
628 | page_table_unlock(AS, true); |
638 | page_table_unlock(AS, true); |
629 | } |
639 | } |
630 | 640 | ||
631 | /** Instruction access bit fault handler. |
641 | /** Instruction access bit fault handler. |
632 | * |
642 | * |
633 | * @param vector Interruption vector. |
643 | * @param vector Interruption vector. |
634 | * @param istate Structure with saved interruption state. |
644 | * @param istate Structure with saved interruption state. |
635 | */ |
645 | */ |
636 | void instruction_access_bit_fault(uint64_t vector, istate_t *istate) |
646 | void instruction_access_bit_fault(uint64_t vector, istate_t *istate) |
637 | { |
647 | { |
638 | region_register rr; |
648 | region_register rr; |
639 | rid_t rid; |
649 | rid_t rid; |
640 | uintptr_t va; |
650 | uintptr_t va; |
641 | pte_t *t; |
651 | pte_t *t; |
642 | 652 | ||
643 | va = istate->cr_ifa; /* faulting address */ |
653 | va = istate->cr_ifa; /* faulting address */ |
644 | rr.word = rr_read(VA2VRN(va)); |
654 | rr.word = rr_read(VA2VRN(va)); |
645 | rid = rr.map.rid; |
655 | rid = rr.map.rid; |
646 | 656 | ||
647 | page_table_lock(AS, true); |
657 | page_table_lock(AS, true); |
648 | t = page_mapping_find(AS, va); |
658 | t = page_mapping_find(AS, va); |
649 | ASSERT(t && t->p); |
659 | ASSERT(t && t->p); |
650 | if (t && t->p && t->x) { |
660 | if (t && t->p && t->x) { |
651 | /* |
661 | /* |
652 | * Update the Accessed bit in page tables and reinsert |
662 | * Update the Accessed bit in page tables and reinsert |
653 | * the mapping into ITC. |
663 | * the mapping into ITC. |
654 | */ |
664 | */ |
655 | t->a = true; |
665 | t->a = true; |
656 | itc_pte_copy(t); |
666 | itc_pte_copy(t); |
657 | } else { |
667 | } else { |
658 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
668 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
659 | fault_if_from_uspace(istate,"Page fault at %p",va); |
669 | fault_if_from_uspace(istate, "Page fault at %p", va); |
660 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
670 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
661 | t->a = true; |
- | |
662 | itc_pte_copy(t); |
671 | istate->cr_iip); |
663 | } |
672 | } |
664 | } |
673 | } |
665 | page_table_unlock(AS, true); |
674 | page_table_unlock(AS, true); |
666 | } |
675 | } |
667 | 676 | ||
668 | /** Data access bit fault handler. |
677 | /** Data access bit fault handler. |
669 | * |
678 | * |
670 | * @param vector Interruption vector. |
679 | * @param vector Interruption vector. |
671 | * @param istate Structure with saved interruption state. |
680 | * @param istate Structure with saved interruption state. |
672 | */ |
681 | */ |
673 | void data_access_bit_fault(uint64_t vector, istate_t *istate) |
682 | void data_access_bit_fault(uint64_t vector, istate_t *istate) |
674 | { |
683 | { |
675 | region_register rr; |
684 | region_register rr; |
676 | rid_t rid; |
685 | rid_t rid; |
677 | uintptr_t va; |
686 | uintptr_t va; |
678 | pte_t *t; |
687 | pte_t *t; |
679 | 688 | ||
680 | va = istate->cr_ifa; /* faulting address */ |
689 | va = istate->cr_ifa; /* faulting address */ |
681 | rr.word = rr_read(VA2VRN(va)); |
690 | rr.word = rr_read(VA2VRN(va)); |
682 | rid = rr.map.rid; |
691 | rid = rr.map.rid; |
683 | 692 | ||
684 | page_table_lock(AS, true); |
693 | page_table_lock(AS, true); |
685 | t = page_mapping_find(AS, va); |
694 | t = page_mapping_find(AS, va); |
686 | ASSERT(t && t->p); |
695 | ASSERT(t && t->p); |
687 | if (t && t->p) { |
696 | if (t && t->p) { |
688 | /* |
697 | /* |
689 | * Update the Accessed bit in page tables and reinsert |
698 | * Update the Accessed bit in page tables and reinsert |
690 | * the mapping into DTC. |
699 | * the mapping into DTC. |
691 | */ |
700 | */ |
692 | t->a = true; |
701 | t->a = true; |
693 | dtc_pte_copy(t); |
702 | dtc_pte_copy(t); |
694 | } else { |
703 | } else { |
695 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
704 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
696 | fault_if_from_uspace(istate,"Page fault at %p",va); |
705 | fault_if_from_uspace(istate, "Page fault at %p", va); |
697 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
706 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
698 | t->a = true; |
- | |
699 | itc_pte_copy(t); |
707 | istate->cr_iip); |
700 | } |
708 | } |
701 | } |
709 | } |
702 | page_table_unlock(AS, true); |
710 | page_table_unlock(AS, true); |
703 | } |
711 | } |
704 | 712 | ||
705 | /** Page not present fault handler. |
713 | /** Page not present fault handler. |
706 | * |
714 | * |
707 | * @param vector Interruption vector. |
715 | * @param vector Interruption vector. |
708 | * @param istate Structure with saved interruption state. |
716 | * @param istate Structure with saved interruption state. |
709 | */ |
717 | */ |
710 | void page_not_present(uint64_t vector, istate_t *istate) |
718 | void page_not_present(uint64_t vector, istate_t *istate) |
711 | { |
719 | { |
712 | region_register rr; |
720 | region_register rr; |
713 | rid_t rid; |
721 | rid_t rid; |
714 | uintptr_t va; |
722 | uintptr_t va; |
715 | pte_t *t; |
723 | pte_t *t; |
716 | 724 | ||
717 | va = istate->cr_ifa; /* faulting address */ |
725 | va = istate->cr_ifa; /* faulting address */ |
718 | rr.word = rr_read(VA2VRN(va)); |
726 | rr.word = rr_read(VA2VRN(va)); |
719 | rid = rr.map.rid; |
727 | rid = rr.map.rid; |
720 | 728 | ||
721 | page_table_lock(AS, true); |
729 | page_table_lock(AS, true); |
722 | t = page_mapping_find(AS, va); |
730 | t = page_mapping_find(AS, va); |
723 | ASSERT(t); |
731 | ASSERT(t); |
724 | 732 | ||
725 | if (t->p) { |
733 | if (t->p) { |
726 | /* |
734 | /* |
727 | * If the Present bit is set in page hash table, just copy it |
735 | * If the Present bit is set in page hash table, just copy it |
728 | * and update ITC/DTC. |
736 | * and update ITC/DTC. |
729 | */ |
737 | */ |
730 | if (t->x) |
738 | if (t->x) |
731 | itc_pte_copy(t); |
739 | itc_pte_copy(t); |
732 | else |
740 | else |
733 | dtc_pte_copy(t); |
741 | dtc_pte_copy(t); |
734 | page_table_unlock(AS, true); |
742 | page_table_unlock(AS, true); |
735 | } else { |
743 | } else { |
736 | page_table_unlock(AS, true); |
744 | page_table_unlock(AS, true); |
737 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
745 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
738 | fault_if_from_uspace(istate,"Page fault at %p",va); |
746 | fault_if_from_uspace(istate, "Page fault at %p", va); |
739 | panic("%s: va=%p, rid=%d\n", __func__, va, rid); |
747 | panic("%s: va=%p, rid=%d\n", __func__, va, rid); |
740 | } |
748 | } |
741 | } |
749 | } |
742 | } |
750 | } |
743 | 751 | ||
744 | /** @} |
752 | /** @} |
745 | */ |
753 | */ |
746 | 754 |