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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (C) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /* |
29 | /* |
30 | * TLB management. |
30 | * TLB management. |
31 | */ |
31 | */ |
32 | 32 | ||
33 | #include <mm/tlb.h> |
33 | #include <mm/tlb.h> |
- | 34 | #include <mm/asid.h> |
|
34 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
- | 36 | #include <arch/mm/page.h> |
|
35 | #include <arch/barrier.h> |
37 | #include <arch/barrier.h> |
36 | #include <arch/interrupt.h> |
38 | #include <arch/interrupt.h> |
37 | #include <typedefs.h> |
39 | #include <typedefs.h> |
38 | #include <panic.h> |
40 | #include <panic.h> |
- | 41 | #include <print.h> |
|
39 | 42 | ||
40 | /** Invalidate all TLB entries. */ |
43 | /** Invalidate all TLB entries. */ |
41 | void tlb_invalidate_all(void) |
44 | void tlb_invalidate_all(void) |
42 | { |
45 | { |
43 | /* TODO */ |
46 | /* TODO */ |
44 | } |
47 | } |
45 | 48 | ||
46 | /** Invalidate entries belonging to an address space. |
49 | /** Invalidate entries belonging to an address space. |
47 | * |
50 | * |
48 | * @param asid Address space identifier. |
51 | * @param asid Address space identifier. |
49 | */ |
52 | */ |
50 | void tlb_invalidate_asid(asid_t asid) |
53 | void tlb_invalidate_asid(asid_t asid) |
51 | { |
54 | { |
52 | /* TODO */ |
55 | /* TODO */ |
53 | } |
56 | } |
54 | 57 | ||
55 | /** Insert data into data translation cache. |
58 | /** Insert data into data translation cache. |
56 | * |
59 | * |
57 | * @param va Virtual page address. |
60 | * @param va Virtual page address. |
58 | * @param asid Address space identifier. |
61 | * @param asid Address space identifier. |
59 | * @param entry The rest of TLB entry as required by TLB insertion format. |
62 | * @param entry The rest of TLB entry as required by TLB insertion format. |
60 | */ |
63 | */ |
61 | void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) { |
64 | void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) { |
62 | tc_mapping_insert(va, asid, entry, true); |
65 | tc_mapping_insert(va, asid, entry, true); |
63 | } |
66 | } |
64 | 67 | ||
65 | /** Insert data into instruction translation cache. |
68 | /** Insert data into instruction translation cache. |
66 | * |
69 | * |
67 | * @param va Virtual page address. |
70 | * @param va Virtual page address. |
68 | * @param asid Address space identifier. |
71 | * @param asid Address space identifier. |
69 | * @param entry The rest of TLB entry as required by TLB insertion format. |
72 | * @param entry The rest of TLB entry as required by TLB insertion format. |
70 | */ |
73 | */ |
71 | void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) { |
74 | void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) { |
72 | tc_mapping_insert(va, asid, entry, false); |
75 | tc_mapping_insert(va, asid, entry, false); |
73 | } |
76 | } |
74 | 77 | ||
75 | /** Insert data into instruction or data translation cache. |
78 | /** Insert data into instruction or data translation cache. |
76 | * |
79 | * |
77 | * @param va Virtual page address. |
80 | * @param va Virtual page address. |
78 | * @param asid Address space identifier. |
81 | * @param asid Address space identifier. |
79 | * @param entry The rest of TLB entry as required by TLB insertion format. |
82 | * @param entry The rest of TLB entry as required by TLB insertion format. |
80 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
83 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
81 | */ |
84 | */ |
82 | void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc) |
85 | void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc) |
83 | { |
86 | { |
84 | region_register rr; |
87 | region_register rr; |
85 | bool restore_rr = false; |
88 | bool restore_rr = false; |
86 | 89 | ||
87 | if (!(entry.not_present.p)) |
90 | if (!(entry.p)) |
88 | return; |
91 | return; |
89 | 92 | ||
90 | rr.word = rr_read(VA_REGION(va)); |
93 | rr.word = rr_read(VA2VRN(va)); |
91 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA_REGION(va))))) { |
94 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
92 | /* |
95 | /* |
93 | * The selected region register does not contain required RID. |
96 | * The selected region register does not contain required RID. |
94 | * Save the old content of the register and replace the RID. |
97 | * Save the old content of the register and replace the RID. |
95 | */ |
98 | */ |
96 | region_register rr0; |
99 | region_register rr0; |
97 | 100 | ||
98 | rr0 = rr; |
101 | rr0 = rr; |
99 | rr0.map.rid = ASID2RID(asid, VA_REGION(va)); |
102 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
100 | rr_write(VA_REGION(va), rr0.word); |
103 | rr_write(VA2VRN(va), rr0.word); |
101 | srlz_d(); |
104 | srlz_d(); |
102 | srlz_i(); |
105 | srlz_i(); |
103 | } |
106 | } |
104 | 107 | ||
105 | __asm__ volatile ( |
108 | __asm__ volatile ( |
106 | "mov r8=psr;;\n" |
109 | "mov r8=psr;;\n" |
107 | "rsm %0;;\n" /* PSR_IC_MASK */ |
110 | "rsm %0;;\n" /* PSR_IC_MASK */ |
108 | "srlz.d;;\n" |
111 | "srlz.d;;\n" |
109 | "srlz.i;;\n" |
112 | "srlz.i;;\n" |
110 | "mov cr.ifa=%1\n" /* va */ |
113 | "mov cr.ifa=%1\n" /* va */ |
111 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
114 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
112 | "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
115 | "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
113 | "(p6) itc.i %3;;\n" |
116 | "(p6) itc.i %3;;\n" |
114 | "(p7) itc.d %3;;\n" |
117 | "(p7) itc.d %3;;\n" |
115 | "mov psr.l=r8;;\n" |
118 | "mov psr.l=r8;;\n" |
116 | "srlz.d;;\n" |
119 | "srlz.d;;\n" |
117 | : |
120 | : |
118 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc) |
121 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc) |
119 | : "p6", "p7", "r8" |
122 | : "p6", "p7", "r8" |
120 | ); |
123 | ); |
121 | 124 | ||
122 | if (restore_rr) { |
125 | if (restore_rr) { |
123 | rr_write(VA_REGION(va),rr.word); |
126 | rr_write(VA2VRN(va), rr.word); |
124 | srlz_d(); |
127 | srlz_d(); |
125 | srlz_i(); |
128 | srlz_i(); |
126 | } |
129 | } |
127 | } |
130 | } |
128 | 131 | ||
129 | /** Insert data into instruction translation register. |
132 | /** Insert data into instruction translation register. |
130 | * |
133 | * |
131 | * @param va Virtual page address. |
134 | * @param va Virtual page address. |
132 | * @param asid Address space identifier. |
135 | * @param asid Address space identifier. |
133 | * @param entry The rest of TLB entry as required by TLB insertion format. |
136 | * @param entry The rest of TLB entry as required by TLB insertion format. |
134 | * @param tr Translation register. |
137 | * @param tr Translation register. |
135 | */ |
138 | */ |
136 | void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
139 | void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
137 | { |
140 | { |
138 | tr_mapping_insert(va, asid, entry, false, tr); |
141 | tr_mapping_insert(va, asid, entry, false, tr); |
139 | } |
142 | } |
140 | 143 | ||
141 | /** Insert data into data translation register. |
144 | /** Insert data into data translation register. |
142 | * |
145 | * |
143 | * @param va Virtual page address. |
146 | * @param va Virtual page address. |
144 | * @param asid Address space identifier. |
147 | * @param asid Address space identifier. |
145 | * @param entry The rest of TLB entry as required by TLB insertion format. |
148 | * @param entry The rest of TLB entry as required by TLB insertion format. |
146 | * @param tr Translation register. |
149 | * @param tr Translation register. |
147 | */ |
150 | */ |
148 | void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
151 | void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
149 | { |
152 | { |
150 | tr_mapping_insert(va, asid, entry, true, tr); |
153 | tr_mapping_insert(va, asid, entry, true, tr); |
151 | } |
154 | } |
152 | 155 | ||
153 | /** Insert data into instruction or data translation register. |
156 | /** Insert data into instruction or data translation register. |
154 | * |
157 | * |
155 | * @param va Virtual page address. |
158 | * @param va Virtual page address. |
156 | * @param asid Address space identifier. |
159 | * @param asid Address space identifier. |
157 | * @param entry The rest of TLB entry as required by TLB insertion format. |
160 | * @param entry The rest of TLB entry as required by TLB insertion format. |
158 | * @param dtc If true, insert into data translation register, use instruction translation register otherwise. |
161 | * @param dtc If true, insert into data translation register, use instruction translation register otherwise. |
159 | * @param tr Translation register. |
162 | * @param tr Translation register. |
160 | */ |
163 | */ |
161 | void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
164 | void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
162 | { |
165 | { |
163 | region_register rr; |
166 | region_register rr; |
164 | bool restore_rr = false; |
167 | bool restore_rr = false; |
165 | 168 | ||
166 | if (!(entry.not_present.p)) |
169 | if (!(entry.p)) |
167 | return; |
170 | return; |
168 | 171 | ||
169 | rr.word = rr_read(VA_REGION(va)); |
172 | rr.word = rr_read(VA2VRN(va)); |
170 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA_REGION(va))))) { |
173 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
171 | /* |
174 | /* |
172 | * The selected region register does not contain required RID. |
175 | * The selected region register does not contain required RID. |
173 | * Save the old content of the register and replace the RID. |
176 | * Save the old content of the register and replace the RID. |
174 | */ |
177 | */ |
175 | region_register rr0; |
178 | region_register rr0; |
176 | 179 | ||
177 | rr0 = rr; |
180 | rr0 = rr; |
178 | rr0.map.rid = ASID2RID(asid, VA_REGION(va)); |
181 | rr0.map.rid = ASID2RID(asid, VA2VRN(va)); |
179 | rr_write(VA_REGION(va), rr0.word); |
182 | rr_write(VA2VRN(va), rr0.word); |
180 | srlz_d(); |
183 | srlz_d(); |
181 | srlz_i(); |
184 | srlz_i(); |
182 | } |
185 | } |
183 | 186 | ||
184 | __asm__ volatile ( |
187 | __asm__ volatile ( |
185 | "mov r8=psr;;\n" |
188 | "mov r8=psr;;\n" |
186 | "rsm %0;;\n" /* PSR_IC_MASK */ |
189 | "rsm %0;;\n" /* PSR_IC_MASK */ |
187 | "srlz.d;;\n" |
190 | "srlz.d;;\n" |
188 | "srlz.i;;\n" |
191 | "srlz.i;;\n" |
189 | "mov cr.ifa=%1\n" /* va */ |
192 | "mov cr.ifa=%1\n" /* va */ |
190 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
193 | "mov cr.itir=%2;;\n" /* entry.word[1] */ |
191 | "cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */ |
194 | "cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */ |
192 | "(p6) itr.i itr[%4]=%3;;\n" |
195 | "(p6) itr.i itr[%4]=%3;;\n" |
193 | "(p7) itr.d dtr[%4]=%3;;\n" |
196 | "(p7) itr.d dtr[%4]=%3;;\n" |
194 | "mov psr.l=r8;;\n" |
197 | "mov psr.l=r8;;\n" |
195 | "srlz.d;;\n" |
198 | "srlz.d;;\n" |
196 | : |
199 | : |
197 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr) |
200 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr) |
198 | : "p6", "p7", "r8" |
201 | : "p6", "p7", "r8" |
199 | ); |
202 | ); |
200 | 203 | ||
201 | if (restore_rr) { |
204 | if (restore_rr) { |
202 | rr_write(VA_REGION(va),rr.word); |
205 | rr_write(VA2VRN(va), rr.word); |
203 | srlz_d(); |
206 | srlz_d(); |
204 | srlz_i(); |
207 | srlz_i(); |
205 | } |
208 | } |
206 | } |
209 | } |
207 | 210 | ||
- | 211 | /** Insert data into DTLB. |
|
- | 212 | * |
|
- | 213 | * @param va Virtual page address. |
|
- | 214 | * @param asid Address space identifier. |
|
- | 215 | * @param entry The rest of TLB entry as required by TLB insertion format. |
|
- | 216 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
|
- | 217 | * @param tr Translation register if dtr is true, ignored otherwise. |
|
- | 218 | */ |
|
- | 219 | void dtlb_mapping_insert(__address page, __address frame, bool dtr, index_t tr) |
|
- | 220 | { |
|
- | 221 | tlb_entry_t entry; |
|
- | 222 | ||
- | 223 | entry.word[0] = 0; |
|
- | 224 | entry.word[1] = 0; |
|
- | 225 | ||
- | 226 | entry.p = true; /* present */ |
|
- | 227 | entry.ma = MA_WRITEBACK; |
|
- | 228 | entry.a = true; /* already accessed */ |
|
- | 229 | entry.d = true; /* already dirty */ |
|
- | 230 | entry.pl = PL_KERNEL; |
|
- | 231 | entry.ar = AR_READ | AR_WRITE; |
|
- | 232 | entry.ppn = frame >> PPN_SHIFT; |
|
- | 233 | entry.ps = PAGE_WIDTH; |
|
- | 234 | ||
- | 235 | if (dtr) |
|
- | 236 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr); |
|
- | 237 | else |
|
- | 238 | dtc_mapping_insert(page, ASID_KERNEL, entry); |
|
- | 239 | } |
|
- | 240 | ||
208 | void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
241 | void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
209 | { |
242 | { |
210 | panic("%s\n", __FUNCTION__); |
243 | panic("%s\n", __FUNCTION__); |
211 | } |
244 | } |
212 | 245 | ||
- | 246 | /** Data TLB fault with VHPT turned off. |
|
- | 247 | * |
|
- | 248 | * @param vector Interruption vector. |
|
- | 249 | * @param pstate Structure with saved interruption state. |
|
- | 250 | */ |
|
213 | void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
251 | void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
214 | { |
252 | { |
- | 253 | region_register rr; |
|
- | 254 | rid_t rid; |
|
- | 255 | __address va; |
|
- | 256 | ||
- | 257 | va = pstate->cr_ifa; /* faulting address */ |
|
- | 258 | rr.word = rr_read(VA2VRN(va)); |
|
- | 259 | rid = rr.map.rid; |
|
- | 260 | if (RID2ASID(rid) == ASID_KERNEL) { |
|
- | 261 | if (VA2VRN(va) == VRN_KERNEL) { |
|
- | 262 | /* |
|
- | 263 | * Provide KA2PA(identity) mapping for faulting piece of |
|
- | 264 | * kernel address space. |
|
- | 265 | */ |
|
- | 266 | dtlb_mapping_insert(va, KA2PA(va), false, 0); |
|
- | 267 | return; |
|
- | 268 | } |
|
- | 269 | } |
|
215 | panic("%s: %P\n", __FUNCTION__, pstate->cr_ifa); |
270 | panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid); |
216 | } |
271 | } |
217 | 272 | ||
218 | void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
273 | void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate) |
219 | { |
274 | { |
220 | panic("%s\n", __FUNCTION__); |
275 | panic("%s\n", __FUNCTION__); |
221 | } |
276 | } |
222 | 277 | ||
223 | void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate) |
278 | void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate) |
224 | { |
279 | { |
225 | panic("%s\n", __FUNCTION__); |
280 | panic("%s\n", __FUNCTION__); |
226 | } |
281 | } |
227 | 282 | ||
228 | void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate) |
283 | void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate) |
229 | { |
284 | { |
230 | panic("%s\n", __FUNCTION__); |
285 | panic("%s\n", __FUNCTION__); |
231 | } |
286 | } |
232 | 287 | ||
233 | void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate) |
288 | void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate) |
234 | { |
289 | { |
235 | panic("%s\n", __FUNCTION__); |
290 | panic("%s\n", __FUNCTION__); |
236 | } |
291 | } |
237 | 292 | ||
238 | void page_not_present(__u64 vector, struct exception_regdump *pstate) |
293 | void page_not_present(__u64 vector, struct exception_regdump *pstate) |
239 | { |
294 | { |
240 | panic("%s\n", __FUNCTION__); |
295 | panic("%s\n", __FUNCTION__); |
241 | } |
296 | } |
242 | 297 |