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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch.h> |
29 | #include <arch.h> |
30 | #include <arch/ski/ski.h> |
30 | #include <arch/ski/ski.h> |
31 | #include <arch/drivers/it.h> |
31 | #include <arch/drivers/it.h> |
32 | #include <arch/interrupt.h> |
32 | #include <arch/interrupt.h> |
33 | #include <arch/barrier.h> |
33 | #include <arch/barrier.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
35 | #include <arch/register.h> |
35 | #include <arch/register.h> |
36 | #include <arch/types.h> |
36 | #include <arch/types.h> |
37 | #include <arch/context.h> |
37 | #include <arch/context.h> |
38 | #include <arch/stack.h> |
38 | #include <arch/stack.h> |
39 | #include <arch/mm/page.h> |
39 | #include <arch/mm/page.h> |
40 | #include <mm/as.h> |
40 | #include <mm/as.h> |
41 | #include <config.h> |
41 | #include <config.h> |
42 | #include <userspace.h> |
42 | #include <userspace.h> |
43 | #include <console/console.h> |
43 | #include <console/console.h> |
44 | #include <proc/thread.h> |
44 | #include <proc/uarg.h> |
45 | 45 | ||
46 | void arch_pre_mm_init(void) |
46 | void arch_pre_mm_init(void) |
47 | { |
47 | { |
48 | /* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
48 | /* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
49 | iva_write((__address) &ivt); |
49 | iva_write((__address) &ivt); |
50 | srlz_d(); |
50 | srlz_d(); |
51 | 51 | ||
52 | ski_init_console(); |
52 | ski_init_console(); |
53 | it_init(); |
53 | it_init(); |
54 | 54 | ||
55 | /* Setup usermode */ |
55 | /* Setup usermode */ |
56 | init.cnt = 2; |
56 | init.cnt = 2; |
57 | init.tasks[0].addr = INIT0_ADDRESS; |
57 | init.tasks[0].addr = INIT0_ADDRESS; |
58 | init.tasks[0].size = INIT0_SIZE; |
58 | init.tasks[0].size = INIT0_SIZE; |
59 | init.tasks[1].addr = INIT1_ADDRESS; |
59 | init.tasks[1].addr = INIT1_ADDRESS; |
60 | init.tasks[1].size = INIT1_SIZE; |
60 | init.tasks[1].size = INIT1_SIZE; |
61 | } |
61 | } |
62 | 62 | ||
63 | void arch_post_mm_init(void) |
63 | void arch_post_mm_init(void) |
64 | { |
64 | { |
65 | } |
65 | } |
66 | 66 | ||
67 | void arch_pre_smp_init(void) |
67 | void arch_pre_smp_init(void) |
68 | { |
68 | { |
69 | } |
69 | } |
70 | 70 | ||
71 | void arch_post_smp_init(void) |
71 | void arch_post_smp_init(void) |
72 | { |
72 | { |
73 | } |
73 | } |
74 | 74 | ||
75 | /** Enter userspace and never return. */ |
75 | /** Enter userspace and never return. */ |
76 | void userspace(uspace_arg_t *uarg) |
76 | void userspace(uspace_arg_t *kernel_uarg) |
77 | { |
77 | { |
78 | psr_t psr; |
78 | psr_t psr; |
79 | rsc_t rsc; |
79 | rsc_t rsc; |
80 | 80 | ||
81 | psr.value = psr_read(); |
81 | psr.value = psr_read(); |
82 | psr.cpl = PL_USER; |
82 | psr.cpl = PL_USER; |
83 | psr.i = true; /* start with interrupts enabled */ |
83 | psr.i = true; /* start with interrupts enabled */ |
84 | psr.ic = true; |
84 | psr.ic = true; |
85 | psr.ri = 0; /* start with instruction #0 */ |
85 | psr.ri = 0; /* start with instruction #0 */ |
86 | psr.bn = 1; /* start in bank 0 */ |
86 | psr.bn = 1; /* start in bank 0 */ |
87 | 87 | ||
88 | __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); |
88 | __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); |
89 | rsc.loadrs = 0; |
89 | rsc.loadrs = 0; |
90 | rsc.be = false; |
90 | rsc.be = false; |
91 | rsc.pl = PL_USER; |
91 | rsc.pl = PL_USER; |
92 | rsc.mode = 3; /* eager mode */ |
92 | rsc.mode = 3; /* eager mode */ |
93 | 93 | ||
- | 94 | switch_to_userspace((__address) kernel_uarg->uspace_entry, |
|
94 | switch_to_userspace(uarg->uspace_entry, uarg->uspace_stack+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), uarg->uspace_stack, psr.value, rsc.value); |
95 | ((__address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), |
- | 96 | (__address) kernel_uarg->uspace_stack, |
|
- | 97 | (__address) kernel_uarg->uspace_uarg, |
|
- | 98 | psr.value, rsc.value); |
|
95 | 99 | ||
96 | while (1) { |
100 | while (1) { |
97 | ; |
101 | ; |
98 | } |
102 | } |
99 | } |
103 | } |
100 | 104 |