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/*
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/*
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 * Copyright (c) 2005 Jakub Jermar
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 * Copyright (c) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup ia64   
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/** @addtogroup ia64   
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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/** Interval Timer driver. */
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/** Interval Timer driver. */
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#include <arch/drivers/it.h>
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#include <arch/drivers/it.h>
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <time/clock.h>
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#include <time/clock.h>
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#include <ddi/irq.h>
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#include <ddi/irq.h>
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#include <ddi/device.h>
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#include <ddi/device.h>
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#include <arch.h>
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#include <arch.h>
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#define IT_SERVICE_CLOCKS 64
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#define IT_SERVICE_CLOCKS 64
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static irq_t it_irq;
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static irq_t it_irq;
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static irq_ownership_t it_claim(void);
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static irq_ownership_t it_claim(void);
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static void it_interrupt(irq_t *irq, void *arg, ...);
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static void it_interrupt(irq_t *irq, void *arg, ...);
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/** Initialize Interval Timer. */
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/** Initialize Interval Timer. */
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void it_init(void)
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void it_init(void)
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{
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{
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    cr_itv_t itv;
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    cr_itv_t itv;
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-
 
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    if(config.cpu_active==1)
-
 
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    {
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    irq_initialize(&it_irq);
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        irq_initialize(&it_irq);
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    it_irq.inr = INTERRUPT_TIMER;
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        it_irq.inr = INTERRUPT_TIMER;
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    it_irq.devno = device_assign_devno();
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        it_irq.devno = device_assign_devno();
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    it_irq.claim = it_claim;
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        it_irq.claim = it_claim;
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    it_irq.handler = it_interrupt;
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        it_irq.handler = it_interrupt;
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    irq_register(&it_irq);
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        irq_register(&it_irq);
-
 
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    }
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    /* initialize Interval Timer external interrupt vector */
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    /* initialize Interval Timer external interrupt vector */
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    itv.value = itv_read();
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    itv.value = itv_read();
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    itv.vector = INTERRUPT_TIMER;
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    itv.vector = INTERRUPT_TIMER;
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    itv.m = 0;
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    itv.m = 0;
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    itv_write(itv.value);
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    itv_write(itv.value);
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    /* set Interval Timer Counter to zero */
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    /* set Interval Timer Counter to zero */
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    itc_write(0);
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    itc_write(0);
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    /* generate first Interval Timer interrupt in IT_DELTA ticks */
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    /* generate first Interval Timer interrupt in IT_DELTA ticks */
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    itm_write(IT_DELTA);
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    itm_write(IT_DELTA);
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    /* propagate changes */
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    /* propagate changes */
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    srlz_d();
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    srlz_d();
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}
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}
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/** Always claim ownership for this IRQ.
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/** Always claim ownership for this IRQ.
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 *
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 *
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 * Other devices are responsible to avoid using INR 0.
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 * Other devices are responsible to avoid using INR 0.
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 *
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 *
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 * @return Always IRQ_ACCEPT.
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 * @return Always IRQ_ACCEPT.
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 */
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 */
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irq_ownership_t it_claim(void)
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irq_ownership_t it_claim(void)
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{
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{
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    return IRQ_ACCEPT;
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    return IRQ_ACCEPT;
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}
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}
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/** Process Interval Timer interrupt. */
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/** Process Interval Timer interrupt. */
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void it_interrupt(irq_t *irq, void *arg, ...)
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void it_interrupt(irq_t *irq, void *arg, ...)
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{
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{
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    int64_t c;
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    int64_t c;
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    int64_t m;
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    int64_t m;
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    eoi_write(EOI);
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    eoi_write(EOI);
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    m = itm_read();
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    m = itm_read();
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    while (1) {
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    while (1) {
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        c = itc_read();
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        c = itc_read();
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        c += IT_SERVICE_CLOCKS;
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        c += IT_SERVICE_CLOCKS;
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        m += IT_DELTA;
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        m += IT_DELTA;
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        if (m - c < 0)
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        if (m - c < 0)
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            CPU->missed_clock_ticks++;
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            CPU->missed_clock_ticks++;
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        else
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        else
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            break;
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            break;
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    }
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    }
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    itm_write(m);
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    itm_write(m);
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    srlz_d();               /* propagate changes */
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    srlz_d();               /* propagate changes */
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    /*
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    /*
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     * We are holding a lock which prevents preemption.
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     * We are holding a lock which prevents preemption.
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     * Release the lock, call clock() and reacquire the lock again.
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     * Release the lock, call clock() and reacquire the lock again.
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     */
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     */
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    spinlock_unlock(&irq->lock);   
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    spinlock_unlock(&irq->lock);   
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    clock();
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    clock();
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    spinlock_lock(&irq->lock);
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    spinlock_lock(&irq->lock);
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}
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}
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/** @}
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/** @}
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 */
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 */
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