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1 | # |
1 | # |
2 | # Copyright (c) 2005 Jakub Jermar |
2 | # Copyright (c) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/register.h> |
29 | #include <arch/register.h> |
30 | 30 | ||
31 | .text |
31 | .text |
32 | 32 | ||
33 | /** Copy memory from/to userspace. |
33 | /** Copy memory from/to userspace. |
34 | * |
34 | * |
35 | * This memcpy() has been taken from the assembler output of |
35 | * This memcpy() has been taken from the assembler output of |
36 | * the generic _memcpy() and modified to have the failover part. |
36 | * the generic _memcpy() and modified to have the failover part. |
37 | * |
37 | * |
38 | * @param in0 Destination address. |
38 | * @param in0 Destination address. |
39 | * @param in1 Source address. |
39 | * @param in1 Source address. |
40 | * @param in2 Number of byte to copy. |
40 | * @param in2 Number of byte to copy. |
41 | */ |
41 | */ |
42 | .global memcpy |
42 | .global memcpy |
43 | .global memcpy_from_uspace |
43 | .global memcpy_from_uspace |
44 | .global memcpy_to_uspace |
44 | .global memcpy_to_uspace |
45 | .global memcpy_from_uspace_failover_address |
45 | .global memcpy_from_uspace_failover_address |
46 | .global memcpy_to_uspace_failover_address |
46 | .global memcpy_to_uspace_failover_address |
47 | memcpy: |
47 | memcpy: |
48 | memcpy_from_uspace: |
48 | memcpy_from_uspace: |
49 | memcpy_to_uspace: |
49 | memcpy_to_uspace: |
50 | alloc loc0 = ar.pfs, 3, 1, 0, 0 |
50 | alloc loc0 = ar.pfs, 3, 1, 0, 0 |
51 | 51 | ||
52 | adds r14 = 7, in1 |
52 | adds r14 = 7, in1 |
53 | mov r2 = ar.lc |
53 | mov r2 = ar.lc |
54 | mov r8 = in0 |
54 | mov r8 = in0 |
55 | and r14 = -8, r14 ;; |
55 | and r14 = -8, r14 ;; |
56 | cmp.ne p6, p7 = r14, in1 |
56 | cmp.ne p6, p7 = r14, in1 |
57 | (p7) br.cond.dpnt 3f ;; |
57 | (p7) br.cond.dpnt 3f ;; |
58 | 0: |
58 | 0: |
59 | cmp.ne p6, p7 = 0, in2 |
59 | cmp.ne p6, p7 = 0, in2 |
60 | (p7) br.cond.dpnt 2f ;; |
60 | (p7) br.cond.dpnt 2f ;; |
61 | (p6) adds r14 = -1, in2 |
61 | (p6) adds r14 = -1, in2 |
62 | (p6) mov r16 = r0 |
62 | (p6) mov r16 = r0 |
63 | (p6) mov r17 = r0 ;; |
63 | (p6) mov r17 = r0 ;; |
64 | (p6) mov ar.lc = r14 |
64 | (p6) mov ar.lc = r14 |
65 | 1: |
65 | 1: |
66 | add r14 = r16, in1 |
66 | add r14 = r16, in1 |
67 | add r15 = r16, in0 |
67 | add r15 = r16, in0 |
68 | adds r17 = 1, r17 ;; |
68 | adds r17 = 1, r17 ;; |
69 | ld1 r14 = [r14] |
69 | ld1 r14 = [r14] |
70 | mov r16 = r17 ;; |
70 | mov r16 = r17 ;; |
71 | st1 [r15] = r14 |
71 | st1 [r15] = r14 |
72 | br.cloop.sptk.few 1b ;; |
72 | br.cloop.sptk.few 1b ;; |
73 | 2: |
73 | 2: |
74 | mov ar.lc = r2 |
74 | mov ar.lc = r2 |
75 | mov ar.pfs = loc0 |
75 | mov ar.pfs = loc0 |
76 | br.ret.sptk.many rp |
76 | br.ret.sptk.many rp |
77 | 3: |
77 | 3: |
78 | adds r14 = 7, in0 ;; |
78 | adds r14 = 7, in0 ;; |
79 | and r14 = -8, r14 ;; |
79 | and r14 = -8, r14 ;; |
80 | cmp.eq p6, p7 = r14, in0 |
80 | cmp.eq p6, p7 = r14, in0 |
81 | (p7) br.cond.dptk 0b |
81 | (p7) br.cond.dptk 0b |
82 | shr.u r18 = in2, 3 ;; |
82 | shr.u r18 = in2, 3 ;; |
83 | cmp.ne p6, p7 = 0, r18 |
83 | cmp.ne p6, p7 = 0, r18 |
84 | (p7) br.cond.dpnt 5f ;; |
84 | (p7) br.cond.dpnt 5f ;; |
85 | (p6) adds r14 = -1, r18 |
85 | (p6) adds r14 = -1, r18 |
86 | (p6) mov r16 = r0 |
86 | (p6) mov r16 = r0 |
87 | (p6) mov r17 = r0 ;; |
87 | (p6) mov r17 = r0 ;; |
88 | (p6) mov ar.lc = r14 |
88 | (p6) mov ar.lc = r14 |
89 | 4: |
89 | 4: |
90 | shladd r14 = r16, 3, r0 |
90 | shladd r14 = r16, 3, r0 |
91 | adds r16 = 1, r17 ;; |
91 | adds r16 = 1, r17 ;; |
92 | add r15 = in1, r14 |
92 | add r15 = in1, r14 |
93 | add r14 = in0, r14 |
93 | add r14 = in0, r14 |
94 | mov r17 = r16 ;; |
94 | mov r17 = r16 ;; |
95 | ld8 r15 = [r15] ;; |
95 | ld8 r15 = [r15] ;; |
96 | st8 [r14] = r15 |
96 | st8 [r14] = r15 |
97 | br.cloop.sptk.few 4b |
97 | br.cloop.sptk.few 4b |
98 | 5: |
98 | 5: |
99 | and r15 = 7, in2 |
99 | and r15 = 7, in2 |
100 | shladd r14 = r18, 3, r0 |
100 | shladd r14 = r18, 3, r0 |
101 | mov r16 = r0 |
101 | mov r16 = r0 |
102 | mov r18 = r0 ;; |
102 | mov r18 = r0 ;; |
103 | cmp.eq p6, p7 = 0, r15 |
103 | cmp.eq p6, p7 = 0, r15 |
104 | add in0 = r14, in0 |
104 | add in0 = r14, in0 |
105 | adds r15 = -1, r15 |
105 | adds r15 = -1, r15 |
106 | add r17 = r14, in1 |
106 | add r17 = r14, in1 |
107 | (p6) br.cond.dpnt 2b ;; |
107 | (p6) br.cond.dpnt 2b ;; |
108 | mov ar.lc = r15 |
108 | mov ar.lc = r15 |
109 | 6: |
109 | 6: |
110 | add r14 = r16, r17 |
110 | add r14 = r16, r17 |
111 | add r15 = r16, in0 |
111 | add r15 = r16, in0 |
112 | adds r16 = 1, r18 ;; |
112 | adds r16 = 1, r18 ;; |
113 | ld1 r14 = [r14] |
113 | ld1 r14 = [r14] |
114 | mov r18 = r16 ;; |
114 | mov r18 = r16 ;; |
115 | st1 [r15] = r14 |
115 | st1 [r15] = r14 |
116 | br.cloop.sptk.few 6b ;; |
116 | br.cloop.sptk.few 6b ;; |
117 | mov ar.lc = r2 |
117 | mov ar.lc = r2 |
118 | mov ar.pfs = loc0 |
118 | mov ar.pfs = loc0 |
119 | br.ret.sptk.many rp |
119 | br.ret.sptk.many rp |
120 | 120 | ||
121 | memcpy_from_uspace_failover_address: |
121 | memcpy_from_uspace_failover_address: |
122 | memcpy_to_uspace_failover_address: |
122 | memcpy_to_uspace_failover_address: |
123 | mov r8 = r0 /* return 0 on failure */ |
123 | mov r8 = r0 /* return 0 on failure */ |
124 | mov ar.pfs = loc0 |
124 | mov ar.pfs = loc0 |
125 | br.ret.sptk.many rp |
125 | br.ret.sptk.many rp |
126 | 126 | ||
127 | .global memsetb |
127 | .global memsetb |
128 | memsetb: |
128 | memsetb: |
129 | br _memsetb |
129 | br _memsetb |
130 | 130 | ||
- | 131 | .global memsetw |
|
- | 132 | memsetw: |
|
- | 133 | br _memsetw |
|
- | 134 | ||
131 | .global cpu_halt |
135 | .global cpu_halt |
132 | cpu_halt: |
136 | cpu_halt: |
133 | br cpu_halt |
137 | br cpu_halt |
134 | 138 | ||
135 | .global panic_printf |
139 | .global panic_printf |
136 | panic_printf: |
140 | panic_printf: |
137 | { |
141 | { |
138 | br.call.sptk.many b0=printf |
142 | br.call.sptk.many b0=printf |
139 | } |
143 | } |
140 | br halt |
144 | br halt |
141 | 145 | ||
142 | /** Switch to userspace - low level code. |
146 | /** Switch to userspace - low level code. |
143 | * |
147 | * |
144 | * @param in0 Userspace entry point address. |
148 | * @param in0 Userspace entry point address. |
145 | * @param in1 Userspace stack pointer address. |
149 | * @param in1 Userspace stack pointer address. |
146 | * @param in2 Userspace register stack pointer address. |
150 | * @param in2 Userspace register stack pointer address. |
147 | * @param in3 Userspace address of thread uspace_arg_t structure. |
151 | * @param in3 Userspace address of thread uspace_arg_t structure. |
148 | * @param in4 Value to be stored in IPSR. |
152 | * @param in4 Value to be stored in IPSR. |
149 | * @param in5 Value to be stored in RSC. |
153 | * @param in5 Value to be stored in RSC. |
150 | */ |
154 | */ |
151 | .global switch_to_userspace |
155 | .global switch_to_userspace |
152 | switch_to_userspace: |
156 | switch_to_userspace: |
153 | alloc loc0 = ar.pfs, 6, 3, 0, 0 |
157 | alloc loc0 = ar.pfs, 6, 3, 0, 0 |
154 | rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ |
158 | rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ |
155 | srlz.d ;; |
159 | srlz.d ;; |
156 | srlz.i ;; |
160 | srlz.i ;; |
157 | 161 | ||
158 | mov cr.ipsr = in4 |
162 | mov cr.ipsr = in4 |
159 | mov cr.iip = in0 |
163 | mov cr.iip = in0 |
160 | mov r12 = in1 |
164 | mov r12 = in1 |
161 | 165 | ||
162 | xor r1 = r1, r1 |
166 | xor r1 = r1, r1 |
163 | 167 | ||
164 | /* r2 is defined to hold pcb_ptr - set it to 0 */ |
168 | /* r2 is defined to hold pcb_ptr - set it to 0 */ |
165 | xor r2 = r2, r2 |
169 | xor r2 = r2, r2 |
166 | 170 | ||
167 | mov loc1 = cr.ifs |
171 | mov loc1 = cr.ifs |
168 | movl loc2 = PFM_MASK ;; |
172 | movl loc2 = PFM_MASK ;; |
169 | and loc1 = loc2, loc1 ;; |
173 | and loc1 = loc2, loc1 ;; |
170 | mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ |
174 | mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ |
171 | 175 | ||
172 | invala |
176 | invala |
173 | 177 | ||
174 | mov loc1 = ar.rsc ;; |
178 | mov loc1 = ar.rsc ;; |
175 | and loc1 = ~3, loc1 ;; |
179 | and loc1 = ~3, loc1 ;; |
176 | mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ |
180 | mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ |
177 | 181 | ||
178 | flushrs ;; |
182 | flushrs ;; |
179 | 183 | ||
180 | mov ar.bspstore = in2 ;; |
184 | mov ar.bspstore = in2 ;; |
181 | mov ar.rsc = in5 ;; |
185 | mov ar.rsc = in5 ;; |
182 | 186 | ||
183 | mov r8 = in3 |
187 | mov r8 = in3 |
184 | 188 | ||
185 | rfi ;; |
189 | rfi ;; |
186 | 190 | ||
187 | 191 | ||
188 |
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192 |
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189 | 193 | ||
190 | 194 | ||
191 | 195 |