WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_ASM_H_
#define KERN_ia64_ASM_H_
 
#include <config.h>
#include <arch/types.h>
#include <arch/register.h>
 
 
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void  outb(ioport_t port, uint8_t v)
{
    *((uint8_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xfff) | ((port >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void  outw(ioport_t port, uint16_t v)
{
    *((uint16_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xfff) | ((port >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void  outl(ioport_t port, uint32_t v)
{
    *((uint32_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xfff) | ((port >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline uint8_t inb(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint8_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xfff) | ((port >> 2) << 12))));
}
 
static inline uint16_t inw(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint16_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xffE) | ((port >> 2) << 12))));
}
 
static inline uint32_t inl(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint32_t *)(IA64_IOSPACE_ADDRESS +
        ((port & 0xfff) | ((port >> 2) << 12))));
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uint64_t v;
 
    //I'm not sure why but this code bad inlines in scheduler, 
    //so THE shifts about 16B and causes kernel panic
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    //return v;
   
    //this code have the same meaning but inlines well
    asm volatile ("mov %0 = r12" : "=r" (v)  );
    return v & (~(STACK_SIZE-1));
}
 
/** Return Processor State Register.
 *
 * @return PSR.
 */
static inline uint64_t psr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = psr\n" : "=r" (v));
   
    return v;
}
 
/** Read IVA (Interruption Vector Address).
 *
 * @return Return location of interruption vector table.
 */
static inline uint64_t iva_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
   
    return v;
}
 
/** Write IVA (Interruption Vector Address) register.
 *
 * @param v New location of interruption vector table.
 */
static inline void iva_write(uint64_t v)
{
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
}
 
 
/** Read IVR (External Interrupt Vector Register).
 *
 * @return Highest priority, pending, unmasked external interrupt vector.
 */
static inline uint64_t ivr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
   
    return v;
}
 
static inline uint64_t cr64_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
   
    return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 */
static inline void itc_write(uint64_t v)
{
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
}
 
/** Read ITC (Interval Timer Counter) register.
 *
 * @return Current counter value.
 */
static inline uint64_t itc_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
   
    return v;
}
 
/** Write ITM (Interval Timer Match) register.
 *
 * @param v New match value.
 */
static inline void itm_write(uint64_t v)
{
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
}
 
/** Read ITM (Interval Timer Match) register.
 *
 * @return Match value.
 */
static inline uint64_t itm_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
   
    return v;
}
 
/** Read ITV (Interval Timer Vector) register.
 *
 * @return Current vector and mask bit.
 */
static inline uint64_t itv_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
   
    return v;
}
 
/** Write ITV (Interval Timer Vector) register.
 *
 * @param v New vector and mask bit.
 */
static inline void itv_write(uint64_t v)
{
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
}
 
/** Write EOI (End Of Interrupt) register.
 *
 * @param v This value is ignored.
 */
static inline void eoi_write(uint64_t v)
{
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
 
/** Read TPR (Task Priority Register).
 *
 * @return Current value of TPR.
 */
static inline uint64_t tpr_read(void)
{
    uint64_t v;
 
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
   
    return v;
}
 
/** Write TPR (Task Priority Register).
 *
 * @param v New value of TPR.
 */
static inline void tpr_write(uint64_t v)
{
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_disable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "rsm %1\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_enable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "ssm %1\n"
        ";;\n"
        "srlz.d\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Restore interrupt priority level.
 *
 * Restore PSR.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    if (ipl & PSR_I_MASK)
        (void) interrupts_enable();
    else
        (void) interrupts_disable();
}
 
/** Return interrupt priority level.
 *
 * @return PSR.
 */
static inline ipl_t interrupts_read(void)
{
    return (ipl_t) psr_read();
}
 
/** Disable protection key checking. */
static inline void pk_disable(void)
{
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(uint32_t t);
 
extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
    uint64_t, uint64_t);
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/include/asm.h – Rev 3774 → 3779

Rev 3774		Rev 3779
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia64	29	/** @addtogroup ia64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia64_ASM_H_	35	#ifndef KERN_ia64_ASM_H_
36	#define KERN_ia64_ASM_H_	36	#define KERN_ia64_ASM_H_
37		37
38	#include <config.h>	38	#include <config.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <arch/register.h>	40	#include <arch/register.h>
41		41
42	typedef uint64_t ioport_t;	-
43		-
44	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL	42	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
45		43
46	static inline void outb(ioport_t port, uint8_t v)	44	static inline void outb(ioport_t port, uint8_t v)
47	{	45	{
48	((uint8_t )(IA64_IOSPACE_ADDRESS +	46	((uint8_t )(IA64_IOSPACE_ADDRESS +
49	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	47	((port & 0xfff) \| ((port >> 2) << 12)))) = v;
50		48
51	asm volatile ("mf\n" ::: "memory");	49	asm volatile ("mf\n" ::: "memory");
52	}	50	}
53		51
54	static inline void outw(ioport_t port, uint16_t v)	52	static inline void outw(ioport_t port, uint16_t v)
55	{	53	{
56	((uint16_t )(IA64_IOSPACE_ADDRESS +	54	((uint16_t )(IA64_IOSPACE_ADDRESS +
57	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	55	((port & 0xfff) \| ((port >> 2) << 12)))) = v;
58		56
59	asm volatile ("mf\n" ::: "memory");	57	asm volatile ("mf\n" ::: "memory");
60	}	58	}
61		59
62	static inline void outl(ioport_t port, uint32_t v)	60	static inline void outl(ioport_t port, uint32_t v)
63	{	61	{
64	((uint32_t )(IA64_IOSPACE_ADDRESS +	62	((uint32_t )(IA64_IOSPACE_ADDRESS +
65	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	63	((port & 0xfff) \| ((port >> 2) << 12)))) = v;
66		64
67	asm volatile ("mf\n" ::: "memory");	65	asm volatile ("mf\n" ::: "memory");
68	}	66	}
69		67
70	static inline uint8_t inb(ioport_t port)	68	static inline uint8_t inb(ioport_t port)
71	{	69	{
72	asm volatile ("mf\n" ::: "memory");	70	asm volatile ("mf\n" ::: "memory");
73		71
74	return ((uint8_t )(IA64_IOSPACE_ADDRESS +	72	return ((uint8_t )(IA64_IOSPACE_ADDRESS +
75	((port & 0xfff) \| ((port >> 2) << 12))));	73	((port & 0xfff) \| ((port >> 2) << 12))));
76	}	74	}
77		75
78	static inline uint16_t inw(ioport_t port)	76	static inline uint16_t inw(ioport_t port)
79	{	77	{
80	asm volatile ("mf\n" ::: "memory");	78	asm volatile ("mf\n" ::: "memory");
81		79
82	return ((uint16_t )(IA64_IOSPACE_ADDRESS +	80	return ((uint16_t )(IA64_IOSPACE_ADDRESS +
83	((port & 0xffE) \| ((port >> 2) << 12))));	81	((port & 0xffE) \| ((port >> 2) << 12))));
84	}	82	}
85		83
86	static inline uint32_t inl(ioport_t port)	84	static inline uint32_t inl(ioport_t port)
87	{	85	{
88	asm volatile ("mf\n" ::: "memory");	86	asm volatile ("mf\n" ::: "memory");
89		87
90	return ((uint32_t )(IA64_IOSPACE_ADDRESS +	88	return ((uint32_t )(IA64_IOSPACE_ADDRESS +
91	((port & 0xfff) \| ((port >> 2) << 12))));	89	((port & 0xfff) \| ((port >> 2) << 12))));
92	}	90	}
93		91
94	/** Return base address of current stack	92	/** Return base address of current stack
95	*	93	*
96	* Return the base address of the current stack.	94	* Return the base address of the current stack.
97	* The stack is assumed to be STACK_SIZE long.	95	* The stack is assumed to be STACK_SIZE long.
98	* The stack must start on page boundary.	96	* The stack must start on page boundary.
99	*/	97	*/
100	static inline uintptr_t get_stack_base(void)	98	static inline uintptr_t get_stack_base(void)
101	{	99	{
102	uint64_t v;	100	uint64_t v;
103		101
104	//I'm not sure why but this code bad inlines in scheduler,	102	//I'm not sure why but this code bad inlines in scheduler,
105	//so THE shifts about 16B and causes kernel panic	103	//so THE shifts about 16B and causes kernel panic
106	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));	104	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
107	//return v;	105	//return v;
108		106
109	//this code have the same meaning but inlines well	107	//this code have the same meaning but inlines well
110	asm volatile ("mov %0 = r12" : "=r" (v) );	108	asm volatile ("mov %0 = r12" : "=r" (v) );
111	return v & (~(STACK_SIZE-1));	109	return v & (~(STACK_SIZE-1));
112	}	110	}
113		111
114	/** Return Processor State Register.	112	/** Return Processor State Register.
115	*	113	*
116	* @return PSR.	114	* @return PSR.
117	*/	115	*/
118	static inline uint64_t psr_read(void)	116	static inline uint64_t psr_read(void)
119	{	117	{
120	uint64_t v;	118	uint64_t v;
121		119
122	asm volatile ("mov %0 = psr\n" : "=r" (v));	120	asm volatile ("mov %0 = psr\n" : "=r" (v));
123		121
124	return v;	122	return v;
125	}	123	}
126		124
127	/** Read IVA (Interruption Vector Address).	125	/** Read IVA (Interruption Vector Address).
128	*	126	*
129	* @return Return location of interruption vector table.	127	* @return Return location of interruption vector table.
130	*/	128	*/
131	static inline uint64_t iva_read(void)	129	static inline uint64_t iva_read(void)
132	{	130	{
133	uint64_t v;	131	uint64_t v;
134		132
135	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));	133	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
136		134
137	return v;	135	return v;
138	}	136	}
139		137
140	/** Write IVA (Interruption Vector Address) register.	138	/** Write IVA (Interruption Vector Address) register.
141	*	139	*
142	* @param v New location of interruption vector table.	140	* @param v New location of interruption vector table.
143	*/	141	*/
144	static inline void iva_write(uint64_t v)	142	static inline void iva_write(uint64_t v)
145	{	143	{
146	asm volatile ("mov cr.iva = %0\n" : : "r" (v));	144	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
147	}	145	}
148		146
149		147
150	/** Read IVR (External Interrupt Vector Register).	148	/** Read IVR (External Interrupt Vector Register).
151	*	149	*
152	* @return Highest priority, pending, unmasked external interrupt vector.	150	* @return Highest priority, pending, unmasked external interrupt vector.
153	*/	151	*/
154	static inline uint64_t ivr_read(void)	152	static inline uint64_t ivr_read(void)
155	{	153	{
156	uint64_t v;	154	uint64_t v;
157		155
158	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));	156	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
159		157
160	return v;	158	return v;
161	}	159	}
162		160
163	static inline uint64_t cr64_read(void)	161	static inline uint64_t cr64_read(void)
164	{	162	{
165	uint64_t v;	163	uint64_t v;
166		164
167	asm volatile ("mov %0 = cr64\n" : "=r" (v));	165	asm volatile ("mov %0 = cr64\n" : "=r" (v));
168		166
169	return v;	167	return v;
170	}	168	}
171		169
172		170
173	/** Write ITC (Interval Timer Counter) register.	171	/** Write ITC (Interval Timer Counter) register.
174	*	172	*
175	* @param v New counter value.	173	* @param v New counter value.
176	*/	174	*/
177	static inline void itc_write(uint64_t v)	175	static inline void itc_write(uint64_t v)
178	{	176	{
179	asm volatile ("mov ar.itc = %0\n" : : "r" (v));	177	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
180	}	178	}
181		179
182	/** Read ITC (Interval Timer Counter) register.	180	/** Read ITC (Interval Timer Counter) register.
183	*	181	*
184	* @return Current counter value.	182	* @return Current counter value.
185	*/	183	*/
186	static inline uint64_t itc_read(void)	184	static inline uint64_t itc_read(void)
187	{	185	{
188	uint64_t v;	186	uint64_t v;
189		187
190	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));	188	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
191		189
192	return v;	190	return v;
193	}	191	}
194		192
195	/** Write ITM (Interval Timer Match) register.	193	/** Write ITM (Interval Timer Match) register.
196	*	194	*
197	* @param v New match value.	195	* @param v New match value.
198	*/	196	*/
199	static inline void itm_write(uint64_t v)	197	static inline void itm_write(uint64_t v)
200	{	198	{
201	asm volatile ("mov cr.itm = %0\n" : : "r" (v));	199	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
202	}	200	}
203		201
204	/** Read ITM (Interval Timer Match) register.	202	/** Read ITM (Interval Timer Match) register.
205	*	203	*
206	* @return Match value.	204	* @return Match value.
207	*/	205	*/
208	static inline uint64_t itm_read(void)	206	static inline uint64_t itm_read(void)
209	{	207	{
210	uint64_t v;	208	uint64_t v;
211		209
212	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));	210	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
213		211
214	return v;	212	return v;
215	}	213	}
216		214
217	/** Read ITV (Interval Timer Vector) register.	215	/** Read ITV (Interval Timer Vector) register.
218	*	216	*
219	* @return Current vector and mask bit.	217	* @return Current vector and mask bit.
220	*/	218	*/
221	static inline uint64_t itv_read(void)	219	static inline uint64_t itv_read(void)
222	{	220	{
223	uint64_t v;	221	uint64_t v;
224		222
225	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));	223	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
226		224
227	return v;	225	return v;
228	}	226	}
229		227
230	/** Write ITV (Interval Timer Vector) register.	228	/** Write ITV (Interval Timer Vector) register.
231	*	229	*
232	* @param v New vector and mask bit.	230	* @param v New vector and mask bit.
233	*/	231	*/
234	static inline void itv_write(uint64_t v)	232	static inline void itv_write(uint64_t v)
235	{	233	{
236	asm volatile ("mov cr.itv = %0\n" : : "r" (v));	234	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
237	}	235	}
238		236
239	/** Write EOI (End Of Interrupt) register.	237	/** Write EOI (End Of Interrupt) register.
240	*	238	*
241	* @param v This value is ignored.	239	* @param v This value is ignored.
242	*/	240	*/
243	static inline void eoi_write(uint64_t v)	241	static inline void eoi_write(uint64_t v)
244	{	242	{
245	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));	243	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
246	}	244	}
247		245
248	/** Read TPR (Task Priority Register).	246	/** Read TPR (Task Priority Register).
249	*	247	*
250	* @return Current value of TPR.	248	* @return Current value of TPR.
251	*/	249	*/
252	static inline uint64_t tpr_read(void)	250	static inline uint64_t tpr_read(void)
253	{	251	{
254	uint64_t v;	252	uint64_t v;
255		253
256	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));	254	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));
257		255
258	return v;	256	return v;
259	}	257	}
260		258
261	/** Write TPR (Task Priority Register).	259	/** Write TPR (Task Priority Register).
262	*	260	*
263	* @param v New value of TPR.	261	* @param v New value of TPR.
264	*/	262	*/
265	static inline void tpr_write(uint64_t v)	263	static inline void tpr_write(uint64_t v)
266	{	264	{
267	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));	265	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
268	}	266	}
269		267
270	/** Disable interrupts.	268	/** Disable interrupts.
271	*	269	*
272	* Disable interrupts and return previous	270	* Disable interrupts and return previous
273	* value of PSR.	271	* value of PSR.
274	*	272	*
275	* @return Old interrupt priority level.	273	* @return Old interrupt priority level.
276	*/	274	*/
277	static ipl_t interrupts_disable(void)	275	static ipl_t interrupts_disable(void)
278	{	276	{
279	uint64_t v;	277	uint64_t v;
280		278
281	asm volatile (	279	asm volatile (
282	"mov %0 = psr\n"	280	"mov %0 = psr\n"
283	"rsm %1\n"	281	"rsm %1\n"
284	: "=r" (v)	282	: "=r" (v)
285	: "i" (PSR_I_MASK)	283	: "i" (PSR_I_MASK)
286	);	284	);
287		285
288	return (ipl_t) v;	286	return (ipl_t) v;
289	}	287	}
290		288
291	/** Enable interrupts.	289	/** Enable interrupts.
292	*	290	*
293	* Enable interrupts and return previous	291	* Enable interrupts and return previous
294	* value of PSR.	292	* value of PSR.
295	*	293	*
296	* @return Old interrupt priority level.	294	* @return Old interrupt priority level.
297	*/	295	*/
298	static ipl_t interrupts_enable(void)	296	static ipl_t interrupts_enable(void)
299	{	297	{
300	uint64_t v;	298	uint64_t v;
301		299
302	asm volatile (	300	asm volatile (
303	"mov %0 = psr\n"	301	"mov %0 = psr\n"
304	"ssm %1\n"	302	"ssm %1\n"
305	";;\n"	303	";;\n"
306	"srlz.d\n"	304	"srlz.d\n"
307	: "=r" (v)	305	: "=r" (v)
308	: "i" (PSR_I_MASK)	306	: "i" (PSR_I_MASK)
309	);	307	);
310		308
311	return (ipl_t) v;	309	return (ipl_t) v;
312	}	310	}
313		311
314	/** Restore interrupt priority level.	312	/** Restore interrupt priority level.
315	*	313	*
316	* Restore PSR.	314	* Restore PSR.
317	*	315	*
318	* @param ipl Saved interrupt priority level.	316	* @param ipl Saved interrupt priority level.
319	*/	317	*/
320	static inline void interrupts_restore(ipl_t ipl)	318	static inline void interrupts_restore(ipl_t ipl)
321	{	319	{
322	if (ipl & PSR_I_MASK)	320	if (ipl & PSR_I_MASK)
323	(void) interrupts_enable();	321	(void) interrupts_enable();
324	else	322	else
325	(void) interrupts_disable();	323	(void) interrupts_disable();
326	}	324	}
327		325
328	/** Return interrupt priority level.	326	/** Return interrupt priority level.
329	*	327	*
330	* @return PSR.	328	* @return PSR.
331	*/	329	*/
332	static inline ipl_t interrupts_read(void)	330	static inline ipl_t interrupts_read(void)
333	{	331	{
334	return (ipl_t) psr_read();	332	return (ipl_t) psr_read();
335	}	333	}
336		334
337	/** Disable protection key checking. */	335	/** Disable protection key checking. */
338	static inline void pk_disable(void)	336	static inline void pk_disable(void)
339	{	337	{
340	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));	338	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
341	}	339	}
342		340
343	extern void cpu_halt(void);	341	extern void cpu_halt(void);
344	extern void cpu_sleep(void);	342	extern void cpu_sleep(void);
345	extern void asm_delay_loop(uint32_t t);	343	extern void asm_delay_loop(uint32_t t);
346		344
347	extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,	345	extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
348	uint64_t, uint64_t);	346	uint64_t, uint64_t);
349		347
350	#endif	348	#endif
351		349
352	/** @}	350	/** @}
353	*/	351	*/
354		352