WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_ASM_H_
#define KERN_ia64_ASM_H_
 
#include <config.h>
#include <arch/types.h>
#include <arch/register.h>
 
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void  outb(uint64_t port,uint8_t v)
{
    *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
 
static inline uint8_t inb(uint64_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
}
 
 
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uint64_t v;
 
    asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
   
    return v;
}
 
/** Return Processor State Register.
 *
 * @return PSR.
 */
static inline uint64_t psr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = psr\n" : "=r" (v));
   
    return v;
}
 
/** Read IVA (Interruption Vector Address).
 *
 * @return Return location of interruption vector table.
 */
static inline uint64_t iva_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
   
    return v;
}
 
/** Write IVA (Interruption Vector Address) register.
 *
 * @param v New location of interruption vector table.
 */
static inline void iva_write(uint64_t v)
{
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
}
 
 
/** Read IVR (External Interrupt Vector Register).
 *
 * @return Highest priority, pending, unmasked external interrupt vector.
 */
static inline uint64_t ivr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
   
    return v;
}
 
/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 */
static inline void itc_write(uint64_t v)
{
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
}
 
/** Read ITC (Interval Timer Counter) register.
 *
 * @return Current counter value.
 */
static inline uint64_t itc_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
   
    return v;
}
 
/** Write ITM (Interval Timer Match) register.
 *
 * @param v New match value.
 */
static inline void itm_write(uint64_t v)
{
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
}
 
/** Read ITM (Interval Timer Match) register.
 *
 * @return Match value.
 */
static inline uint64_t itm_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
   
    return v;
}
 
/** Read ITV (Interval Timer Vector) register.
 *
 * @return Current vector and mask bit.
 */
static inline uint64_t itv_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
   
    return v;
}
 
/** Write ITV (Interval Timer Vector) register.
 *
 * @param v New vector and mask bit.
 */
static inline void itv_write(uint64_t v)
{
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
}
 
/** Write EOI (End Of Interrupt) register.
 *
 * @param v This value is ignored.
 */
static inline void eoi_write(uint64_t v)
{
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
 
/** Read TPR (Task Priority Register).
 *
 * @return Current value of TPR.
 */
static inline uint64_t tpr_read(void)
{
    uint64_t v;
 
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
   
    return v;
}
 
/** Write TPR (Task Priority Register).
 *
 * @param v New value of TPR.
 */
static inline void tpr_write(uint64_t v)
{
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_disable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "rsm %1\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_enable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "ssm %1\n"
        ";;\n"
        "srlz.d\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Restore interrupt priority level.
 *
 * Restore PSR.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    if (ipl & PSR_I_MASK)
        (void) interrupts_enable();
    else
        (void) interrupts_disable();
}
 
/** Return interrupt priority level.
 *
 * @return PSR.
 */
static inline ipl_t interrupts_read(void)
{
    return (ipl_t) psr_read();
}
 
/** Disable protection key checking. */
static inline void pk_disable(void)
{
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(uint32_t t);
 
extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/include/asm.h – Rev 2515 → 2726

Rev 2515		Rev 2726
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia64	29	/** @addtogroup ia64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia64_ASM_H_	35	#ifndef KERN_ia64_ASM_H_
36	#define KERN_ia64_ASM_H_	36	#define KERN_ia64_ASM_H_
37		37
38	#include <config.h>	38	#include <config.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <arch/register.h>	40	#include <arch/register.h>
41		41
42		42
43	#define IA64_IOSPACE_ADDRESS 0xE0000FFFFC000000ULL	43	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
44		44
45	static inline void outb(uint64_t port,uint8_t v)	45	static inline void outb(uint64_t port,uint8_t v)
46	{	46	{
47	((char )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	47	((char )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;
-		48
48	asm volatile ("mf\n" ::: "memory");	49	asm volatile ("mf\n" ::: "memory");
49	}	50	}
50		51
51		52
52	static inline uint8_t inb(uint64_t port)	53	static inline uint8_t inb(uint64_t port)
53	{	54	{
54	asm volatile ("mf\n" ::: "memory");	55	asm volatile ("mf\n" ::: "memory");
-		56
55	return ((char )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));	57	return ((char )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));
56	}	58	}
57		59
58		60
59		61
60	/** Return base address of current stack	62	/** Return base address of current stack
61	*	63	*
62	* Return the base address of the current stack.	64	* Return the base address of the current stack.
63	* The stack is assumed to be STACK_SIZE long.	65	* The stack is assumed to be STACK_SIZE long.
64	* The stack must start on page boundary.	66	* The stack must start on page boundary.
65	*/	67	*/
66	static inline uintptr_t get_stack_base(void)	68	static inline uintptr_t get_stack_base(void)
67	{	69	{
68	uint64_t v;	70	uint64_t v;
69		71
70	asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));	72	asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
71		73
72	return v;	74	return v;
73	}	75	}
74		76
75	/** Return Processor State Register.	77	/** Return Processor State Register.
76	*	78	*
77	* @return PSR.	79	* @return PSR.
78	*/	80	*/
79	static inline uint64_t psr_read(void)	81	static inline uint64_t psr_read(void)
80	{	82	{
81	uint64_t v;	83	uint64_t v;
82		84
83	asm volatile ("mov %0 = psr\n" : "=r" (v));	85	asm volatile ("mov %0 = psr\n" : "=r" (v));
84		86
85	return v;	87	return v;
86	}	88	}
87		89
88	/** Read IVA (Interruption Vector Address).	90	/** Read IVA (Interruption Vector Address).
89	*	91	*
90	* @return Return location of interruption vector table.	92	* @return Return location of interruption vector table.
91	*/	93	*/
92	static inline uint64_t iva_read(void)	94	static inline uint64_t iva_read(void)
93	{	95	{
94	uint64_t v;	96	uint64_t v;
95		97
96	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));	98	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
97		99
98	return v;	100	return v;
99	}	101	}
100		102
101	/** Write IVA (Interruption Vector Address) register.	103	/** Write IVA (Interruption Vector Address) register.
102	*	104	*
103	* @param v New location of interruption vector table.	105	* @param v New location of interruption vector table.
104	*/	106	*/
105	static inline void iva_write(uint64_t v)	107	static inline void iva_write(uint64_t v)
106	{	108	{
107	asm volatile ("mov cr.iva = %0\n" : : "r" (v));	109	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
108	}	110	}
109		111
110		112
111	/** Read IVR (External Interrupt Vector Register).	113	/** Read IVR (External Interrupt Vector Register).
112	*	114	*
113	* @return Highest priority, pending, unmasked external interrupt vector.	115	* @return Highest priority, pending, unmasked external interrupt vector.
114	*/	116	*/
115	static inline uint64_t ivr_read(void)	117	static inline uint64_t ivr_read(void)
116	{	118	{
117	uint64_t v;	119	uint64_t v;
118		120
119	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));	121	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
120		122
121	return v;	123	return v;
122	}	124	}
123		125
124	/** Write ITC (Interval Timer Counter) register.	126	/** Write ITC (Interval Timer Counter) register.
125	*	127	*
126	* @param v New counter value.	128	* @param v New counter value.
127	*/	129	*/
128	static inline void itc_write(uint64_t v)	130	static inline void itc_write(uint64_t v)
129	{	131	{
130	asm volatile ("mov ar.itc = %0\n" : : "r" (v));	132	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
131	}	133	}
132		134
133	/** Read ITC (Interval Timer Counter) register.	135	/** Read ITC (Interval Timer Counter) register.
134	*	136	*
135	* @return Current counter value.	137	* @return Current counter value.
136	*/	138	*/
137	static inline uint64_t itc_read(void)	139	static inline uint64_t itc_read(void)
138	{	140	{
139	uint64_t v;	141	uint64_t v;
140		142
141	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));	143	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
142		144
143	return v;	145	return v;
144	}	146	}
145		147
146	/** Write ITM (Interval Timer Match) register.	148	/** Write ITM (Interval Timer Match) register.
147	*	149	*
148	* @param v New match value.	150	* @param v New match value.
149	*/	151	*/
150	static inline void itm_write(uint64_t v)	152	static inline void itm_write(uint64_t v)
151	{	153	{
152	asm volatile ("mov cr.itm = %0\n" : : "r" (v));	154	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
153	}	155	}
154		156
155	/** Read ITM (Interval Timer Match) register.	157	/** Read ITM (Interval Timer Match) register.
156	*	158	*
157	* @return Match value.	159	* @return Match value.
158	*/	160	*/
159	static inline uint64_t itm_read(void)	161	static inline uint64_t itm_read(void)
160	{	162	{
161	uint64_t v;	163	uint64_t v;
162		164
163	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));	165	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
164		166
165	return v;	167	return v;
166	}	168	}
167		169
168	/** Read ITV (Interval Timer Vector) register.	170	/** Read ITV (Interval Timer Vector) register.
169	*	171	*
170	* @return Current vector and mask bit.	172	* @return Current vector and mask bit.
171	*/	173	*/
172	static inline uint64_t itv_read(void)	174	static inline uint64_t itv_read(void)
173	{	175	{
174	uint64_t v;	176	uint64_t v;
175		177
176	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));	178	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
177		179
178	return v;	180	return v;
179	}	181	}
180		182
181	/** Write ITV (Interval Timer Vector) register.	183	/** Write ITV (Interval Timer Vector) register.
182	*	184	*
183	* @param v New vector and mask bit.	185	* @param v New vector and mask bit.
184	*/	186	*/
185	static inline void itv_write(uint64_t v)	187	static inline void itv_write(uint64_t v)
186	{	188	{
187	asm volatile ("mov cr.itv = %0\n" : : "r" (v));	189	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
188	}	190	}
189		191
190	/** Write EOI (End Of Interrupt) register.	192	/** Write EOI (End Of Interrupt) register.
191	*	193	*
192	* @param v This value is ignored.	194	* @param v This value is ignored.
193	*/	195	*/
194	static inline void eoi_write(uint64_t v)	196	static inline void eoi_write(uint64_t v)
195	{	197	{
196	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));	198	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
197	}	199	}
198		200
199	/** Read TPR (Task Priority Register).	201	/** Read TPR (Task Priority Register).
200	*	202	*
201	* @return Current value of TPR.	203	* @return Current value of TPR.
202	*/	204	*/
203	static inline uint64_t tpr_read(void)	205	static inline uint64_t tpr_read(void)
204	{	206	{
205	uint64_t v;	207	uint64_t v;
206		208
207	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));	209	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));
208		210
209	return v;	211	return v;
210	}	212	}
211		213
212	/** Write TPR (Task Priority Register).	214	/** Write TPR (Task Priority Register).
213	*	215	*
214	* @param v New value of TPR.	216	* @param v New value of TPR.
215	*/	217	*/
216	static inline void tpr_write(uint64_t v)	218	static inline void tpr_write(uint64_t v)
217	{	219	{
218	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));	220	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
219	}	221	}
220		222
221	/** Disable interrupts.	223	/** Disable interrupts.
222	*	224	*
223	* Disable interrupts and return previous	225	* Disable interrupts and return previous
224	* value of PSR.	226	* value of PSR.
225	*	227	*
226	* @return Old interrupt priority level.	228	* @return Old interrupt priority level.
227	*/	229	*/
228	static ipl_t interrupts_disable(void)	230	static ipl_t interrupts_disable(void)
229	{	231	{
230	uint64_t v;	232	uint64_t v;
231		233
232	asm volatile (	234	asm volatile (
233	"mov %0 = psr\n"	235	"mov %0 = psr\n"
234	"rsm %1\n"	236	"rsm %1\n"
235	: "=r" (v)	237	: "=r" (v)
236	: "i" (PSR_I_MASK)	238	: "i" (PSR_I_MASK)
237	);	239	);
238		240
239	return (ipl_t) v;	241	return (ipl_t) v;
240	}	242	}
241		243
242	/** Enable interrupts.	244	/** Enable interrupts.
243	*	245	*
244	* Enable interrupts and return previous	246	* Enable interrupts and return previous
245	* value of PSR.	247	* value of PSR.
246	*	248	*
247	* @return Old interrupt priority level.	249	* @return Old interrupt priority level.
248	*/	250	*/
249	static ipl_t interrupts_enable(void)	251	static ipl_t interrupts_enable(void)
250	{	252	{
251	uint64_t v;	253	uint64_t v;
252		254
253	asm volatile (	255	asm volatile (
254	"mov %0 = psr\n"	256	"mov %0 = psr\n"
255	"ssm %1\n"	257	"ssm %1\n"
256	";;\n"	258	";;\n"
257	"srlz.d\n"	259	"srlz.d\n"
258	: "=r" (v)	260	: "=r" (v)
259	: "i" (PSR_I_MASK)	261	: "i" (PSR_I_MASK)
260	);	262	);
261		263
262	return (ipl_t) v;	264	return (ipl_t) v;
263	}	265	}
264		266
265	/** Restore interrupt priority level.	267	/** Restore interrupt priority level.
266	*	268	*
267	* Restore PSR.	269	* Restore PSR.
268	*	270	*
269	* @param ipl Saved interrupt priority level.	271	* @param ipl Saved interrupt priority level.
270	*/	272	*/
271	static inline void interrupts_restore(ipl_t ipl)	273	static inline void interrupts_restore(ipl_t ipl)
272	{	274	{
273	if (ipl & PSR_I_MASK)	275	if (ipl & PSR_I_MASK)
274	(void) interrupts_enable();	276	(void) interrupts_enable();
275	else	277	else
276	(void) interrupts_disable();	278	(void) interrupts_disable();
277	}	279	}
278		280
279	/** Return interrupt priority level.	281	/** Return interrupt priority level.
280	*	282	*
281	* @return PSR.	283	* @return PSR.
282	*/	284	*/
283	static inline ipl_t interrupts_read(void)	285	static inline ipl_t interrupts_read(void)
284	{	286	{
285	return (ipl_t) psr_read();	287	return (ipl_t) psr_read();
286	}	288	}
287		289
288	/** Disable protection key checking. */	290	/** Disable protection key checking. */
289	static inline void pk_disable(void)	291	static inline void pk_disable(void)
290	{	292	{
291	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));	293	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
292	}	294	}
293		295
294	extern void cpu_halt(void);	296	extern void cpu_halt(void);
295	extern void cpu_sleep(void);	297	extern void cpu_sleep(void);
296	extern void asm_delay_loop(uint32_t t);	298	extern void asm_delay_loop(uint32_t t);
297		299
298	extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);	300	extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
299		301
300	#endif	302	#endif
301		303
302	/** @}	304	/** @}
303	*/	305	*/
304		306