WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32xen/src/smp/apic.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32xen
 * @{
 */
/** @file
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  QEMU 0.8.0 with 2-15 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 
uint32_t apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
 
static void apic_spurious(int n, istate_t *istate);
static void l_apic_timer_interrupt(int n, istate_t *istate);
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    unsigned int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
        }
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1<<i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param istate Interrupted state.
 */
void apic_spurious(int n, istate_t *istate)
{
#ifdef CONFIG_DEBUG
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
#endif
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(uint8_t vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(uint8_t apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors())
        return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i < 2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    tpr_t tpr;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    uint32_t t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
 
    /* Task Priority Register initialization. */
    tpr.value = l_apic[TPR];
    tpr.pri_sc = 0;
    tpr.pri = 0;
    l_apic[TPR] = tpr.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    svr.focus_checking = true;
    l_apic[SVR] = svr.value;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /*
     * Measure and configure the timer to generate timer
     * interrupt with period 1s/HZ seconds.
     */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000000/HZ);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
    /* Program Logical Destination Register. */
    ldr.value = l_apic[LDR];
    if (CPU->id < sizeof(CPU->id) * 8)  /* size in bits */
        ldr.id = (1 << CPU->id);
    l_apic[LDR] = ldr.value;
   
    /* Program Destination Format Register for Flat mode. */
    dfr.value = l_apic[DFR];
    dfr.model = MODEL_FLAT;
    l_apic[DFR] = dfr.value;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Local APIC Timer Interrupt.
 *
 * @param n Interrupt vector number.
 * @param istate Interrupted state.
 */
void l_apic_timer_interrupt(int n, istate_t *istate)
{
    l_apic_eoi();
    clock();
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
uint8_t l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
uint32_t io_apic_read(uint8_t address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param x Content to be written to the addressed IO APIC register.
 */
void io_apic_write(uint8_t address, uint32_t x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
    reg.lo = io_apic_read(IOREDTBL + pin * 2);
    reg.hi = io_apic_read(IOREDTBL + pin * 2 + 1);
   
    reg.dest = dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin * 2, reg.lo);
    io_apic_write(IOREDTBL + pin * 2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(uint16_t irqmask)
{
    io_redirection_reg_t reg;
    unsigned int i;
    int pin;
   
    for (i = 0; i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(uint16_t irqmask)
{
    unsigned int i;
    int pin;
    io_redirection_reg_t reg;  
   
    for (i = 0; i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 
/** @}
 */
 

Rev 2107	Rev 2457
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32xen	29	/** @addtogroup ia32xen
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/types.h>	35	#include <arch/types.h>
36	#include <arch/smp/apic.h>	36	#include <arch/smp/apic.h>
37	#include <arch/smp/ap.h>	37	#include <arch/smp/ap.h>
38	#include <arch/smp/mps.h>	38	#include <arch/smp/mps.h>
39	#include <mm/page.h>	39	#include <mm/page.h>
40	#include <time/delay.h>	40	#include <time/delay.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <print.h>	43	#include <print.h>
44	#include <arch/asm.h>	44	#include <arch/asm.h>
45	#include <arch.h>	45	#include <arch.h>
46		46
47	#ifdef CONFIG_SMP	47	#ifdef CONFIG_SMP
48		48
49	/*	49	/*
50	* Advanced Programmable Interrupt Controller for SMP systems.	50	* Advanced Programmable Interrupt Controller for SMP systems.
51	* Tested on:	51	* Tested on:
52	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs	52	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
53	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	53	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
54	* VMware Workstation 5.5 with 2 CPUs	54	* VMware Workstation 5.5 with 2 CPUs
55	* QEMU 0.8.0 with 2-15 CPUs	55	* QEMU 0.8.0 with 2-15 CPUs
56	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	56	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
57	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	57	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
58	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	58	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
59	*/	59	*/
60		60
61	/*	61	/*
62	* These variables either stay configured as initilalized, or are changed by	62	* These variables either stay configured as initilalized, or are changed by
63	* the MP configuration code.	63	* the MP configuration code.
64	*	64	*
65	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	65	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
66	* optimize the code too much and accesses to l_apic and io_apic, that must	66	* optimize the code too much and accesses to l_apic and io_apic, that must
67	* always be 32-bit, would use byte oriented instructions.	67	* always be 32-bit, would use byte oriented instructions.
68	*/	68	*/
69	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;	69	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;
70	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;	70	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;
71		71
72	uint32_t apic_id_mask = 0;	72	uint32_t apic_id_mask = 0;
73		73
74	static int apic_poll_errors(void);	74	static int apic_poll_errors(void);
75		75
76	#ifdef LAPIC_VERBOSE	76	#ifdef LAPIC_VERBOSE
77	static char *delmod_str[] = {	77	static char *delmod_str[] = {
78	"Fixed",	78	"Fixed",
79	"Lowest Priority",	79	"Lowest Priority",
80	"SMI",	80	"SMI",
81	"Reserved",	81	"Reserved",
82	"NMI",	82	"NMI",
83	"INIT",	83	"INIT",
84	"STARTUP",	84	"STARTUP",
85	"ExtInt"	85	"ExtInt"
86	};	86	};
87		87
88	static char *destmod_str[] = {	88	static char *destmod_str[] = {
89	"Physical",	89	"Physical",
90	"Logical"	90	"Logical"
91	};	91	};
92		92
93	static char *trigmod_str[] = {	93	static char *trigmod_str[] = {
94	"Edge",	94	"Edge",
95	"Level"	95	"Level"
96	};	96	};
97		97
98	static char *mask_str[] = {	98	static char *mask_str[] = {
99	"Unmasked",	99	"Unmasked",
100	"Masked"	100	"Masked"
101	};	101	};
102		102
103	static char *delivs_str[] = {	103	static char *delivs_str[] = {
104	"Idle",	104	"Idle",
105	"Send Pending"	105	"Send Pending"
106	};	106	};
107		107
108	static char *tm_mode_str[] = {	108	static char *tm_mode_str[] = {
109	"One-shot",	109	"One-shot",
110	"Periodic"	110	"Periodic"
111	};	111	};
112		112
113	static char *intpol_str[] = {	113	static char *intpol_str[] = {
114	"Polarity High",	114	"Polarity High",
115	"Polarity Low"	115	"Polarity Low"
116	};	116	};
117	#endif /* LAPIC_VERBOSE */	117	#endif /* LAPIC_VERBOSE */
118		118
119		119
120	static void apic_spurious(int n, istate_t *istate);	120	static void apic_spurious(int n, istate_t *istate);
121	static void l_apic_timer_interrupt(int n, istate_t *istate);	121	static void l_apic_timer_interrupt(int n, istate_t *istate);
122		122
123	/** Initialize APIC on BSP. */	123	/** Initialize APIC on BSP. */
124	void apic_init(void)	124	void apic_init(void)
125	{	125	{
126	io_apic_id_t idreg;	126	io_apic_id_t idreg;
127	unsigned int i;	127	unsigned int i;
128		128
129	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);	129	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
130		130
131	enable_irqs_function = io_apic_enable_irqs;	131	enable_irqs_function = io_apic_enable_irqs;
132	disable_irqs_function = io_apic_disable_irqs;	132	disable_irqs_function = io_apic_disable_irqs;
133	eoi_function = l_apic_eoi;	133	eoi_function = l_apic_eoi;
134		134
135	/*	135	/*
136	* Configure interrupt routing.	136	* Configure interrupt routing.
137	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	137	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
138	* Other interrupts will be forwarded to the lowest priority CPU.	138	* Other interrupts will be forwarded to the lowest priority CPU.
139	*/	139	*/
140	io_apic_disable_irqs(0xffff);	140	io_apic_disable_irqs(0xffff);
141	exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);	141	exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
142	for (i = 0; i < IRQ_COUNT; i++) {	142	for (i = 0; i < IRQ_COUNT; i++) {
143	int pin;	143	int pin;
144		144
145	if ((pin = smp_irq_to_pin(i)) != -1) {	145	if ((pin = smp_irq_to_pin(i)) != -1) {
146	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);	146	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
147	}	147	}
148	}	148	}
149		149
150	/*	150	/*
151	* Ensure that io_apic has unique ID.	151	* Ensure that io_apic has unique ID.
152	*/	152	*/
153	idreg.value = io_apic_read(IOAPICID);	153	idreg.value = io_apic_read(IOAPICID);
154	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	154	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
155	for (i = 0; i < APIC_ID_COUNT; i++) {	155	for (i = 0; i < APIC_ID_COUNT; i++) {
156	if (!((1<<i) & apic_id_mask)) {	156	if (!((1<<i) & apic_id_mask)) {
157	idreg.apic_id = i;	157	idreg.apic_id = i;
158	io_apic_write(IOAPICID, idreg.value);	158	io_apic_write(IOAPICID, idreg.value);
159	break;	159	break;
160	}	160	}
161	}	161	}
162	}	162	}
163		163
164	/*	164	/*
165	* Configure the BSP's lapic.	165	* Configure the BSP's lapic.
166	*/	166	*/
167	l_apic_init();	167	l_apic_init();
168		168
169	l_apic_debug();	169	l_apic_debug();
170	}	170	}
171		171
172	/** APIC spurious interrupt handler.	172	/** APIC spurious interrupt handler.
173	*	173	*
174	* @param n Interrupt vector.	174	* @param n Interrupt vector.
175	* @param istate Interrupted state.	175	* @param istate Interrupted state.
176	*/	176	*/
177	void apic_spurious(int n, istate_t *istate)	177	void apic_spurious(int n, istate_t *istate)
178	{	178	{
179	#ifdef CONFIG_DEBUG	179	#ifdef CONFIG_DEBUG
180	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	180	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
181	#endif	181	#endif
182	}	182	}
183		183
184	/** Poll for APIC errors.	184	/** Poll for APIC errors.
185	*	185	*
186	* Examine Error Status Register and report all errors found.	186	* Examine Error Status Register and report all errors found.
187	*	187	*
188	* @return 0 on error, 1 on success.	188	* @return 0 on error, 1 on success.
189	*/	189	*/
190	int apic_poll_errors(void)	190	int apic_poll_errors(void)
191	{	191	{
192	esr_t esr;	192	esr_t esr;
193		193
194	esr.value = l_apic[ESR];	194	esr.value = l_apic[ESR];
195		195
196	if (esr.send_checksum_error)	196	if (esr.send_checksum_error)
197	printf("Send Checksum Error\n");	197	printf("Send Checksum Error\n");
198	if (esr.receive_checksum_error)	198	if (esr.receive_checksum_error)
199	printf("Receive Checksum Error\n");	199	printf("Receive Checksum Error\n");
200	if (esr.send_accept_error)	200	if (esr.send_accept_error)
201	printf("Send Accept Error\n");	201	printf("Send Accept Error\n");
202	if (esr.receive_accept_error)	202	if (esr.receive_accept_error)
203	printf("Receive Accept Error\n");	203	printf("Receive Accept Error\n");
204	if (esr.send_illegal_vector)	204	if (esr.send_illegal_vector)
205	printf("Send Illegal Vector\n");	205	printf("Send Illegal Vector\n");
206	if (esr.received_illegal_vector)	206	if (esr.received_illegal_vector)
207	printf("Received Illegal Vector\n");	207	printf("Received Illegal Vector\n");
208	if (esr.illegal_register_address)	208	if (esr.illegal_register_address)
209	printf("Illegal Register Address\n");	209	printf("Illegal Register Address\n");
210		210
211	return !esr.err_bitmap;	211	return !esr.err_bitmap;
212	}	212	}
213		213
214	/** Send all CPUs excluding CPU IPI vector.	214	/** Send all CPUs excluding CPU IPI vector.
215	*	215	*
216	* @param vector Interrupt vector to be sent.	216	* @param vector Interrupt vector to be sent.
217	*	217	*
218	* @return 0 on failure, 1 on success.	218	* @return 0 on failure, 1 on success.
219	*/	219	*/
220	int l_apic_broadcast_custom_ipi(uint8_t vector)	220	int l_apic_broadcast_custom_ipi(uint8_t vector)
221	{	221	{
222	icr_t icr;	222	icr_t icr;
223		223
224	icr.lo = l_apic[ICRlo];	224	icr.lo = l_apic[ICRlo];
225	icr.delmod = DELMOD_FIXED;	225	icr.delmod = DELMOD_FIXED;
226	icr.destmod = DESTMOD_LOGIC;	226	icr.destmod = DESTMOD_LOGIC;
227	icr.level = LEVEL_ASSERT;	227	icr.level = LEVEL_ASSERT;
228	icr.shorthand = SHORTHAND_ALL_EXCL;	228	icr.shorthand = SHORTHAND_ALL_EXCL;
229	icr.trigger_mode = TRIGMOD_LEVEL;	229	icr.trigger_mode = TRIGMOD_LEVEL;
230	icr.vector = vector;	230	icr.vector = vector;
231		231
232	l_apic[ICRlo] = icr.lo;	232	l_apic[ICRlo] = icr.lo;
233		233
234	icr.lo = l_apic[ICRlo];	234	icr.lo = l_apic[ICRlo];
235	if (icr.delivs == DELIVS_PENDING) {	235	if (icr.delivs == DELIVS_PENDING) {
236	#ifdef CONFIG_DEBUG	236	#ifdef CONFIG_DEBUG
237	printf("IPI is pending.\n");	237	printf("IPI is pending.\n");
238	#endif	238	#endif
239	}	239	}
240		240
241	return apic_poll_errors();	241	return apic_poll_errors();
242	}	242	}
243		243
244	/** Universal Start-up Algorithm for bringing up the AP processors.	244	/** Universal Start-up Algorithm for bringing up the AP processors.
245	*	245	*
246	* @param apicid APIC ID of the processor to be brought up.	246	* @param apicid APIC ID of the processor to be brought up.
247	*	247	*
248	* @return 0 on failure, 1 on success.	248	* @return 0 on failure, 1 on success.
249	*/	249	*/
250	int l_apic_send_init_ipi(uint8_t apicid)	250	int l_apic_send_init_ipi(uint8_t apicid)
251	{	251	{
252	icr_t icr;	252	icr_t icr;
253	int i;	253	int i;
254		254
255	/*	255	/*
256	* Read the ICR register in and zero all non-reserved fields.	256	* Read the ICR register in and zero all non-reserved fields.
257	*/	257	*/
258	icr.lo = l_apic[ICRlo];	258	icr.lo = l_apic[ICRlo];
259	icr.hi = l_apic[ICRhi];	259	icr.hi = l_apic[ICRhi];
260		260
261	icr.delmod = DELMOD_INIT;	261	icr.delmod = DELMOD_INIT;
262	icr.destmod = DESTMOD_PHYS;	262	icr.destmod = DESTMOD_PHYS;
263	icr.level = LEVEL_ASSERT;	263	icr.level = LEVEL_ASSERT;
264	icr.trigger_mode = TRIGMOD_LEVEL;	264	icr.trigger_mode = TRIGMOD_LEVEL;
265	icr.shorthand = SHORTHAND_NONE;	265	icr.shorthand = SHORTHAND_NONE;
266	icr.vector = 0;	266	icr.vector = 0;
267	icr.dest = apicid;	267	icr.dest = apicid;
268		268
269	l_apic[ICRhi] = icr.hi;	269	l_apic[ICRhi] = icr.hi;
270	l_apic[ICRlo] = icr.lo;	270	l_apic[ICRlo] = icr.lo;
271		271
272	/*	272	/*
273	* According to MP Specification, 20us should be enough to	273	* According to MP Specification, 20us should be enough to
274	* deliver the IPI.	274	* deliver the IPI.
275	*/	275	*/
276	delay(20);	276	delay(20);
277		277
278	if (!apic_poll_errors())	278	if (!apic_poll_errors())
279	return 0;	279	return 0;
280		280
281	icr.lo = l_apic[ICRlo];	281	icr.lo = l_apic[ICRlo];
282	if (icr.delivs == DELIVS_PENDING) {	282	if (icr.delivs == DELIVS_PENDING) {
283	#ifdef CONFIG_DEBUG	283	#ifdef CONFIG_DEBUG
284	printf("IPI is pending.\n");	284	printf("IPI is pending.\n");
285	#endif	285	#endif
286	}	286	}
287		287
288	icr.delmod = DELMOD_INIT;	288	icr.delmod = DELMOD_INIT;
289	icr.destmod = DESTMOD_PHYS;	289	icr.destmod = DESTMOD_PHYS;
290	icr.level = LEVEL_DEASSERT;	290	icr.level = LEVEL_DEASSERT;
291	icr.shorthand = SHORTHAND_NONE;	291	icr.shorthand = SHORTHAND_NONE;
292	icr.trigger_mode = TRIGMOD_LEVEL;	292	icr.trigger_mode = TRIGMOD_LEVEL;
293	icr.vector = 0;	293	icr.vector = 0;
294	l_apic[ICRlo] = icr.lo;	294	l_apic[ICRlo] = icr.lo;
295		295
296	/*	296	/*
297	* Wait 10ms as MP Specification specifies.	297	* Wait 10ms as MP Specification specifies.
298	*/	298	*/
299	delay(10000);	299	delay(10000);
300		300
301	if (!is_82489DX_apic(l_apic[LAVR])) {	301	if (!is_82489DX_apic(l_apic[LAVR])) {
302	/*	302	/*
303	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	303	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
304	*/	304	*/
305	for (i = 0; i < 2; i++) {	305	for (i = 0; i < 2; i++) {
306	icr.lo = l_apic[ICRlo];	306	icr.lo = l_apic[ICRlo];
307	icr.delmod = DELMOD_STARTUP;	307	icr.delmod = DELMOD_STARTUP;
308	icr.destmod = DESTMOD_PHYS;	308	icr.destmod = DESTMOD_PHYS;
309	icr.level = LEVEL_ASSERT;	309	icr.level = LEVEL_ASSERT;
310	icr.shorthand = SHORTHAND_NONE;	310	icr.shorthand = SHORTHAND_NONE;
311	icr.trigger_mode = TRIGMOD_LEVEL;	311	icr.trigger_mode = TRIGMOD_LEVEL;
312	l_apic[ICRlo] = icr.lo;	312	l_apic[ICRlo] = icr.lo;
313	delay(200);	313	delay(200);
314	}	314	}
315	}	315	}
316		316
317	return apic_poll_errors();	317	return apic_poll_errors();
318	}	318	}
319		319
320	/** Initialize Local APIC. */	320	/** Initialize Local APIC. */
321	void l_apic_init(void)	321	void l_apic_init(void)
322	{	322	{
323	lvt_error_t error;	323	lvt_error_t error;
324	lvt_lint_t lint;	324	lvt_lint_t lint;
325	tpr_t tpr;	325	tpr_t tpr;
326	svr_t svr;	326	svr_t svr;
327	icr_t icr;	327	icr_t icr;
328	tdcr_t tdcr;	328	tdcr_t tdcr;
329	lvt_tm_t tm;	329	lvt_tm_t tm;
330	ldr_t ldr;	330	ldr_t ldr;
331	dfr_t dfr;	331	dfr_t dfr;
332	uint32_t t1, t2;	332	uint32_t t1, t2;
333		333
334	/* Initialize LVT Error register. */	334	/* Initialize LVT Error register. */
335	error.value = l_apic[LVT_Err];	335	error.value = l_apic[LVT_Err];
336	error.masked = true;	336	error.masked = true;
337	l_apic[LVT_Err] = error.value;	337	l_apic[LVT_Err] = error.value;
338		338
339	/* Initialize LVT LINT0 register. */	339	/* Initialize LVT LINT0 register. */
340	lint.value = l_apic[LVT_LINT0];	340	lint.value = l_apic[LVT_LINT0];
341	lint.masked = true;	341	lint.masked = true;
342	l_apic[LVT_LINT0] = lint.value;	342	l_apic[LVT_LINT0] = lint.value;
343		343
344	/* Initialize LVT LINT1 register. */	344	/* Initialize LVT LINT1 register. */
345	lint.value = l_apic[LVT_LINT1];	345	lint.value = l_apic[LVT_LINT1];
346	lint.masked = true;	346	lint.masked = true;
347	l_apic[LVT_LINT1] = lint.value;	347	l_apic[LVT_LINT1] = lint.value;
348		348
349	/* Task Priority Register initialization. */	349	/* Task Priority Register initialization. */
350	tpr.value = l_apic[TPR];	350	tpr.value = l_apic[TPR];
351	tpr.pri_sc = 0;	351	tpr.pri_sc = 0;
352	tpr.pri = 0;	352	tpr.pri = 0;
353	l_apic[TPR] = tpr.value;	353	l_apic[TPR] = tpr.value;
354		354
355	/* Spurious-Interrupt Vector Register initialization. */	355	/* Spurious-Interrupt Vector Register initialization. */
356	svr.value = l_apic[SVR];	356	svr.value = l_apic[SVR];
357	svr.vector = VECTOR_APIC_SPUR;	357	svr.vector = VECTOR_APIC_SPUR;
358	svr.lapic_enabled = true;	358	svr.lapic_enabled = true;
359	svr.focus_checking = true;	359	svr.focus_checking = true;
360	l_apic[SVR] = svr.value;	360	l_apic[SVR] = svr.value;
361		361
362	if (CPU->arch.family >= 6)	362	if (CPU->arch.family >= 6)
363	enable_l_apic_in_msr();	363	enable_l_apic_in_msr();
364		364
365	/* Interrupt Command Register initialization. */	365	/* Interrupt Command Register initialization. */
366	icr.lo = l_apic[ICRlo];	366	icr.lo = l_apic[ICRlo];
367	icr.delmod = DELMOD_INIT;	367	icr.delmod = DELMOD_INIT;
368	icr.destmod = DESTMOD_PHYS;	368	icr.destmod = DESTMOD_PHYS;
369	icr.level = LEVEL_DEASSERT;	369	icr.level = LEVEL_DEASSERT;
370	icr.shorthand = SHORTHAND_ALL_INCL;	370	icr.shorthand = SHORTHAND_ALL_INCL;
371	icr.trigger_mode = TRIGMOD_LEVEL;	371	icr.trigger_mode = TRIGMOD_LEVEL;
372	l_apic[ICRlo] = icr.lo;	372	l_apic[ICRlo] = icr.lo;
373		373
374	/* Timer Divide Configuration Register initialization. */	374	/* Timer Divide Configuration Register initialization. */
375	tdcr.value = l_apic[TDCR];	375	tdcr.value = l_apic[TDCR];
376	tdcr.div_value = DIVIDE_1;	376	tdcr.div_value = DIVIDE_1;
377	l_apic[TDCR] = tdcr.value;	377	l_apic[TDCR] = tdcr.value;
378		378
379	/* Program local timer. */	379	/* Program local timer. */
380	tm.value = l_apic[LVT_Tm];	380	tm.value = l_apic[LVT_Tm];
381	tm.vector = VECTOR_CLK;	381	tm.vector = VECTOR_CLK;
382	tm.mode = TIMER_PERIODIC;	382	tm.mode = TIMER_PERIODIC;
383	tm.masked = false;	383	tm.masked = false;
384	l_apic[LVT_Tm] = tm.value;	384	l_apic[LVT_Tm] = tm.value;
385		385
386	/*	386	/*
387	* Measure and configure the timer to generate timer	387	* Measure and configure the timer to generate timer
388	* interrupt with period 1s/HZ seconds.	388	* interrupt with period 1s/HZ seconds.
389	*/	389	*/
390	t1 = l_apic[CCRT];	390	t1 = l_apic[CCRT];
391	l_apic[ICRT] = 0xffffffff;	391	l_apic[ICRT] = 0xffffffff;
392		392
393	while (l_apic[CCRT] == t1)	393	while (l_apic[CCRT] == t1)
394	;	394	;
395		395
396	t1 = l_apic[CCRT];	396	t1 = l_apic[CCRT];
397	delay(1000000/HZ);	397	delay(1000000/HZ);
398	t2 = l_apic[CCRT];	398	t2 = l_apic[CCRT];
399		399
400	l_apic[ICRT] = t1-t2;	400	l_apic[ICRT] = t1-t2;
401		401
402	/* Program Logical Destination Register. */	402	/* Program Logical Destination Register. */
403	ldr.value = l_apic[LDR];	403	ldr.value = l_apic[LDR];
404	if (CPU->id < sizeof(CPU->id) * 8) /* size in bits */	404	if (CPU->id < sizeof(CPU->id) * 8) /* size in bits */
405	ldr.id = (1 << CPU->id);	405	ldr.id = (1 << CPU->id);
406	l_apic[LDR] = ldr.value;	406	l_apic[LDR] = ldr.value;
407		407
408	/* Program Destination Format Register for Flat mode. */	408	/* Program Destination Format Register for Flat mode. */
409	dfr.value = l_apic[DFR];	409	dfr.value = l_apic[DFR];
410	dfr.model = MODEL_FLAT;	410	dfr.model = MODEL_FLAT;
411	l_apic[DFR] = dfr.value;	411	l_apic[DFR] = dfr.value;
412	}	412	}
413		413
414	/** Local APIC End of Interrupt. */	414	/** Local APIC End of Interrupt. */
415	void l_apic_eoi(void)	415	void l_apic_eoi(void)
416	{	416	{
417	l_apic[EOI] = 0;	417	l_apic[EOI] = 0;
418	}	418	}
419		419
420	/** Dump content of Local APIC registers. */	420	/** Dump content of Local APIC registers. */
421	void l_apic_debug(void)	421	void l_apic_debug(void)
422	{	422	{
423	#ifdef LAPIC_VERBOSE	423	#ifdef LAPIC_VERBOSE
424	lvt_tm_t tm;	424	lvt_tm_t tm;
425	lvt_lint_t lint;	425	lvt_lint_t lint;
426	lvt_error_t error;	426	lvt_error_t error;
427		427
428	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	428	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
429		429
430	tm.value = l_apic[LVT_Tm];	430	tm.value = l_apic[LVT_Tm];
431	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	431	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
432	lint.value = l_apic[LVT_LINT0];	432	lint.value = l_apic[LVT_LINT0];
433	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	433	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
434	lint.value = l_apic[LVT_LINT1];	434	lint.value = l_apic[LVT_LINT1];
435	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	435	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
436	error.value = l_apic[LVT_Err];	436	error.value = l_apic[LVT_Err];
437	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	437	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
438	#endif	438	#endif
439	}	439	}
440		440
441	/** Local APIC Timer Interrupt.	441	/** Local APIC Timer Interrupt.
442	*	442	*
443	* @param n Interrupt vector number.	443	* @param n Interrupt vector number.
444	* @param istate Interrupted state.	444	* @param istate Interrupted state.
445	*/	445	*/
446	void l_apic_timer_interrupt(int n, istate_t *istate)	446	void l_apic_timer_interrupt(int n, istate_t *istate)
447	{	447	{
448	l_apic_eoi();	448	l_apic_eoi();
449	clock();	449	clock();
450	}	450	}
451		451
452	/** Get Local APIC ID.	452	/** Get Local APIC ID.
453	*	453	*
454	* @return Local APIC ID.	454	* @return Local APIC ID.
455	*/	455	*/
456	uint8_t l_apic_id(void)	456	uint8_t l_apic_id(void)
457	{	457	{
458	l_apic_id_t idreg;	458	l_apic_id_t idreg;
459		459
460	idreg.value = l_apic[L_APIC_ID];	460	idreg.value = l_apic[L_APIC_ID];
461	return idreg.apic_id;	461	return idreg.apic_id;
462	}	462	}
463		463
464	/** Read from IO APIC register.	464	/** Read from IO APIC register.
465	*	465	*
466	* @param address IO APIC register address.	466	* @param address IO APIC register address.
467	*	467	*
468	* @return Content of the addressed IO APIC register.	468	* @return Content of the addressed IO APIC register.
469	*/	469	*/
470	uint32_t io_apic_read(uint8_t address)	470	uint32_t io_apic_read(uint8_t address)
471	{	471	{
472	io_regsel_t regsel;	472	io_regsel_t regsel;
473		473
474	regsel.value = io_apic[IOREGSEL];	474	regsel.value = io_apic[IOREGSEL];
475	regsel.reg_addr = address;	475	regsel.reg_addr = address;
476	io_apic[IOREGSEL] = regsel.value;	476	io_apic[IOREGSEL] = regsel.value;
477	return io_apic[IOWIN];	477	return io_apic[IOWIN];
478	}	478	}
479		479
480	/** Write to IO APIC register.	480	/** Write to IO APIC register.
481	*	481	*
482	* @param address IO APIC register address.	482	* @param address IO APIC register address.
483	* @param x Content to be written to the addressed IO APIC register.	483	* @param x Content to be written to the addressed IO APIC register.
484	*/	484	*/
485	void io_apic_write(uint8_t address, uint32_t x)	485	void io_apic_write(uint8_t address, uint32_t x)
486	{	486	{
487	io_regsel_t regsel;	487	io_regsel_t regsel;
488		488
489	regsel.value = io_apic[IOREGSEL];	489	regsel.value = io_apic[IOREGSEL];
490	regsel.reg_addr = address;	490	regsel.reg_addr = address;
491	io_apic[IOREGSEL] = regsel.value;	491	io_apic[IOREGSEL] = regsel.value;
492	io_apic[IOWIN] = x;	492	io_apic[IOWIN] = x;
493	}	493	}
494		494
495	/** Change some attributes of one item in I/O Redirection Table.	495	/** Change some attributes of one item in I/O Redirection Table.
496	*	496	*
497	* @param pin IO APIC pin number.	497	* @param pin IO APIC pin number.
498	* @param dest Interrupt destination address.	498	* @param dest Interrupt destination address.
499	* @param v Interrupt vector to trigger.	499	* @param v Interrupt vector to trigger.
500	* @param flags Flags.	500	* @param flags Flags.

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(root)/trunk/kernel/arch/ia32xen/src/smp/apic.c – Rev 2107 → 2457