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1 | # |
1 | # |
2 | # Copyright (C) 2001-2004 Jakub Jermar |
2 | # Copyright (c) 2001-2004 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | ## very low and hardware-level functions |
29 | ## very low and hardware-level functions |
30 | 30 | ||
31 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
32 | # and 1 means interrupt with error word |
32 | # and 1 means interrupt with error word |
33 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
33 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | 34 | ||
35 | .text |
35 | .text |
36 | 36 | ||
37 | .global xen_callback |
37 | .global xen_callback |
38 | .global xen_failsafe_callback |
38 | .global xen_failsafe_callback |
39 | .global enable_l_apic_in_msr |
39 | .global enable_l_apic_in_msr |
40 | .global memcpy |
40 | .global memcpy |
41 | .global memcpy_from_uspace |
41 | .global memcpy_from_uspace |
42 | .global memcpy_from_uspace_failover_address |
42 | .global memcpy_from_uspace_failover_address |
43 | .global memcpy_to_uspace |
43 | .global memcpy_to_uspace |
44 | .global memcpy_to_uspace_failover_address |
44 | .global memcpy_to_uspace_failover_address |
45 | 45 | ||
46 | 46 | ||
47 | xen_callback: |
47 | xen_callback: |
48 | iret |
48 | iret |
49 | 49 | ||
50 | xen_failsafe_callback: |
50 | xen_failsafe_callback: |
51 | iret |
51 | iret |
52 | 52 | ||
53 | 53 | ||
54 | #define MEMCPY_DST 4 |
54 | #define MEMCPY_DST 4 |
55 | #define MEMCPY_SRC 8 |
55 | #define MEMCPY_SRC 8 |
56 | #define MEMCPY_SIZE 12 |
56 | #define MEMCPY_SIZE 12 |
57 | 57 | ||
58 | /** Copy memory to/from userspace. |
58 | /** Copy memory to/from userspace. |
59 | * |
59 | * |
60 | * This is almost conventional memcpy(). |
60 | * This is almost conventional memcpy(). |
61 | * The difference is that there is a failover part |
61 | * The difference is that there is a failover part |
62 | * to where control is returned from a page fault |
62 | * to where control is returned from a page fault |
63 | * if the page fault occurs during copy_from_uspace() |
63 | * if the page fault occurs during copy_from_uspace() |
64 | * or copy_to_uspace(). |
64 | * or copy_to_uspace(). |
65 | * |
65 | * |
66 | * @param MEMCPY_DST(%esp) Destination address. |
66 | * @param MEMCPY_DST(%esp) Destination address. |
67 | * @param MEMCPY_SRC(%esp) Source address. |
67 | * @param MEMCPY_SRC(%esp) Source address. |
68 | * @param MEMCPY_SIZE(%esp) Size. |
68 | * @param MEMCPY_SIZE(%esp) Size. |
69 | * |
69 | * |
70 | * @return MEMCPY_SRC(%esp) on success and 0 on failure. |
70 | * @return MEMCPY_SRC(%esp) on success and 0 on failure. |
71 | */ |
71 | */ |
72 | memcpy: |
72 | memcpy: |
73 | memcpy_from_uspace: |
73 | memcpy_from_uspace: |
74 | memcpy_to_uspace: |
74 | memcpy_to_uspace: |
75 | movl %edi, %edx /* save %edi */ |
75 | movl %edi, %edx /* save %edi */ |
76 | movl %esi, %eax /* save %esi */ |
76 | movl %esi, %eax /* save %esi */ |
77 | 77 | ||
78 | movl MEMCPY_SIZE(%esp), %ecx |
78 | movl MEMCPY_SIZE(%esp), %ecx |
79 | shrl $2, %ecx /* size / 4 */ |
79 | shrl $2, %ecx /* size / 4 */ |
80 | 80 | ||
81 | movl MEMCPY_DST(%esp), %edi |
81 | movl MEMCPY_DST(%esp), %edi |
82 | movl MEMCPY_SRC(%esp), %esi |
82 | movl MEMCPY_SRC(%esp), %esi |
83 | 83 | ||
84 | rep movsl /* copy as much as possible word by word */ |
84 | rep movsl /* copy as much as possible word by word */ |
85 | 85 | ||
86 | movl MEMCPY_SIZE(%esp), %ecx |
86 | movl MEMCPY_SIZE(%esp), %ecx |
87 | andl $3, %ecx /* size % 4 */ |
87 | andl $3, %ecx /* size % 4 */ |
88 | jz 0f |
88 | jz 0f |
89 | 89 | ||
90 | rep movsb /* copy the rest byte by byte */ |
90 | rep movsb /* copy the rest byte by byte */ |
91 | 91 | ||
92 | 0: |
92 | 0: |
93 | movl %edx, %edi |
93 | movl %edx, %edi |
94 | movl %eax, %esi |
94 | movl %eax, %esi |
95 | movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */ |
95 | movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */ |
96 | ret |
96 | ret |
97 | 97 | ||
98 | /* |
98 | /* |
99 | * We got here from as_page_fault() after the memory operations |
99 | * We got here from as_page_fault() after the memory operations |
100 | * above had caused a page fault. |
100 | * above had caused a page fault. |
101 | */ |
101 | */ |
102 | memcpy_from_uspace_failover_address: |
102 | memcpy_from_uspace_failover_address: |
103 | memcpy_to_uspace_failover_address: |
103 | memcpy_to_uspace_failover_address: |
104 | movl %edx, %edi |
104 | movl %edx, %edi |
105 | movl %eax, %esi |
105 | movl %eax, %esi |
106 | xorl %eax, %eax /* return 0, failure */ |
106 | xorl %eax, %eax /* return 0, failure */ |
107 | ret |
107 | ret |
108 | 108 | ||
109 | 109 | ||
110 | ## Enable local APIC |
110 | ## Enable local APIC |
111 | # |
111 | # |
112 | # Enable local APIC in MSR. |
112 | # Enable local APIC in MSR. |
113 | # |
113 | # |
114 | enable_l_apic_in_msr: |
114 | enable_l_apic_in_msr: |
115 | push %eax |
115 | push %eax |
116 | 116 | ||
117 | movl $0x1b, %ecx |
117 | movl $0x1b, %ecx |
118 | rdmsr |
118 | rdmsr |
119 | orl $(1<<11),%eax |
119 | orl $(1<<11),%eax |
120 | orl $(0xfee00000),%eax |
120 | orl $(0xfee00000),%eax |
121 | wrmsr |
121 | wrmsr |
122 | 122 | ||
123 | pop %eax |
123 | pop %eax |
124 | ret |
124 | ret |
125 | 125 |