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1 | /* |
1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
3 | * Copyright (c) 2005 Sergey Bondari |
3 | * Copyright (c) 2005 Sergey Bondari |
4 | * Copyright (c) 2006 Martin Decky |
4 | * Copyright (c) 2006 Martin Decky |
5 | * All rights reserved. |
5 | * All rights reserved. |
6 | * |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
9 | * are met: |
10 | * |
10 | * |
11 | * - Redistributions of source code must retain the above copyright |
11 | * - Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. |
12 | * notice, this list of conditions and the following disclaimer. |
13 | * - Redistributions in binary form must reproduce the above copyright |
13 | * - Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
15 | * documentation and/or other materials provided with the distribution. |
16 | * - The name of the author may not be used to endorse or promote products |
16 | * - The name of the author may not be used to endorse or promote products |
17 | * derived from this software without specific prior written permission. |
17 | * derived from this software without specific prior written permission. |
18 | * |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
29 | */ |
29 | */ |
30 | 30 | ||
31 | /** @addtogroup ia32xen |
31 | /** @addtogroup ia32xen |
32 | * @{ |
32 | * @{ |
33 | */ |
33 | */ |
34 | /** @file |
34 | /** @file |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #ifndef KERN_ia32xen_ASM_H_ |
37 | #ifndef KERN_ia32xen_ASM_H_ |
38 | #define KERN_ia32xen_ASM_H_ |
38 | #define KERN_ia32xen_ASM_H_ |
39 | 39 | ||
40 | #include <arch/pm.h> |
40 | #include <arch/pm.h> |
41 | #include <arch/types.h> |
41 | #include <arch/types.h> |
42 | #include <arch/barrier.h> |
42 | #include <arch/barrier.h> |
43 | #include <config.h> |
43 | #include <config.h> |
44 | 44 | ||
45 | extern void enable_l_apic_in_msr(void); |
45 | extern void enable_l_apic_in_msr(void); |
46 | 46 | ||
47 | 47 | ||
48 | extern void asm_delay_loop(uint32_t t); |
48 | extern void asm_delay_loop(uint32_t t); |
49 | extern void asm_fake_loop(uint32_t t); |
49 | extern void asm_fake_loop(uint32_t t); |
50 | 50 | ||
51 | 51 | ||
52 | /** Halt CPU |
52 | /** Halt CPU |
53 | * |
53 | * |
54 | * Halt the current CPU until interrupt event. |
54 | * Halt the current CPU until interrupt event. |
55 | */ |
55 | */ |
56 | #define cpu_halt() ((void) 0) |
56 | #define cpu_halt() ((void) 0) |
57 | #define cpu_sleep() ((void) 0) |
57 | #define cpu_sleep() ((void) 0) |
58 | 58 | ||
59 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
59 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
60 | { \ |
60 | { \ |
61 | unative_t res; \ |
61 | unative_t res; \ |
62 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
62 | asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
63 | return res; \ |
63 | return res; \ |
64 | } |
64 | } |
65 | 65 | ||
66 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
66 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
67 | { \ |
67 | { \ |
68 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
68 | asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
69 | } |
69 | } |
70 | 70 | ||
71 | GEN_READ_REG(cr0); |
71 | GEN_READ_REG(cr0); |
72 | GEN_READ_REG(cr2); |
72 | GEN_READ_REG(cr2); |
73 | 73 | ||
74 | GEN_READ_REG(dr0); |
74 | GEN_READ_REG(dr0); |
75 | GEN_READ_REG(dr1); |
75 | GEN_READ_REG(dr1); |
76 | GEN_READ_REG(dr2); |
76 | GEN_READ_REG(dr2); |
77 | GEN_READ_REG(dr3); |
77 | GEN_READ_REG(dr3); |
78 | GEN_READ_REG(dr6); |
78 | GEN_READ_REG(dr6); |
79 | GEN_READ_REG(dr7); |
79 | GEN_READ_REG(dr7); |
80 | 80 | ||
81 | GEN_WRITE_REG(dr0); |
81 | GEN_WRITE_REG(dr0); |
82 | GEN_WRITE_REG(dr1); |
82 | GEN_WRITE_REG(dr1); |
83 | GEN_WRITE_REG(dr2); |
83 | GEN_WRITE_REG(dr2); |
84 | GEN_WRITE_REG(dr3); |
84 | GEN_WRITE_REG(dr3); |
85 | GEN_WRITE_REG(dr6); |
85 | GEN_WRITE_REG(dr6); |
86 | GEN_WRITE_REG(dr7); |
86 | GEN_WRITE_REG(dr7); |
87 | 87 | ||
88 | /** Byte to port |
88 | /** Byte to port |
89 | * |
89 | * |
90 | * Output byte to port |
90 | * Output byte to port |
91 | * |
91 | * |
92 | * @param port Port to write to |
92 | * @param port Port to write to |
93 | * @param val Value to write |
93 | * @param val Value to write |
94 | */ |
94 | */ |
95 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
95 | static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
96 | 96 | ||
97 | /** Word to port |
97 | /** Word to port |
98 | * |
98 | * |
99 | * Output word to port |
99 | * Output word to port |
100 | * |
100 | * |
101 | * @param port Port to write to |
101 | * @param port Port to write to |
102 | * @param val Value to write |
102 | * @param val Value to write |
103 | */ |
103 | */ |
104 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
104 | static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
105 | 105 | ||
106 | /** Double word to port |
106 | /** Double word to port |
107 | * |
107 | * |
108 | * Output double word to port |
108 | * Output double word to port |
109 | * |
109 | * |
110 | * @param port Port to write to |
110 | * @param port Port to write to |
111 | * @param val Value to write |
111 | * @param val Value to write |
112 | */ |
112 | */ |
113 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
113 | static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
114 | 114 | ||
115 | /** Byte from port |
115 | /** Byte from port |
116 | * |
116 | * |
117 | * Get byte from port |
117 | * Get byte from port |
118 | * |
118 | * |
119 | * @param port Port to read from |
119 | * @param port Port to read from |
120 | * @return Value read |
120 | * @return Value read |
121 | */ |
121 | */ |
122 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
122 | static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
123 | 123 | ||
124 | /** Word from port |
124 | /** Word from port |
125 | * |
125 | * |
126 | * Get word from port |
126 | * Get word from port |
127 | * |
127 | * |
128 | * @param port Port to read from |
128 | * @param port Port to read from |
129 | * @return Value read |
129 | * @return Value read |
130 | */ |
130 | */ |
131 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
131 | static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
132 | 132 | ||
133 | /** Double word from port |
133 | /** Double word from port |
134 | * |
134 | * |
135 | * Get double word from port |
135 | * Get double word from port |
136 | * |
136 | * |
137 | * @param port Port to read from |
137 | * @param port Port to read from |
138 | * @return Value read |
138 | * @return Value read |
139 | */ |
139 | */ |
140 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
140 | static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
141 | 141 | ||
142 | /** Enable interrupts. |
142 | /** Enable interrupts. |
143 | * |
143 | * |
144 | * Enable interrupts and return previous |
144 | * Enable interrupts and return previous |
145 | * value of EFLAGS. |
145 | * value of EFLAGS. |
146 | * |
146 | * |
147 | * @return Old interrupt priority level. |
147 | * @return Old interrupt priority level. |
148 | */ |
148 | */ |
149 | static inline ipl_t interrupts_enable(void) |
149 | static inline ipl_t interrupts_enable(void) |
150 | { |
150 | { |
151 | // FIXME SMP |
151 | // FIXME SMP |
152 | 152 | ||
153 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
153 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
154 | write_barrier(); |
154 | write_barrier(); |
155 | shared_info.vcpu_info[0].evtchn_upcall_mask = 0; |
155 | shared_info.vcpu_info[0].evtchn_upcall_mask = 0; |
156 | write_barrier(); |
156 | write_barrier(); |
157 | if (shared_info.vcpu_info[0].evtchn_upcall_pending) |
157 | if (shared_info.vcpu_info[0].evtchn_upcall_pending) |
158 | force_evtchn_callback(); |
158 | force_evtchn_callback(); |
159 | 159 | ||
160 | return v; |
160 | return v; |
161 | } |
161 | } |
162 | 162 | ||
163 | /** Disable interrupts. |
163 | /** Disable interrupts. |
164 | * |
164 | * |
165 | * Disable interrupts and return previous |
165 | * Disable interrupts and return previous |
166 | * value of EFLAGS. |
166 | * value of EFLAGS. |
167 | * |
167 | * |
168 | * @return Old interrupt priority level. |
168 | * @return Old interrupt priority level. |
169 | */ |
169 | */ |
170 | static inline ipl_t interrupts_disable(void) |
170 | static inline ipl_t interrupts_disable(void) |
171 | { |
171 | { |
172 | // FIXME SMP |
172 | // FIXME SMP |
173 | 173 | ||
174 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
174 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
175 | shared_info.vcpu_info[0].evtchn_upcall_mask = 1; |
175 | shared_info.vcpu_info[0].evtchn_upcall_mask = 1; |
176 | write_barrier(); |
176 | write_barrier(); |
177 | 177 | ||
178 | return v; |
178 | return v; |
179 | } |
179 | } |
180 | 180 | ||
181 | /** Restore interrupt priority level. |
181 | /** Restore interrupt priority level. |
182 | * |
182 | * |
183 | * Restore EFLAGS. |
183 | * Restore EFLAGS. |
184 | * |
184 | * |
185 | * @param ipl Saved interrupt priority level. |
185 | * @param ipl Saved interrupt priority level. |
186 | */ |
186 | */ |
187 | static inline void interrupts_restore(ipl_t ipl) |
187 | static inline void interrupts_restore(ipl_t ipl) |
188 | { |
188 | { |
189 | if (ipl == 0) |
189 | if (ipl == 0) |
190 | interrupts_enable(); |
190 | interrupts_enable(); |
191 | else |
191 | else |
192 | interrupts_disable(); |
192 | interrupts_disable(); |
193 | } |
193 | } |
194 | 194 | ||
195 | /** Return interrupt priority level. |
195 | /** Return interrupt priority level. |
196 | * |
196 | * |
197 | * @return EFLAFS. |
197 | * @return EFLAFS. |
198 | */ |
198 | */ |
199 | static inline ipl_t interrupts_read(void) |
199 | static inline ipl_t interrupts_read(void) |
200 | { |
200 | { |
201 | // FIXME SMP |
201 | // FIXME SMP |
202 | 202 | ||
203 | return shared_info.vcpu_info[0].evtchn_upcall_mask; |
203 | return shared_info.vcpu_info[0].evtchn_upcall_mask; |
204 | } |
204 | } |
205 | 205 | ||
206 | /** Return base address of current stack |
206 | /** Return base address of current stack |
207 | * |
207 | * |
208 | * Return the base address of the current stack. |
208 | * Return the base address of the current stack. |
209 | * The stack is assumed to be STACK_SIZE bytes long. |
209 | * The stack is assumed to be STACK_SIZE bytes long. |
210 | * The stack must start on page boundary. |
210 | * The stack must start on page boundary. |
211 | */ |
211 | */ |
212 | static inline uintptr_t get_stack_base(void) |
212 | static inline uintptr_t get_stack_base(void) |
213 | { |
213 | { |
214 | uintptr_t v; |
214 | uintptr_t v; |
215 | 215 | ||
216 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
216 | asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
217 | 217 | ||
218 | return v; |
218 | return v; |
219 | } |
219 | } |
220 | 220 | ||
221 | /** Return current IP address */ |
221 | /** Return current IP address */ |
222 | static inline uintptr_t * get_ip() |
222 | static inline uintptr_t * get_ip() |
223 | { |
223 | { |
224 | uintptr_t *ip; |
224 | uintptr_t *ip; |
225 | 225 | ||
226 | __asm__ volatile ( |
226 | asm volatile ( |
227 | "mov %%eip, %0" |
227 | "mov %%eip, %0" |
228 | : "=r" (ip) |
228 | : "=r" (ip) |
229 | ); |
229 | ); |
230 | return ip; |
230 | return ip; |
231 | } |
231 | } |
232 | 232 | ||
233 | /** Invalidate TLB Entry. |
233 | /** Invalidate TLB Entry. |
234 | * |
234 | * |
235 | * @param addr Address on a page whose TLB entry is to be invalidated. |
235 | * @param addr Address on a page whose TLB entry is to be invalidated. |
236 | */ |
236 | */ |
237 | static inline void invlpg(uintptr_t addr) |
237 | static inline void invlpg(uintptr_t addr) |
238 | { |
238 | { |
239 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
239 | asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
240 | } |
240 | } |
241 | 241 | ||
242 | /** Load GDTR register from memory. |
242 | /** Load GDTR register from memory. |
243 | * |
243 | * |
244 | * @param gdtr_reg Address of memory from where to load GDTR. |
244 | * @param gdtr_reg Address of memory from where to load GDTR. |
245 | */ |
245 | */ |
246 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
246 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
247 | { |
247 | { |
248 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
248 | asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
249 | } |
249 | } |
250 | 250 | ||
251 | /** Store GDTR register to memory. |
251 | /** Store GDTR register to memory. |
252 | * |
252 | * |
253 | * @param gdtr_reg Address of memory to where to load GDTR. |
253 | * @param gdtr_reg Address of memory to where to load GDTR. |
254 | */ |
254 | */ |
255 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
255 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
256 | { |
256 | { |
257 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
257 | asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
258 | } |
258 | } |
259 | 259 | ||
260 | /** Load TR from descriptor table. |
260 | /** Load TR from descriptor table. |
261 | * |
261 | * |
262 | * @param sel Selector specifying descriptor of TSS segment. |
262 | * @param sel Selector specifying descriptor of TSS segment. |
263 | */ |
263 | */ |
264 | static inline void tr_load(uint16_t sel) |
264 | static inline void tr_load(uint16_t sel) |
265 | { |
265 | { |
266 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
266 | asm volatile ("ltr %0" : : "r" (sel)); |
267 | } |
267 | } |
268 | 268 | ||
269 | #endif |
269 | #endif |
270 | 270 | ||
271 | /** @} |
271 | /** @} |
272 | */ |
272 | */ |
273 | 273 |