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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * Copyright (C) 2005 Sergey Bondari |
3 | * Copyright (C) 2005 Sergey Bondari |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup xen32 |
30 | /** @addtogroup xen32 |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef __xen32_ASM_H__ |
36 | #ifndef __xen32_ASM_H__ |
37 | #define __xen32_ASM_H__ |
37 | #define __xen32_ASM_H__ |
38 | 38 | ||
39 | #include <arch/pm.h> |
39 | #include <arch/pm.h> |
40 | #include <arch/types.h> |
40 | #include <arch/types.h> |
41 | #include <config.h> |
41 | #include <config.h> |
42 | 42 | ||
43 | extern uint32_t interrupt_handler_size; |
43 | extern uint32_t interrupt_handler_size; |
44 | 44 | ||
45 | extern void paging_on(void); |
- | |
46 | - | ||
47 | extern void interrupt_handlers(void); |
45 | extern void interrupt_handlers(void); |
48 | 46 | ||
49 | extern void enable_l_apic_in_msr(void); |
47 | extern void enable_l_apic_in_msr(void); |
50 | 48 | ||
51 | 49 | ||
52 | extern void asm_delay_loop(uint32_t t); |
50 | extern void asm_delay_loop(uint32_t t); |
53 | extern void asm_fake_loop(uint32_t t); |
51 | extern void asm_fake_loop(uint32_t t); |
54 | 52 | ||
55 | 53 | ||
56 | /** Halt CPU |
54 | /** Halt CPU |
57 | * |
55 | * |
58 | * Halt the current CPU until interrupt event. |
56 | * Halt the current CPU until interrupt event. |
59 | */ |
57 | */ |
60 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
58 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
61 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
59 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
62 | 60 | ||
63 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
61 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
64 | { \ |
62 | { \ |
65 | unative_t res; \ |
63 | unative_t res; \ |
66 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
64 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
67 | return res; \ |
65 | return res; \ |
68 | } |
66 | } |
69 | 67 | ||
70 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
68 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
71 | { \ |
69 | { \ |
72 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
70 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
73 | } |
71 | } |
74 | 72 | ||
75 | GEN_READ_REG(cr0); |
73 | GEN_READ_REG(cr0); |
76 | GEN_READ_REG(cr2); |
74 | GEN_READ_REG(cr2); |
77 | GEN_READ_REG(cr3); |
- | |
78 | GEN_WRITE_REG(cr3); |
- | |
79 | 75 | ||
80 | GEN_READ_REG(dr0); |
76 | GEN_READ_REG(dr0); |
81 | GEN_READ_REG(dr1); |
77 | GEN_READ_REG(dr1); |
82 | GEN_READ_REG(dr2); |
78 | GEN_READ_REG(dr2); |
83 | GEN_READ_REG(dr3); |
79 | GEN_READ_REG(dr3); |
84 | GEN_READ_REG(dr6); |
80 | GEN_READ_REG(dr6); |
85 | GEN_READ_REG(dr7); |
81 | GEN_READ_REG(dr7); |
86 | 82 | ||
87 | GEN_WRITE_REG(dr0); |
83 | GEN_WRITE_REG(dr0); |
88 | GEN_WRITE_REG(dr1); |
84 | GEN_WRITE_REG(dr1); |
89 | GEN_WRITE_REG(dr2); |
85 | GEN_WRITE_REG(dr2); |
90 | GEN_WRITE_REG(dr3); |
86 | GEN_WRITE_REG(dr3); |
91 | GEN_WRITE_REG(dr6); |
87 | GEN_WRITE_REG(dr6); |
92 | GEN_WRITE_REG(dr7); |
88 | GEN_WRITE_REG(dr7); |
93 | 89 | ||
94 | /** Byte to port |
90 | /** Byte to port |
95 | * |
91 | * |
96 | * Output byte to port |
92 | * Output byte to port |
97 | * |
93 | * |
98 | * @param port Port to write to |
94 | * @param port Port to write to |
99 | * @param val Value to write |
95 | * @param val Value to write |
100 | */ |
96 | */ |
101 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
97 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
102 | 98 | ||
103 | /** Word to port |
99 | /** Word to port |
104 | * |
100 | * |
105 | * Output word to port |
101 | * Output word to port |
106 | * |
102 | * |
107 | * @param port Port to write to |
103 | * @param port Port to write to |
108 | * @param val Value to write |
104 | * @param val Value to write |
109 | */ |
105 | */ |
110 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
106 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
111 | 107 | ||
112 | /** Double word to port |
108 | /** Double word to port |
113 | * |
109 | * |
114 | * Output double word to port |
110 | * Output double word to port |
115 | * |
111 | * |
116 | * @param port Port to write to |
112 | * @param port Port to write to |
117 | * @param val Value to write |
113 | * @param val Value to write |
118 | */ |
114 | */ |
119 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
115 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
120 | 116 | ||
121 | /** Byte from port |
117 | /** Byte from port |
122 | * |
118 | * |
123 | * Get byte from port |
119 | * Get byte from port |
124 | * |
120 | * |
125 | * @param port Port to read from |
121 | * @param port Port to read from |
126 | * @return Value read |
122 | * @return Value read |
127 | */ |
123 | */ |
128 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
124 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
129 | 125 | ||
130 | /** Word from port |
126 | /** Word from port |
131 | * |
127 | * |
132 | * Get word from port |
128 | * Get word from port |
133 | * |
129 | * |
134 | * @param port Port to read from |
130 | * @param port Port to read from |
135 | * @return Value read |
131 | * @return Value read |
136 | */ |
132 | */ |
137 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
133 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
138 | 134 | ||
139 | /** Double word from port |
135 | /** Double word from port |
140 | * |
136 | * |
141 | * Get double word from port |
137 | * Get double word from port |
142 | * |
138 | * |
143 | * @param port Port to read from |
139 | * @param port Port to read from |
144 | * @return Value read |
140 | * @return Value read |
145 | */ |
141 | */ |
146 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
142 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
147 | 143 | ||
148 | /** Enable interrupts. |
144 | /** Enable interrupts. |
149 | * |
145 | * |
150 | * Enable interrupts and return previous |
146 | * Enable interrupts and return previous |
151 | * value of EFLAGS. |
147 | * value of EFLAGS. |
152 | * |
148 | * |
153 | * @return Old interrupt priority level. |
149 | * @return Old interrupt priority level. |
154 | */ |
150 | */ |
155 | static inline ipl_t interrupts_enable(void) |
151 | static inline ipl_t interrupts_enable(void) |
156 | { |
152 | { |
157 | ipl_t v = 0; |
153 | ipl_t v = 0; |
158 | /* __asm__ volatile ( |
154 | /* __asm__ volatile ( |
159 | "pushf\n\t" |
155 | "pushf\n\t" |
160 | "popl %0\n\t" |
156 | "popl %0\n\t" |
161 | "sti\n" |
157 | "sti\n" |
162 | : "=r" (v) |
158 | : "=r" (v) |
163 | );*/ |
159 | );*/ |
164 | return v; |
160 | return v; |
165 | } |
161 | } |
166 | 162 | ||
167 | /** Disable interrupts. |
163 | /** Disable interrupts. |
168 | * |
164 | * |
169 | * Disable interrupts and return previous |
165 | * Disable interrupts and return previous |
170 | * value of EFLAGS. |
166 | * value of EFLAGS. |
171 | * |
167 | * |
172 | * @return Old interrupt priority level. |
168 | * @return Old interrupt priority level. |
173 | */ |
169 | */ |
174 | static inline ipl_t interrupts_disable(void) |
170 | static inline ipl_t interrupts_disable(void) |
175 | { |
171 | { |
176 | ipl_t v = 0; |
172 | ipl_t v = 0; |
177 | /* __asm__ volatile ( |
173 | /* __asm__ volatile ( |
178 | "pushf\n\t" |
174 | "pushf\n\t" |
179 | "popl %0\n\t" |
175 | "popl %0\n\t" |
180 | "cli\n" |
176 | "cli\n" |
181 | : "=r" (v) |
177 | : "=r" (v) |
182 | );*/ |
178 | );*/ |
183 | return v; |
179 | return v; |
184 | } |
180 | } |
185 | 181 | ||
186 | /** Restore interrupt priority level. |
182 | /** Restore interrupt priority level. |
187 | * |
183 | * |
188 | * Restore EFLAGS. |
184 | * Restore EFLAGS. |
189 | * |
185 | * |
190 | * @param ipl Saved interrupt priority level. |
186 | * @param ipl Saved interrupt priority level. |
191 | */ |
187 | */ |
192 | static inline void interrupts_restore(ipl_t ipl) |
188 | static inline void interrupts_restore(ipl_t ipl) |
193 | { |
189 | { |
194 | /* __asm__ volatile ( |
190 | /* __asm__ volatile ( |
195 | "pushl %0\n\t" |
191 | "pushl %0\n\t" |
196 | "popf\n" |
192 | "popf\n" |
197 | : : "r" (ipl) |
193 | : : "r" (ipl) |
198 | );*/ |
194 | );*/ |
199 | } |
195 | } |
200 | 196 | ||
201 | /** Return interrupt priority level. |
197 | /** Return interrupt priority level. |
202 | * |
198 | * |
203 | * @return EFLAFS. |
199 | * @return EFLAFS. |
204 | */ |
200 | */ |
205 | static inline ipl_t interrupts_read(void) |
201 | static inline ipl_t interrupts_read(void) |
206 | { |
202 | { |
207 | ipl_t v = 0; |
203 | ipl_t v = 0; |
208 | /* __asm__ volatile ( |
204 | /* __asm__ volatile ( |
209 | "pushf\n\t" |
205 | "pushf\n\t" |
210 | "popl %0\n" |
206 | "popl %0\n" |
211 | : "=r" (v) |
207 | : "=r" (v) |
212 | );*/ |
208 | );*/ |
213 | return v; |
209 | return v; |
214 | } |
210 | } |
215 | 211 | ||
216 | /** Return base address of current stack |
212 | /** Return base address of current stack |
217 | * |
213 | * |
218 | * Return the base address of the current stack. |
214 | * Return the base address of the current stack. |
219 | * The stack is assumed to be STACK_SIZE bytes long. |
215 | * The stack is assumed to be STACK_SIZE bytes long. |
220 | * The stack must start on page boundary. |
216 | * The stack must start on page boundary. |
221 | */ |
217 | */ |
222 | static inline uintptr_t get_stack_base(void) |
218 | static inline uintptr_t get_stack_base(void) |
223 | { |
219 | { |
224 | uintptr_t v; |
220 | uintptr_t v; |
225 | 221 | ||
226 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
222 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
227 | 223 | ||
228 | return v; |
224 | return v; |
229 | } |
225 | } |
230 | 226 | ||
231 | static inline uint64_t rdtsc(void) |
227 | static inline uint64_t rdtsc(void) |
232 | { |
228 | { |
233 | uint64_t v; |
229 | uint64_t v; |
234 | 230 | ||
235 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
231 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
236 | 232 | ||
237 | return v; |
233 | return v; |
238 | } |
234 | } |
239 | 235 | ||
240 | /** Return current IP address */ |
236 | /** Return current IP address */ |
241 | static inline uintptr_t * get_ip() |
237 | static inline uintptr_t * get_ip() |
242 | { |
238 | { |
243 | uintptr_t *ip; |
239 | uintptr_t *ip; |
244 | 240 | ||
245 | __asm__ volatile ( |
241 | __asm__ volatile ( |
246 | "mov %%eip, %0" |
242 | "mov %%eip, %0" |
247 | : "=r" (ip) |
243 | : "=r" (ip) |
248 | ); |
244 | ); |
249 | return ip; |
245 | return ip; |
250 | } |
246 | } |
251 | 247 | ||
252 | /** Invalidate TLB Entry. |
248 | /** Invalidate TLB Entry. |
253 | * |
249 | * |
254 | * @param addr Address on a page whose TLB entry is to be invalidated. |
250 | * @param addr Address on a page whose TLB entry is to be invalidated. |
255 | */ |
251 | */ |
256 | static inline void invlpg(uintptr_t addr) |
252 | static inline void invlpg(uintptr_t addr) |
257 | { |
253 | { |
258 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
254 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
259 | } |
255 | } |
260 | 256 | ||
261 | /** Load GDTR register from memory. |
257 | /** Load GDTR register from memory. |
262 | * |
258 | * |
263 | * @param gdtr_reg Address of memory from where to load GDTR. |
259 | * @param gdtr_reg Address of memory from where to load GDTR. |
264 | */ |
260 | */ |
265 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
261 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
266 | { |
262 | { |
267 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
263 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
268 | } |
264 | } |
269 | 265 | ||
270 | /** Store GDTR register to memory. |
266 | /** Store GDTR register to memory. |
271 | * |
267 | * |
272 | * @param gdtr_reg Address of memory to where to load GDTR. |
268 | * @param gdtr_reg Address of memory to where to load GDTR. |
273 | */ |
269 | */ |
274 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
270 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
275 | { |
271 | { |
276 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
272 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
277 | } |
273 | } |
278 | 274 | ||
279 | /** Load IDTR register from memory. |
275 | /** Load IDTR register from memory. |
280 | * |
276 | * |
281 | * @param idtr_reg Address of memory from where to load IDTR. |
277 | * @param idtr_reg Address of memory from where to load IDTR. |
282 | */ |
278 | */ |
283 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
279 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
284 | { |
280 | { |
285 | __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
281 | __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
286 | } |
282 | } |
287 | 283 | ||
288 | /** Load TR from descriptor table. |
284 | /** Load TR from descriptor table. |
289 | * |
285 | * |
290 | * @param sel Selector specifying descriptor of TSS segment. |
286 | * @param sel Selector specifying descriptor of TSS segment. |
291 | */ |
287 | */ |
292 | static inline void tr_load(uint16_t sel) |
288 | static inline void tr_load(uint16_t sel) |
293 | { |
289 | { |
294 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
290 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
295 | } |
291 | } |
296 | 292 | ||
297 | #endif |
293 | #endif |
298 | 294 | ||
299 | /** @} |
295 | /** @} |
300 | */ |
296 | */ |
301 | 297 |