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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <arch/boot/boot.h> |
33 | #include <arch/boot/boot.h> |
34 | #include <mm/page.h> |
34 | #include <mm/page.h> |
35 | #include <time/delay.h> |
35 | #include <time/delay.h> |
36 | #include <interrupt.h> |
36 | #include <interrupt.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <print.h> |
38 | #include <print.h> |
39 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | 41 | ||
42 | #ifdef CONFIG_SMP |
42 | #ifdef CONFIG_SMP |
43 | 43 | ||
44 | /* |
44 | /* |
45 | * Advanced Programmable Interrupt Controller for SMP systems. |
45 | * Advanced Programmable Interrupt Controller for SMP systems. |
46 | * Tested on: |
46 | * Tested on: |
47 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
47 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
49 | * VMware Workstation 5.5 with 2 CPUs |
49 | * VMware Workstation 5.5 with 2 CPUs |
- | 50 | * QEMU 0.8.0 with 2-15 CPUs |
|
50 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
51 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
51 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
52 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
52 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
53 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
53 | */ |
54 | */ |
54 | 55 | ||
55 | /* |
56 | /* |
56 | * These variables either stay configured as initilalized, or are changed by |
57 | * These variables either stay configured as initilalized, or are changed by |
57 | * the MP configuration code. |
58 | * the MP configuration code. |
58 | * |
59 | * |
59 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
60 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
60 | * optimize the code too much and accesses to l_apic and io_apic, that must |
61 | * optimize the code too much and accesses to l_apic and io_apic, that must |
61 | * always be 32-bit, would use byte oriented instructions. |
62 | * always be 32-bit, would use byte oriented instructions. |
62 | */ |
63 | */ |
63 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
64 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
64 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
65 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
65 | 66 | ||
66 | __u32 apic_id_mask = 0; |
67 | __u32 apic_id_mask = 0; |
67 | 68 | ||
68 | static int apic_poll_errors(void); |
69 | static int apic_poll_errors(void); |
69 | 70 | ||
70 | #ifdef LAPIC_VERBOSE |
71 | #ifdef LAPIC_VERBOSE |
71 | static char *delmod_str[] = { |
72 | static char *delmod_str[] = { |
72 | "Fixed", |
73 | "Fixed", |
73 | "Lowest Priority", |
74 | "Lowest Priority", |
74 | "SMI", |
75 | "SMI", |
75 | "Reserved", |
76 | "Reserved", |
76 | "NMI", |
77 | "NMI", |
77 | "INIT", |
78 | "INIT", |
78 | "STARTUP", |
79 | "STARTUP", |
79 | "ExtInt" |
80 | "ExtInt" |
80 | }; |
81 | }; |
81 | 82 | ||
82 | static char *destmod_str[] = { |
83 | static char *destmod_str[] = { |
83 | "Physical", |
84 | "Physical", |
84 | "Logical" |
85 | "Logical" |
85 | }; |
86 | }; |
86 | 87 | ||
87 | static char *trigmod_str[] = { |
88 | static char *trigmod_str[] = { |
88 | "Edge", |
89 | "Edge", |
89 | "Level" |
90 | "Level" |
90 | }; |
91 | }; |
91 | 92 | ||
92 | static char *mask_str[] = { |
93 | static char *mask_str[] = { |
93 | "Unmasked", |
94 | "Unmasked", |
94 | "Masked" |
95 | "Masked" |
95 | }; |
96 | }; |
96 | 97 | ||
97 | static char *delivs_str[] = { |
98 | static char *delivs_str[] = { |
98 | "Idle", |
99 | "Idle", |
99 | "Send Pending" |
100 | "Send Pending" |
100 | }; |
101 | }; |
101 | 102 | ||
102 | static char *tm_mode_str[] = { |
103 | static char *tm_mode_str[] = { |
103 | "One-shot", |
104 | "One-shot", |
104 | "Periodic" |
105 | "Periodic" |
105 | }; |
106 | }; |
106 | 107 | ||
107 | static char *intpol_str[] = { |
108 | static char *intpol_str[] = { |
108 | "Polarity High", |
109 | "Polarity High", |
109 | "Polarity Low" |
110 | "Polarity Low" |
110 | }; |
111 | }; |
111 | #endif /* LAPIC_VERBOSE */ |
112 | #endif /* LAPIC_VERBOSE */ |
112 | 113 | ||
113 | 114 | ||
114 | static void apic_spurious(int n, void *stack); |
115 | static void apic_spurious(int n, void *stack); |
115 | static void l_apic_timer_interrupt(int n, void *stack); |
116 | static void l_apic_timer_interrupt(int n, void *stack); |
116 | 117 | ||
117 | /** Initialize APIC on BSP. */ |
118 | /** Initialize APIC on BSP. */ |
118 | void apic_init(void) |
119 | void apic_init(void) |
119 | { |
120 | { |
120 | io_apic_id_t idreg; |
121 | io_apic_id_t idreg; |
121 | int i; |
122 | int i; |
122 | 123 | ||
123 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
124 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
124 | 125 | ||
125 | enable_irqs_function = io_apic_enable_irqs; |
126 | enable_irqs_function = io_apic_enable_irqs; |
126 | disable_irqs_function = io_apic_disable_irqs; |
127 | disable_irqs_function = io_apic_disable_irqs; |
127 | eoi_function = l_apic_eoi; |
128 | eoi_function = l_apic_eoi; |
128 | 129 | ||
129 | /* |
130 | /* |
130 | * Configure interrupt routing. |
131 | * Configure interrupt routing. |
131 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
132 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
132 | * Other interrupts will be forwarded to the lowest priority CPU. |
133 | * Other interrupts will be forwarded to the lowest priority CPU. |
133 | */ |
134 | */ |
134 | io_apic_disable_irqs(0xffff); |
135 | io_apic_disable_irqs(0xffff); |
135 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
136 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
136 | for (i = 0; i < IRQ_COUNT; i++) { |
137 | for (i = 0; i < IRQ_COUNT; i++) { |
137 | int pin; |
138 | int pin; |
138 | 139 | ||
139 | if ((pin = smp_irq_to_pin(i)) != -1) { |
140 | if ((pin = smp_irq_to_pin(i)) != -1) { |
140 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
141 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
141 | } |
142 | } |
142 | } |
143 | } |
143 | 144 | ||
144 | /* |
145 | /* |
145 | * Ensure that io_apic has unique ID. |
146 | * Ensure that io_apic has unique ID. |
146 | */ |
147 | */ |
147 | idreg.value = io_apic_read(IOAPICID); |
148 | idreg.value = io_apic_read(IOAPICID); |
148 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
149 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
149 | for (i = 0; i < APIC_ID_COUNT; i++) { |
150 | for (i = 0; i < APIC_ID_COUNT; i++) { |
150 | if (!((1<<i) & apic_id_mask)) { |
151 | if (!((1<<i) & apic_id_mask)) { |
151 | idreg.apic_id = i; |
152 | idreg.apic_id = i; |
152 | io_apic_write(IOAPICID, idreg.value); |
153 | io_apic_write(IOAPICID, idreg.value); |
153 | break; |
154 | break; |
154 | } |
155 | } |
155 | } |
156 | } |
156 | } |
157 | } |
157 | 158 | ||
158 | /* |
159 | /* |
159 | * Configure the BSP's lapic. |
160 | * Configure the BSP's lapic. |
160 | */ |
161 | */ |
161 | l_apic_init(); |
162 | l_apic_init(); |
162 | 163 | ||
163 | l_apic_debug(); |
164 | l_apic_debug(); |
164 | } |
165 | } |
165 | 166 | ||
166 | /** APIC spurious interrupt handler. |
167 | /** APIC spurious interrupt handler. |
167 | * |
168 | * |
168 | * @param n Interrupt vector. |
169 | * @param n Interrupt vector. |
169 | * @param stack Interrupted stack. |
170 | * @param stack Interrupted stack. |
170 | */ |
171 | */ |
171 | void apic_spurious(int n, void *stack) |
172 | void apic_spurious(int n, void *stack) |
172 | { |
173 | { |
173 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
174 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
174 | } |
175 | } |
175 | 176 | ||
176 | /** Poll for APIC errors. |
177 | /** Poll for APIC errors. |
177 | * |
178 | * |
178 | * Examine Error Status Register and report all errors found. |
179 | * Examine Error Status Register and report all errors found. |
179 | * |
180 | * |
180 | * @return 0 on error, 1 on success. |
181 | * @return 0 on error, 1 on success. |
181 | */ |
182 | */ |
182 | int apic_poll_errors(void) |
183 | int apic_poll_errors(void) |
183 | { |
184 | { |
184 | esr_t esr; |
185 | esr_t esr; |
185 | 186 | ||
186 | esr.value = l_apic[ESR]; |
187 | esr.value = l_apic[ESR]; |
187 | 188 | ||
188 | if (esr.send_checksum_error) |
189 | if (esr.send_checksum_error) |
189 | printf("Send Checksum Error\n"); |
190 | printf("Send Checksum Error\n"); |
190 | if (esr.receive_checksum_error) |
191 | if (esr.receive_checksum_error) |
191 | printf("Receive Checksum Error\n"); |
192 | printf("Receive Checksum Error\n"); |
192 | if (esr.send_accept_error) |
193 | if (esr.send_accept_error) |
193 | printf("Send Accept Error\n"); |
194 | printf("Send Accept Error\n"); |
194 | if (esr.receive_accept_error) |
195 | if (esr.receive_accept_error) |
195 | printf("Receive Accept Error\n"); |
196 | printf("Receive Accept Error\n"); |
196 | if (esr.send_illegal_vector) |
197 | if (esr.send_illegal_vector) |
197 | printf("Send Illegal Vector\n"); |
198 | printf("Send Illegal Vector\n"); |
198 | if (esr.received_illegal_vector) |
199 | if (esr.received_illegal_vector) |
199 | printf("Received Illegal Vector\n"); |
200 | printf("Received Illegal Vector\n"); |
200 | if (esr.illegal_register_address) |
201 | if (esr.illegal_register_address) |
201 | printf("Illegal Register Address\n"); |
202 | printf("Illegal Register Address\n"); |
202 | 203 | ||
203 | return !esr.err_bitmap; |
204 | return !esr.err_bitmap; |
204 | } |
205 | } |
205 | 206 | ||
206 | /** Send all CPUs excluding CPU IPI vector. |
207 | /** Send all CPUs excluding CPU IPI vector. |
207 | * |
208 | * |
208 | * @param vector Interrupt vector to be sent. |
209 | * @param vector Interrupt vector to be sent. |
209 | * |
210 | * |
210 | * @return 0 on failure, 1 on success. |
211 | * @return 0 on failure, 1 on success. |
211 | */ |
212 | */ |
212 | int l_apic_broadcast_custom_ipi(__u8 vector) |
213 | int l_apic_broadcast_custom_ipi(__u8 vector) |
213 | { |
214 | { |
214 | icr_t icr; |
215 | icr_t icr; |
215 | 216 | ||
216 | icr.lo = l_apic[ICRlo]; |
217 | icr.lo = l_apic[ICRlo]; |
217 | icr.delmod = DELMOD_FIXED; |
218 | icr.delmod = DELMOD_FIXED; |
218 | icr.destmod = DESTMOD_LOGIC; |
219 | icr.destmod = DESTMOD_LOGIC; |
219 | icr.level = LEVEL_ASSERT; |
220 | icr.level = LEVEL_ASSERT; |
220 | icr.shorthand = SHORTHAND_ALL_EXCL; |
221 | icr.shorthand = SHORTHAND_ALL_EXCL; |
221 | icr.trigger_mode = TRIGMOD_LEVEL; |
222 | icr.trigger_mode = TRIGMOD_LEVEL; |
222 | icr.vector = vector; |
223 | icr.vector = vector; |
223 | 224 | ||
224 | l_apic[ICRlo] = icr.lo; |
225 | l_apic[ICRlo] = icr.lo; |
225 | 226 | ||
226 | icr.lo = l_apic[ICRlo]; |
227 | icr.lo = l_apic[ICRlo]; |
227 | if (icr.delivs == DELIVS_PENDING) |
228 | if (icr.delivs == DELIVS_PENDING) |
228 | printf("IPI is pending.\n"); |
229 | printf("IPI is pending.\n"); |
229 | 230 | ||
230 | return apic_poll_errors(); |
231 | return apic_poll_errors(); |
231 | } |
232 | } |
232 | 233 | ||
233 | /** Universal Start-up Algorithm for bringing up the AP processors. |
234 | /** Universal Start-up Algorithm for bringing up the AP processors. |
234 | * |
235 | * |
235 | * @param apicid APIC ID of the processor to be brought up. |
236 | * @param apicid APIC ID of the processor to be brought up. |
236 | * |
237 | * |
237 | * @return 0 on failure, 1 on success. |
238 | * @return 0 on failure, 1 on success. |
238 | */ |
239 | */ |
239 | int l_apic_send_init_ipi(__u8 apicid) |
240 | int l_apic_send_init_ipi(__u8 apicid) |
240 | { |
241 | { |
241 | icr_t icr; |
242 | icr_t icr; |
242 | int i; |
243 | int i; |
243 | 244 | ||
244 | /* |
245 | /* |
245 | * Read the ICR register in and zero all non-reserved fields. |
246 | * Read the ICR register in and zero all non-reserved fields. |
246 | */ |
247 | */ |
247 | icr.lo = l_apic[ICRlo]; |
248 | icr.lo = l_apic[ICRlo]; |
248 | icr.hi = l_apic[ICRhi]; |
249 | icr.hi = l_apic[ICRhi]; |
249 | 250 | ||
250 | icr.delmod = DELMOD_INIT; |
251 | icr.delmod = DELMOD_INIT; |
251 | icr.destmod = DESTMOD_PHYS; |
252 | icr.destmod = DESTMOD_PHYS; |
252 | icr.level = LEVEL_ASSERT; |
253 | icr.level = LEVEL_ASSERT; |
253 | icr.trigger_mode = TRIGMOD_LEVEL; |
254 | icr.trigger_mode = TRIGMOD_LEVEL; |
254 | icr.shorthand = SHORTHAND_NONE; |
255 | icr.shorthand = SHORTHAND_NONE; |
255 | icr.vector = 0; |
256 | icr.vector = 0; |
256 | icr.dest = apicid; |
257 | icr.dest = apicid; |
257 | 258 | ||
258 | l_apic[ICRhi] = icr.hi; |
259 | l_apic[ICRhi] = icr.hi; |
259 | l_apic[ICRlo] = icr.lo; |
260 | l_apic[ICRlo] = icr.lo; |
260 | 261 | ||
261 | /* |
262 | /* |
262 | * According to MP Specification, 20us should be enough to |
263 | * According to MP Specification, 20us should be enough to |
263 | * deliver the IPI. |
264 | * deliver the IPI. |
264 | */ |
265 | */ |
265 | delay(20); |
266 | delay(20); |
266 | 267 | ||
267 | if (!apic_poll_errors()) return 0; |
268 | if (!apic_poll_errors()) return 0; |
268 | 269 | ||
269 | icr.lo = l_apic[ICRlo]; |
270 | icr.lo = l_apic[ICRlo]; |
270 | if (icr.delivs == DELIVS_PENDING) |
271 | if (icr.delivs == DELIVS_PENDING) |
271 | printf("IPI is pending.\n"); |
272 | printf("IPI is pending.\n"); |
272 | 273 | ||
273 | icr.delmod = DELMOD_INIT; |
274 | icr.delmod = DELMOD_INIT; |
274 | icr.destmod = DESTMOD_PHYS; |
275 | icr.destmod = DESTMOD_PHYS; |
275 | icr.level = LEVEL_DEASSERT; |
276 | icr.level = LEVEL_DEASSERT; |
276 | icr.shorthand = SHORTHAND_NONE; |
277 | icr.shorthand = SHORTHAND_NONE; |
277 | icr.trigger_mode = TRIGMOD_LEVEL; |
278 | icr.trigger_mode = TRIGMOD_LEVEL; |
278 | icr.vector = 0; |
279 | icr.vector = 0; |
279 | l_apic[ICRlo] = icr.lo; |
280 | l_apic[ICRlo] = icr.lo; |
280 | 281 | ||
281 | /* |
282 | /* |
282 | * Wait 10ms as MP Specification specifies. |
283 | * Wait 10ms as MP Specification specifies. |
283 | */ |
284 | */ |
284 | delay(10000); |
285 | delay(10000); |
285 | 286 | ||
286 | if (!is_82489DX_apic(l_apic[LAVR])) { |
287 | if (!is_82489DX_apic(l_apic[LAVR])) { |
287 | /* |
288 | /* |
288 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
289 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
289 | */ |
290 | */ |
290 | for (i = 0; i<2; i++) { |
291 | for (i = 0; i<2; i++) { |
291 | icr.lo = l_apic[ICRlo]; |
292 | icr.lo = l_apic[ICRlo]; |
292 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
293 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
293 | icr.delmod = DELMOD_STARTUP; |
294 | icr.delmod = DELMOD_STARTUP; |
294 | icr.destmod = DESTMOD_PHYS; |
295 | icr.destmod = DESTMOD_PHYS; |
295 | icr.level = LEVEL_ASSERT; |
296 | icr.level = LEVEL_ASSERT; |
296 | icr.shorthand = SHORTHAND_NONE; |
297 | icr.shorthand = SHORTHAND_NONE; |
297 | icr.trigger_mode = TRIGMOD_LEVEL; |
298 | icr.trigger_mode = TRIGMOD_LEVEL; |
298 | l_apic[ICRlo] = icr.lo; |
299 | l_apic[ICRlo] = icr.lo; |
299 | delay(200); |
300 | delay(200); |
300 | } |
301 | } |
301 | } |
302 | } |
302 | 303 | ||
303 | return apic_poll_errors(); |
304 | return apic_poll_errors(); |
304 | } |
305 | } |
305 | 306 | ||
306 | /** Initialize Local APIC. */ |
307 | /** Initialize Local APIC. */ |
307 | void l_apic_init(void) |
308 | void l_apic_init(void) |
308 | { |
309 | { |
309 | lvt_error_t error; |
310 | lvt_error_t error; |
310 | lvt_lint_t lint; |
311 | lvt_lint_t lint; |
311 | tpr_t tpr; |
312 | tpr_t tpr; |
312 | svr_t svr; |
313 | svr_t svr; |
313 | icr_t icr; |
314 | icr_t icr; |
314 | tdcr_t tdcr; |
315 | tdcr_t tdcr; |
315 | lvt_tm_t tm; |
316 | lvt_tm_t tm; |
316 | ldr_t ldr; |
317 | ldr_t ldr; |
317 | dfr_t dfr; |
318 | dfr_t dfr; |
318 | __u32 t1, t2; |
319 | __u32 t1, t2; |
319 | 320 | ||
320 | /* Initialize LVT Error register. */ |
321 | /* Initialize LVT Error register. */ |
321 | error.value = l_apic[LVT_Err]; |
322 | error.value = l_apic[LVT_Err]; |
322 | error.masked = true; |
323 | error.masked = true; |
323 | l_apic[LVT_Err] = error.value; |
324 | l_apic[LVT_Err] = error.value; |
324 | 325 | ||
325 | /* Initialize LVT LINT0 register. */ |
326 | /* Initialize LVT LINT0 register. */ |
326 | lint.value = l_apic[LVT_LINT0]; |
327 | lint.value = l_apic[LVT_LINT0]; |
327 | lint.masked = true; |
328 | lint.masked = true; |
328 | l_apic[LVT_LINT0] = lint.value; |
329 | l_apic[LVT_LINT0] = lint.value; |
329 | 330 | ||
330 | /* Initialize LVT LINT1 register. */ |
331 | /* Initialize LVT LINT1 register. */ |
331 | lint.value = l_apic[LVT_LINT1]; |
332 | lint.value = l_apic[LVT_LINT1]; |
332 | lint.masked = true; |
333 | lint.masked = true; |
333 | l_apic[LVT_LINT1] = lint.value; |
334 | l_apic[LVT_LINT1] = lint.value; |
334 | 335 | ||
335 | /* Task Priority Register initialization. */ |
336 | /* Task Priority Register initialization. */ |
336 | tpr.value = l_apic[TPR]; |
337 | tpr.value = l_apic[TPR]; |
337 | tpr.pri_sc = 0; |
338 | tpr.pri_sc = 0; |
338 | tpr.pri = 0; |
339 | tpr.pri = 0; |
339 | l_apic[TPR] = tpr.value; |
340 | l_apic[TPR] = tpr.value; |
340 | 341 | ||
341 | /* Spurious-Interrupt Vector Register initialization. */ |
342 | /* Spurious-Interrupt Vector Register initialization. */ |
342 | svr.value = l_apic[SVR]; |
343 | svr.value = l_apic[SVR]; |
343 | svr.vector = VECTOR_APIC_SPUR; |
344 | svr.vector = VECTOR_APIC_SPUR; |
344 | svr.lapic_enabled = true; |
345 | svr.lapic_enabled = true; |
345 | svr.focus_checking = true; |
346 | svr.focus_checking = true; |
346 | l_apic[SVR] = svr.value; |
347 | l_apic[SVR] = svr.value; |
347 | 348 | ||
348 | if (CPU->arch.family >= 6) |
349 | if (CPU->arch.family >= 6) |
349 | enable_l_apic_in_msr(); |
350 | enable_l_apic_in_msr(); |
350 | 351 | ||
351 | /* Interrupt Command Register initialization. */ |
352 | /* Interrupt Command Register initialization. */ |
352 | icr.lo = l_apic[ICRlo]; |
353 | icr.lo = l_apic[ICRlo]; |
353 | icr.delmod = DELMOD_INIT; |
354 | icr.delmod = DELMOD_INIT; |
354 | icr.destmod = DESTMOD_PHYS; |
355 | icr.destmod = DESTMOD_PHYS; |
355 | icr.level = LEVEL_DEASSERT; |
356 | icr.level = LEVEL_DEASSERT; |
356 | icr.shorthand = SHORTHAND_ALL_INCL; |
357 | icr.shorthand = SHORTHAND_ALL_INCL; |
357 | icr.trigger_mode = TRIGMOD_LEVEL; |
358 | icr.trigger_mode = TRIGMOD_LEVEL; |
358 | l_apic[ICRlo] = icr.lo; |
359 | l_apic[ICRlo] = icr.lo; |
359 | 360 | ||
360 | /* Timer Divide Configuration Register initialization. */ |
361 | /* Timer Divide Configuration Register initialization. */ |
361 | tdcr.value = l_apic[TDCR]; |
362 | tdcr.value = l_apic[TDCR]; |
362 | tdcr.div_value = DIVIDE_1; |
363 | tdcr.div_value = DIVIDE_1; |
363 | l_apic[TDCR] = tdcr.value; |
364 | l_apic[TDCR] = tdcr.value; |
364 | 365 | ||
365 | /* Program local timer. */ |
366 | /* Program local timer. */ |
366 | tm.value = l_apic[LVT_Tm]; |
367 | tm.value = l_apic[LVT_Tm]; |
367 | tm.vector = VECTOR_CLK; |
368 | tm.vector = VECTOR_CLK; |
368 | tm.mode = TIMER_PERIODIC; |
369 | tm.mode = TIMER_PERIODIC; |
369 | tm.masked = false; |
370 | tm.masked = false; |
370 | l_apic[LVT_Tm] = tm.value; |
371 | l_apic[LVT_Tm] = tm.value; |
371 | 372 | ||
372 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
373 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
373 | t1 = l_apic[CCRT]; |
374 | t1 = l_apic[CCRT]; |
374 | l_apic[ICRT] = 0xffffffff; |
375 | l_apic[ICRT] = 0xffffffff; |
375 | 376 | ||
376 | while (l_apic[CCRT] == t1) |
377 | while (l_apic[CCRT] == t1) |
377 | ; |
378 | ; |
378 | 379 | ||
379 | t1 = l_apic[CCRT]; |
380 | t1 = l_apic[CCRT]; |
380 | delay(1000); |
381 | delay(1000); |
381 | t2 = l_apic[CCRT]; |
382 | t2 = l_apic[CCRT]; |
382 | 383 | ||
383 | l_apic[ICRT] = t1-t2; |
384 | l_apic[ICRT] = t1-t2; |
384 | 385 | ||
385 | /* Program Logical Destination Register. */ |
386 | /* Program Logical Destination Register. */ |
386 | ldr.value = l_apic[LDR]; |
387 | ldr.value = l_apic[LDR]; |
387 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
388 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
388 | ldr.id = (1<<CPU->id); |
389 | ldr.id = (1<<CPU->id); |
389 | l_apic[LDR] = ldr.value; |
390 | l_apic[LDR] = ldr.value; |
390 | 391 | ||
391 | /* Program Destination Format Register for Flat mode. */ |
392 | /* Program Destination Format Register for Flat mode. */ |
392 | dfr.value = l_apic[DFR]; |
393 | dfr.value = l_apic[DFR]; |
393 | dfr.model = MODEL_FLAT; |
394 | dfr.model = MODEL_FLAT; |
394 | l_apic[DFR] = dfr.value; |
395 | l_apic[DFR] = dfr.value; |
395 | } |
396 | } |
396 | 397 | ||
397 | /** Local APIC End of Interrupt. */ |
398 | /** Local APIC End of Interrupt. */ |
398 | void l_apic_eoi(void) |
399 | void l_apic_eoi(void) |
399 | { |
400 | { |
400 | l_apic[EOI] = 0; |
401 | l_apic[EOI] = 0; |
401 | } |
402 | } |
402 | 403 | ||
403 | /** Dump content of Local APIC registers. */ |
404 | /** Dump content of Local APIC registers. */ |
404 | void l_apic_debug(void) |
405 | void l_apic_debug(void) |
405 | { |
406 | { |
406 | #ifdef LAPIC_VERBOSE |
407 | #ifdef LAPIC_VERBOSE |
407 | lvt_tm_t tm; |
408 | lvt_tm_t tm; |
408 | lvt_lint_t lint; |
409 | lvt_lint_t lint; |
409 | lvt_error_t error; |
410 | lvt_error_t error; |
410 | 411 | ||
411 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
412 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
412 | 413 | ||
413 | tm.value = l_apic[LVT_Tm]; |
414 | tm.value = l_apic[LVT_Tm]; |
414 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
415 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
415 | lint.value = l_apic[LVT_LINT0]; |
416 | lint.value = l_apic[LVT_LINT0]; |
416 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
417 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
417 | lint.value = l_apic[LVT_LINT1]; |
418 | lint.value = l_apic[LVT_LINT1]; |
418 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
419 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
419 | error.value = l_apic[LVT_Err]; |
420 | error.value = l_apic[LVT_Err]; |
420 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
421 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
421 | #endif |
422 | #endif |
422 | } |
423 | } |
423 | 424 | ||
424 | /** Local APIC Timer Interrupt. |
425 | /** Local APIC Timer Interrupt. |
425 | * |
426 | * |
426 | * @param n Interrupt vector number. |
427 | * @param n Interrupt vector number. |
427 | * @param stack Interrupted stack. |
428 | * @param stack Interrupted stack. |
428 | */ |
429 | */ |
429 | void l_apic_timer_interrupt(int n, void *stack) |
430 | void l_apic_timer_interrupt(int n, void *stack) |
430 | { |
431 | { |
431 | l_apic_eoi(); |
432 | l_apic_eoi(); |
432 | clock(); |
433 | clock(); |
433 | } |
434 | } |
434 | 435 | ||
435 | /** Get Local APIC ID. |
436 | /** Get Local APIC ID. |
436 | * |
437 | * |
437 | * @return Local APIC ID. |
438 | * @return Local APIC ID. |
438 | */ |
439 | */ |
439 | __u8 l_apic_id(void) |
440 | __u8 l_apic_id(void) |
440 | { |
441 | { |
441 | l_apic_id_t idreg; |
442 | l_apic_id_t idreg; |
442 | 443 | ||
443 | idreg.value = l_apic[L_APIC_ID]; |
444 | idreg.value = l_apic[L_APIC_ID]; |
444 | return idreg.apic_id; |
445 | return idreg.apic_id; |
445 | } |
446 | } |
446 | 447 | ||
447 | /** Read from IO APIC register. |
448 | /** Read from IO APIC register. |
448 | * |
449 | * |
449 | * @param address IO APIC register address. |
450 | * @param address IO APIC register address. |
450 | * |
451 | * |
451 | * @return Content of the addressed IO APIC register. |
452 | * @return Content of the addressed IO APIC register. |
452 | */ |
453 | */ |
453 | __u32 io_apic_read(__u8 address) |
454 | __u32 io_apic_read(__u8 address) |
454 | { |
455 | { |
455 | io_regsel_t regsel; |
456 | io_regsel_t regsel; |
456 | 457 | ||
457 | regsel.value = io_apic[IOREGSEL]; |
458 | regsel.value = io_apic[IOREGSEL]; |
458 | regsel.reg_addr = address; |
459 | regsel.reg_addr = address; |
459 | io_apic[IOREGSEL] = regsel.value; |
460 | io_apic[IOREGSEL] = regsel.value; |
460 | return io_apic[IOWIN]; |
461 | return io_apic[IOWIN]; |
461 | } |
462 | } |
462 | 463 | ||
463 | /** Write to IO APIC register. |
464 | /** Write to IO APIC register. |
464 | * |
465 | * |
465 | * @param address IO APIC register address. |
466 | * @param address IO APIC register address. |
466 | * @param Content to be written to the addressed IO APIC register. |
467 | * @param Content to be written to the addressed IO APIC register. |
467 | */ |
468 | */ |
468 | void io_apic_write(__u8 address, __u32 x) |
469 | void io_apic_write(__u8 address, __u32 x) |
469 | { |
470 | { |
470 | io_regsel_t regsel; |
471 | io_regsel_t regsel; |
471 | 472 | ||
472 | regsel.value = io_apic[IOREGSEL]; |
473 | regsel.value = io_apic[IOREGSEL]; |
473 | regsel.reg_addr = address; |
474 | regsel.reg_addr = address; |
474 | io_apic[IOREGSEL] = regsel.value; |
475 | io_apic[IOREGSEL] = regsel.value; |
475 | io_apic[IOWIN] = x; |
476 | io_apic[IOWIN] = x; |
476 | } |
477 | } |
477 | 478 | ||
478 | /** Change some attributes of one item in I/O Redirection Table. |
479 | /** Change some attributes of one item in I/O Redirection Table. |
479 | * |
480 | * |
480 | * @param pin IO APIC pin number. |
481 | * @param pin IO APIC pin number. |
481 | * @param dest Interrupt destination address. |
482 | * @param dest Interrupt destination address. |
482 | * @param v Interrupt vector to trigger. |
483 | * @param v Interrupt vector to trigger. |
483 | * @param flags Flags. |
484 | * @param flags Flags. |
484 | */ |
485 | */ |
485 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
486 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
486 | { |
487 | { |
487 | io_redirection_reg_t reg; |
488 | io_redirection_reg_t reg; |
488 | int dlvr = DELMOD_FIXED; |
489 | int dlvr = DELMOD_FIXED; |
489 | 490 | ||
490 | if (flags & LOPRI) |
491 | if (flags & LOPRI) |
491 | dlvr = DELMOD_LOWPRI; |
492 | dlvr = DELMOD_LOWPRI; |
492 | 493 | ||
493 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
494 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
494 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
495 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
495 | 496 | ||
496 | reg.dest = dest; |
497 | reg.dest = dest; |
497 | reg.destmod = DESTMOD_LOGIC; |
498 | reg.destmod = DESTMOD_LOGIC; |
498 | reg.trigger_mode = TRIGMOD_EDGE; |
499 | reg.trigger_mode = TRIGMOD_EDGE; |
499 | reg.intpol = POLARITY_HIGH; |
500 | reg.intpol = POLARITY_HIGH; |
500 | reg.delmod = dlvr; |
501 | reg.delmod = dlvr; |
501 | reg.intvec = v; |
502 | reg.intvec = v; |
502 | 503 | ||
503 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
504 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
504 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
505 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
505 | } |
506 | } |
506 | 507 | ||
507 | /** Mask IRQs in IO APIC. |
508 | /** Mask IRQs in IO APIC. |
508 | * |
509 | * |
509 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
510 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
510 | */ |
511 | */ |
511 | void io_apic_disable_irqs(__u16 irqmask) |
512 | void io_apic_disable_irqs(__u16 irqmask) |
512 | { |
513 | { |
513 | io_redirection_reg_t reg; |
514 | io_redirection_reg_t reg; |
514 | int i, pin; |
515 | int i, pin; |
515 | 516 | ||
516 | for (i=0;i<16;i++) { |
517 | for (i=0;i<16;i++) { |
517 | if (irqmask & (1<<i)) { |
518 | if (irqmask & (1<<i)) { |
518 | /* |
519 | /* |
519 | * Mask the signal input in IO APIC if there is a |
520 | * Mask the signal input in IO APIC if there is a |
520 | * mapping for the respective IRQ number. |
521 | * mapping for the respective IRQ number. |
521 | */ |
522 | */ |
522 | pin = smp_irq_to_pin(i); |
523 | pin = smp_irq_to_pin(i); |
523 | if (pin != -1) { |
524 | if (pin != -1) { |
524 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
525 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
525 | reg.masked = true; |
526 | reg.masked = true; |
526 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
527 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
527 | } |
528 | } |
528 | 529 | ||
529 | } |
530 | } |
530 | } |
531 | } |
531 | } |
532 | } |
532 | 533 | ||
533 | /** Unmask IRQs in IO APIC. |
534 | /** Unmask IRQs in IO APIC. |
534 | * |
535 | * |
535 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
536 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
536 | */ |
537 | */ |
537 | void io_apic_enable_irqs(__u16 irqmask) |
538 | void io_apic_enable_irqs(__u16 irqmask) |
538 | { |
539 | { |
539 | int i, pin; |
540 | int i, pin; |
540 | io_redirection_reg_t reg; |
541 | io_redirection_reg_t reg; |
541 | 542 | ||
542 | for (i=0;i<16;i++) { |
543 | for (i=0;i<16;i++) { |
543 | if (irqmask & (1<<i)) { |
544 | if (irqmask & (1<<i)) { |
544 | /* |
545 | /* |
545 | * Unmask the signal input in IO APIC if there is a |
546 | * Unmask the signal input in IO APIC if there is a |
546 | * mapping for the respective IRQ number. |
547 | * mapping for the respective IRQ number. |
547 | */ |
548 | */ |
548 | pin = smp_irq_to_pin(i); |
549 | pin = smp_irq_to_pin(i); |
549 | if (pin != -1) { |
550 | if (pin != -1) { |
550 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
551 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
551 | reg.masked = false; |
552 | reg.masked = false; |
552 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
553 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
553 | } |
554 | } |
554 | 555 | ||
555 | } |
556 | } |
556 | } |
557 | } |
557 | } |
558 | } |
558 | 559 | ||
559 | #endif /* CONFIG_SMP */ |
560 | #endif /* CONFIG_SMP */ |
560 | 561 |