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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <mm/page.h> |
33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
34 | #include <time/delay.h> |
35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
36 | #include <print.h> |
36 | #include <print.h> |
37 | #include <arch/asm.h> |
37 | #include <arch/asm.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | 39 | ||
40 | #ifdef __SMP__ |
40 | #ifdef __SMP__ |
41 | 41 | ||
42 | /* |
42 | /* |
43 | * This is functional, far-from-general-enough interface to the APIC. |
43 | * This is functional, far-from-general-enough interface to the APIC. |
44 | * Advanced Programmable Interrupt Controller for MP systems. |
44 | * Advanced Programmable Interrupt Controller for MP systems. |
45 | * Tested on: |
45 | * Tested on: |
46 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
46 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.14 2-4 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.14 2-4 CPUs |
48 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
48 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
- | 49 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
|
- | 50 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
|
49 | */ |
51 | */ |
50 | 52 | ||
51 | /* |
53 | /* |
52 | * These variables either stay configured as initilalized, or are changed by |
54 | * These variables either stay configured as initilalized, or are changed by |
53 | * the MP configuration code. |
55 | * the MP configuration code. |
54 | * |
56 | * |
55 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
57 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
56 | * optimize the code too much and accesses to l_apic and io_apic, that must |
58 | * optimize the code too much and accesses to l_apic and io_apic, that must |
57 | * always be 32-bit, would use byte oriented instructions. |
59 | * always be 32-bit, would use byte oriented instructions. |
58 | */ |
60 | */ |
59 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
61 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
60 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
62 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
61 | 63 | ||
62 | __u32 apic_id_mask = 0; |
64 | __u32 apic_id_mask = 0; |
63 | 65 | ||
64 | int apic_poll_errors(void); |
66 | int apic_poll_errors(void); |
65 | 67 | ||
66 | void apic_init(void) |
68 | void apic_init(void) |
67 | { |
69 | { |
68 | __u32 tmp, id, i; |
70 | __u32 tmp, id, i; |
69 | 71 | ||
70 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
72 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
71 | 73 | ||
72 | enable_irqs_function = io_apic_enable_irqs; |
74 | enable_irqs_function = io_apic_enable_irqs; |
73 | disable_irqs_function = io_apic_disable_irqs; |
75 | disable_irqs_function = io_apic_disable_irqs; |
74 | eoi_function = l_apic_eoi; |
76 | eoi_function = l_apic_eoi; |
75 | 77 | ||
76 | /* |
78 | /* |
77 | * Configure interrupt routing. |
79 | * Configure interrupt routing. |
78 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
80 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
79 | * Other interrupts will be forwarded to the lowest priority CPU. |
81 | * Other interrupts will be forwarded to the lowest priority CPU. |
80 | */ |
82 | */ |
81 | io_apic_disable_irqs(0xffff); |
83 | io_apic_disable_irqs(0xffff); |
82 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
84 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
83 | for (i=1; i<16; i++) { |
85 | for (i=1; i<16; i++) { |
84 | int pin; |
86 | int pin; |
85 | 87 | ||
86 | if ((pin = mps_irq_to_pin(i)) != -1) |
88 | if ((pin = mps_irq_to_pin(i)) != -1) |
87 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
89 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
88 | } |
90 | } |
89 | 91 | ||
90 | 92 | ||
91 | /* |
93 | /* |
92 | * Ensure that io_apic has unique ID. |
94 | * Ensure that io_apic has unique ID. |
93 | */ |
95 | */ |
94 | tmp = io_apic_read(IOAPICID); |
96 | tmp = io_apic_read(IOAPICID); |
95 | id = (tmp >> 24) & 0xf; |
97 | id = (tmp >> 24) & 0xf; |
96 | if ((1<<id) & apic_id_mask) { |
98 | if ((1<<id) & apic_id_mask) { |
97 | int i; |
99 | int i; |
98 | 100 | ||
99 | for (i=0; i<15; i++) { |
101 | for (i=0; i<15; i++) { |
100 | if (!((1<<i) & apic_id_mask)) { |
102 | if (!((1<<i) & apic_id_mask)) { |
101 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
103 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
102 | break; |
104 | break; |
103 | } |
105 | } |
104 | } |
106 | } |
105 | } |
107 | } |
106 | 108 | ||
107 | /* |
109 | /* |
108 | * Configure the BSP's lapic. |
110 | * Configure the BSP's lapic. |
109 | */ |
111 | */ |
110 | l_apic_init(); |
112 | l_apic_init(); |
111 | l_apic_debug(); |
113 | l_apic_debug(); |
112 | } |
114 | } |
113 | 115 | ||
114 | void apic_spurious(__u8 n, __native stack[]) |
116 | void apic_spurious(__u8 n, __native stack[]) |
115 | { |
117 | { |
116 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
118 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
117 | } |
119 | } |
118 | 120 | ||
119 | int apic_poll_errors(void) |
121 | int apic_poll_errors(void) |
120 | { |
122 | { |
121 | __u32 esr; |
123 | __u32 esr; |
122 | 124 | ||
123 | esr = l_apic[ESR] & ~ESRClear; |
125 | esr = l_apic[ESR] & ~ESRClear; |
124 | 126 | ||
125 | if ((esr>>0) & 1) |
127 | if ((esr>>0) & 1) |
126 | printf("Send CS Error\n"); |
128 | printf("Send CS Error\n"); |
127 | if ((esr>>1) & 1) |
129 | if ((esr>>1) & 1) |
128 | printf("Receive CS Error\n"); |
130 | printf("Receive CS Error\n"); |
129 | if ((esr>>2) & 1) |
131 | if ((esr>>2) & 1) |
130 | printf("Send Accept Error\n"); |
132 | printf("Send Accept Error\n"); |
131 | if ((esr>>3) & 1) |
133 | if ((esr>>3) & 1) |
132 | printf("Receive Accept Error\n"); |
134 | printf("Receive Accept Error\n"); |
133 | if ((esr>>5) & 1) |
135 | if ((esr>>5) & 1) |
134 | printf("Send Illegal Vector\n"); |
136 | printf("Send Illegal Vector\n"); |
135 | if ((esr>>6) & 1) |
137 | if ((esr>>6) & 1) |
136 | printf("Received Illegal Vector\n"); |
138 | printf("Received Illegal Vector\n"); |
137 | if ((esr>>7) & 1) |
139 | if ((esr>>7) & 1) |
138 | printf("Illegal Register Address\n"); |
140 | printf("Illegal Register Address\n"); |
139 | 141 | ||
140 | return !esr; |
142 | return !esr; |
141 | } |
143 | } |
142 | 144 | ||
143 | /* |
145 | /* |
144 | * Send all CPUs excluding CPU IPI vector. |
146 | * Send all CPUs excluding CPU IPI vector. |
145 | */ |
147 | */ |
146 | int l_apic_broadcast_custom_ipi(__u8 vector) |
148 | int l_apic_broadcast_custom_ipi(__u8 vector) |
147 | { |
149 | { |
148 | __u32 lo; |
150 | __u32 lo; |
149 | 151 | ||
150 | /* |
152 | /* |
151 | * Read the ICR register in and zero all non-reserved fields. |
153 | * Read the ICR register in and zero all non-reserved fields. |
152 | */ |
154 | */ |
153 | lo = l_apic[ICRlo] & ICRloClear; |
155 | lo = l_apic[ICRlo] & ICRloClear; |
154 | 156 | ||
155 | lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector; |
157 | lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector; |
156 | 158 | ||
157 | l_apic[ICRlo] = lo; |
159 | l_apic[ICRlo] = lo; |
158 | 160 | ||
159 | lo = l_apic[ICRlo] & ICRloClear; |
161 | lo = l_apic[ICRlo] & ICRloClear; |
160 | if (lo & SEND_PENDING) |
162 | if (lo & SEND_PENDING) |
161 | printf("IPI is pending.\n"); |
163 | printf("IPI is pending.\n"); |
162 | 164 | ||
163 | return apic_poll_errors(); |
165 | return apic_poll_errors(); |
164 | } |
166 | } |
165 | 167 | ||
166 | /* |
168 | /* |
167 | * Universal Start-up Algorithm for bringing up the AP processors. |
169 | * Universal Start-up Algorithm for bringing up the AP processors. |
168 | */ |
170 | */ |
169 | int l_apic_send_init_ipi(__u8 apicid) |
171 | int l_apic_send_init_ipi(__u8 apicid) |
170 | { |
172 | { |
171 | __u32 lo, hi; |
173 | __u32 lo, hi; |
172 | int i; |
174 | int i; |
173 | 175 | ||
174 | /* |
176 | /* |
175 | * Read the ICR register in and zero all non-reserved fields. |
177 | * Read the ICR register in and zero all non-reserved fields. |
176 | */ |
178 | */ |
177 | lo = l_apic[ICRlo] & ICRloClear; |
179 | lo = l_apic[ICRlo] & ICRloClear; |
178 | hi = l_apic[ICRhi] & ICRhiClear; |
180 | hi = l_apic[ICRhi] & ICRhiClear; |
179 | 181 | ||
180 | lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
182 | lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
181 | hi |= apicid << 24; |
183 | hi |= apicid << 24; |
182 | 184 | ||
183 | l_apic[ICRhi] = hi; |
185 | l_apic[ICRhi] = hi; |
184 | l_apic[ICRlo] = lo; |
186 | l_apic[ICRlo] = lo; |
185 | 187 | ||
186 | /* |
188 | /* |
187 | * According to MP Specification, 20us should be enough to |
189 | * According to MP Specification, 20us should be enough to |
188 | * deliver the IPI. |
190 | * deliver the IPI. |
189 | */ |
191 | */ |
190 | delay(20); |
192 | delay(20); |
191 | 193 | ||
192 | if (!apic_poll_errors()) return 0; |
194 | if (!apic_poll_errors()) return 0; |
193 | 195 | ||
194 | lo = l_apic[ICRlo] & ICRloClear; |
196 | lo = l_apic[ICRlo] & ICRloClear; |
195 | if (lo & SEND_PENDING) |
197 | if (lo & SEND_PENDING) |
196 | printf("IPI is pending.\n"); |
198 | printf("IPI is pending.\n"); |
197 | 199 | ||
198 | l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
200 | l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
199 | 201 | ||
200 | /* |
202 | /* |
201 | * Wait 10ms as MP Specification specifies. |
203 | * Wait 10ms as MP Specification specifies. |
202 | */ |
204 | */ |
203 | delay(10000); |
205 | delay(10000); |
204 | 206 | ||
205 | if (!is_82489DX_apic(l_apic[LAVR])) { |
207 | if (!is_82489DX_apic(l_apic[LAVR])) { |
206 | /* |
208 | /* |
207 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
209 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
208 | */ |
210 | */ |
209 | for (i = 0; i<2; i++) { |
211 | for (i = 0; i<2; i++) { |
210 | lo = l_apic[ICRlo] & ICRloClear; |
212 | lo = l_apic[ICRlo] & ICRloClear; |
211 | lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
213 | lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
212 | l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
214 | l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
213 | delay(200); |
215 | delay(200); |
214 | } |
216 | } |
215 | } |
217 | } |
216 | 218 | ||
217 | 219 | ||
218 | return apic_poll_errors(); |
220 | return apic_poll_errors(); |
219 | } |
221 | } |
220 | 222 | ||
221 | void l_apic_init(void) |
223 | void l_apic_init(void) |
222 | { |
224 | { |
223 | __u32 tmp, t1, t2; |
225 | __u32 tmp, t1, t2; |
224 | 226 | ||
225 | l_apic[LVT_Err] |= (1<<16); |
227 | l_apic[LVT_Err] |= (1<<16); |
226 | l_apic[LVT_LINT0] |= (1<<16); |
228 | l_apic[LVT_LINT0] |= (1<<16); |
227 | l_apic[LVT_LINT1] |= (1<<16); |
229 | l_apic[LVT_LINT1] |= (1<<16); |
228 | 230 | ||
229 | tmp = l_apic[SVR] & SVRClear; |
231 | tmp = l_apic[SVR] & SVRClear; |
230 | l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR); |
232 | l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR); |
231 | 233 | ||
232 | l_apic[TPR] &= TPRClear; |
234 | l_apic[TPR] &= TPRClear; |
233 | 235 | ||
234 | if (CPU->arch.family >= 6) |
236 | if (CPU->arch.family >= 6) |
235 | enable_l_apic_in_msr(); |
237 | enable_l_apic_in_msr(); |
236 | 238 | ||
237 | tmp = l_apic[ICRlo] & ICRloClear; |
239 | tmp = l_apic[ICRlo] & ICRloClear; |
238 | l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL; |
240 | l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL; |
239 | 241 | ||
240 | /* |
242 | /* |
241 | * Program the timer for periodic mode and respective vector. |
243 | * Program the timer for periodic mode and respective vector. |
242 | */ |
244 | */ |
243 | 245 | ||
244 | l_apic[TDCR] &= TDCRClear; |
246 | l_apic[TDCR] &= TDCRClear; |
245 | l_apic[TDCR] |= 0xb; |
247 | l_apic[TDCR] |= 0xb; |
246 | tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK); |
248 | tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK); |
247 | l_apic[LVT_Tm] = tmp & ~(1<<16); |
249 | l_apic[LVT_Tm] = tmp & ~(1<<16); |
248 | 250 | ||
249 | t1 = l_apic[CCRT]; |
251 | t1 = l_apic[CCRT]; |
250 | l_apic[ICRT] = 0xffffffff; |
252 | l_apic[ICRT] = 0xffffffff; |
251 | 253 | ||
252 | while (l_apic[CCRT] == t1) |
254 | while (l_apic[CCRT] == t1) |
253 | ; |
255 | ; |
254 | 256 | ||
255 | t1 = l_apic[CCRT]; |
257 | t1 = l_apic[CCRT]; |
256 | delay(1000); |
258 | delay(1000); |
257 | t2 = l_apic[CCRT]; |
259 | t2 = l_apic[CCRT]; |
258 | 260 | ||
259 | l_apic[ICRT] = t1-t2; |
261 | l_apic[ICRT] = t1-t2; |
260 | 262 | ||
261 | } |
263 | } |
262 | 264 | ||
263 | void l_apic_eoi(void) |
265 | void l_apic_eoi(void) |
264 | { |
266 | { |
265 | l_apic[EOI] = 0; |
267 | l_apic[EOI] = 0; |
266 | } |
268 | } |
267 | 269 | ||
268 | void l_apic_debug(void) |
270 | void l_apic_debug(void) |
269 | { |
271 | { |
270 | #ifdef LAPIC_VERBOSE |
272 | #ifdef LAPIC_VERBOSE |
271 | int i, lint; |
273 | int i, lint; |
272 | 274 | ||
273 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
275 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
274 | 276 | ||
275 | printf("LVT_Tm: "); |
277 | printf("LVT_Tm: "); |
276 | if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(','); |
278 | if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(','); |
277 | if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
279 | if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
278 | if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
280 | if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
279 | printf("%B\n", l_apic[LVT_Tm] & 0xff); |
281 | printf("%B\n", l_apic[LVT_Tm] & 0xff); |
280 | 282 | ||
281 | for (i=0; i<2; i++) { |
283 | for (i=0; i<2; i++) { |
282 | lint = i ? LVT_LINT1 : LVT_LINT0; |
284 | lint = i ? LVT_LINT1 : LVT_LINT0; |
283 | printf("LVT_LINT%d: ", i); |
285 | printf("LVT_LINT%d: ", i); |
284 | if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
286 | if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
285 | if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(','); |
287 | if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(','); |
286 | printf("%d", l_apic[lint] & (1<<14)); putchar(','); |
288 | printf("%d", l_apic[lint] & (1<<14)); putchar(','); |
287 | printf("%d", l_apic[lint] & (1<<13)); putchar(','); |
289 | printf("%d", l_apic[lint] & (1<<13)); putchar(','); |
288 | if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
290 | if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
289 | 291 | ||
290 | switch ((l_apic[lint]>>8)&7) { |
292 | switch ((l_apic[lint]>>8)&7) { |
291 | case 0: printf("fixed"); break; |
293 | case 0: printf("fixed"); break; |
292 | case 4: printf("NMI"); break; |
294 | case 4: printf("NMI"); break; |
293 | case 7: printf("ExtINT"); break; |
295 | case 7: printf("ExtINT"); break; |
294 | } |
296 | } |
295 | putchar(','); |
297 | putchar(','); |
296 | printf("%B\n", l_apic[lint] & 0xff); |
298 | printf("%B\n", l_apic[lint] & 0xff); |
297 | } |
299 | } |
298 | 300 | ||
299 | printf("LVT_Err: "); |
301 | printf("LVT_Err: "); |
300 | if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
302 | if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
301 | if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
303 | if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
302 | printf("%B\n", l_apic[LVT_Err] & 0xff); |
304 | printf("%B\n", l_apic[LVT_Err] & 0xff); |
303 | 305 | ||
304 | /* |
306 | /* |
305 | * This register is supported only on P6 and higher. |
307 | * This register is supported only on P6 and higher. |
306 | */ |
308 | */ |
307 | if (CPU->arch.family > 5) { |
309 | if (CPU->arch.family > 5) { |
308 | printf("LVT_PCINT: "); |
310 | printf("LVT_PCINT: "); |
309 | if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
311 | if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
310 | if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
312 | if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
311 | switch ((l_apic[LVT_PCINT] >> 8)&7) { |
313 | switch ((l_apic[LVT_PCINT] >> 8)&7) { |
312 | case 0: printf("fixed"); break; |
314 | case 0: printf("fixed"); break; |
313 | case 4: printf("NMI"); break; |
315 | case 4: printf("NMI"); break; |
314 | case 7: printf("ExtINT"); break; |
316 | case 7: printf("ExtINT"); break; |
315 | } |
317 | } |
316 | putchar(','); |
318 | putchar(','); |
317 | printf("%B\n", l_apic[LVT_PCINT] & 0xff); |
319 | printf("%B\n", l_apic[LVT_PCINT] & 0xff); |
318 | } |
320 | } |
319 | #endif |
321 | #endif |
320 | } |
322 | } |
321 | 323 | ||
322 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
324 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
323 | { |
325 | { |
324 | l_apic_eoi(); |
326 | l_apic_eoi(); |
325 | clock(); |
327 | clock(); |
326 | } |
328 | } |
327 | 329 | ||
328 | __u8 l_apic_id(void) |
330 | __u8 l_apic_id(void) |
329 | { |
331 | { |
330 | return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; |
332 | return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; |
331 | } |
333 | } |
332 | 334 | ||
333 | __u32 io_apic_read(__u8 address) |
335 | __u32 io_apic_read(__u8 address) |
334 | { |
336 | { |
335 | __u32 tmp; |
337 | __u32 tmp; |
336 | 338 | ||
337 | tmp = io_apic[IOREGSEL] & ~0xf; |
339 | tmp = io_apic[IOREGSEL] & ~0xf; |
338 | io_apic[IOREGSEL] = tmp | address; |
340 | io_apic[IOREGSEL] = tmp | address; |
339 | return io_apic[IOWIN]; |
341 | return io_apic[IOWIN]; |
340 | } |
342 | } |
341 | 343 | ||
342 | void io_apic_write(__u8 address, __u32 x) |
344 | void io_apic_write(__u8 address, __u32 x) |
343 | { |
345 | { |
344 | __u32 tmp; |
346 | __u32 tmp; |
345 | 347 | ||
346 | tmp = io_apic[IOREGSEL] & ~0xf; |
348 | tmp = io_apic[IOREGSEL] & ~0xf; |
347 | io_apic[IOREGSEL] = tmp | address; |
349 | io_apic[IOREGSEL] = tmp | address; |
348 | io_apic[IOWIN] = x; |
350 | io_apic[IOWIN] = x; |
349 | } |
351 | } |
350 | 352 | ||
351 | void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) |
353 | void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) |
352 | { |
354 | { |
353 | __u32 reglo, reghi; |
355 | __u32 reglo, reghi; |
354 | int dlvr = 0; |
356 | int dlvr = 0; |
355 | 357 | ||
356 | if (flags & LOPRI) |
358 | if (flags & LOPRI) |
357 | dlvr = 1; |
359 | dlvr = 1; |
358 | 360 | ||
359 | reglo = io_apic_read(IOREDTBL + signal*2); |
361 | reglo = io_apic_read(IOREDTBL + signal*2); |
360 | reghi = io_apic_read(IOREDTBL + signal*2 + 1); |
362 | reghi = io_apic_read(IOREDTBL + signal*2 + 1); |
361 | 363 | ||
362 | reghi &= ~0x0f000000; |
364 | reghi &= ~0x0f000000; |
363 | reghi |= (dest<<24); |
365 | reghi |= (dest<<24); |
364 | 366 | ||
365 | reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */ |
367 | reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */ |
366 | reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v; |
368 | reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v; |
367 | 369 | ||
368 | io_apic_write(IOREDTBL + signal*2, reglo); |
370 | io_apic_write(IOREDTBL + signal*2, reglo); |
369 | io_apic_write(IOREDTBL + signal*2 + 1, reghi); |
371 | io_apic_write(IOREDTBL + signal*2 + 1, reghi); |
370 | } |
372 | } |
371 | 373 | ||
372 | void io_apic_disable_irqs(__u16 irqmask) |
374 | void io_apic_disable_irqs(__u16 irqmask) |
373 | { |
375 | { |
374 | int i,pin; |
376 | int i,pin; |
375 | __u32 reglo; |
377 | __u32 reglo; |
376 | 378 | ||
377 | for (i=0;i<16;i++) { |
379 | for (i=0;i<16;i++) { |
378 | if ((irqmask>>i) & 1) { |
380 | if ((irqmask>>i) & 1) { |
379 | /* |
381 | /* |
380 | * Mask the signal input in IO APIC if there is a |
382 | * Mask the signal input in IO APIC if there is a |
381 | * mapping for the respective IRQ number. |
383 | * mapping for the respective IRQ number. |
382 | */ |
384 | */ |
383 | pin = mps_irq_to_pin(i); |
385 | pin = mps_irq_to_pin(i); |
384 | if (pin != -1) { |
386 | if (pin != -1) { |
385 | reglo = io_apic_read(IOREDTBL + pin*2); |
387 | reglo = io_apic_read(IOREDTBL + pin*2); |
386 | reglo |= (1<<16); |
388 | reglo |= (1<<16); |
387 | io_apic_write(IOREDTBL + pin*2,reglo); |
389 | io_apic_write(IOREDTBL + pin*2,reglo); |
388 | } |
390 | } |
389 | 391 | ||
390 | } |
392 | } |
391 | } |
393 | } |
392 | } |
394 | } |
393 | 395 | ||
394 | void io_apic_enable_irqs(__u16 irqmask) |
396 | void io_apic_enable_irqs(__u16 irqmask) |
395 | { |
397 | { |
396 | int i,pin; |
398 | int i,pin; |
397 | __u32 reglo; |
399 | __u32 reglo; |
398 | 400 | ||
399 | for (i=0;i<16;i++) { |
401 | for (i=0;i<16;i++) { |
400 | if ((irqmask>>i) & 1) { |
402 | if ((irqmask>>i) & 1) { |
401 | /* |
403 | /* |
402 | * Unmask the signal input in IO APIC if there is a |
404 | * Unmask the signal input in IO APIC if there is a |
403 | * mapping for the respective IRQ number. |
405 | * mapping for the respective IRQ number. |
404 | */ |
406 | */ |
405 | pin = mps_irq_to_pin(i); |
407 | pin = mps_irq_to_pin(i); |
406 | if (pin != -1) { |
408 | if (pin != -1) { |
407 | reglo = io_apic_read(IOREDTBL + pin*2); |
409 | reglo = io_apic_read(IOREDTBL + pin*2); |
408 | reglo &= ~(1<<16); |
410 | reglo &= ~(1<<16); |
409 | io_apic_write(IOREDTBL + pin*2,reglo); |
411 | io_apic_write(IOREDTBL + pin*2,reglo); |
410 | } |
412 | } |
411 | 413 | ||
412 | } |
414 | } |
413 | } |
415 | } |
414 | 416 | ||
415 | } |
417 | } |
416 | 418 | ||
417 | #endif /* __SMP__ */ |
419 | #endif /* __SMP__ */ |
418 | 420 |