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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <mm/page.h> |
33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
34 | #include <time/delay.h> |
35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
36 | #include <print.h> |
36 | #include <print.h> |
37 | #include <arch/asm.h> |
37 | #include <arch/asm.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | 39 | ||
40 | #ifdef CONFIG_SMP |
40 | #ifdef CONFIG_SMP |
41 | 41 | ||
42 | /* |
42 | /* |
43 | * Advanced Programmable Interrupt Controller for SMP systems. |
43 | * Advanced Programmable Interrupt Controller for SMP systems. |
44 | * Tested on: |
44 | * Tested on: |
45 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
45 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
46 | * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs |
46 | * Simics 2.0.28 - Simics 2.2.19 2-8 CPUs |
47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
48 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
48 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
49 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
49 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
50 | */ |
50 | */ |
51 | 51 | ||
52 | /* |
52 | /* |
53 | * These variables either stay configured as initilalized, or are changed by |
53 | * These variables either stay configured as initilalized, or are changed by |
54 | * the MP configuration code. |
54 | * the MP configuration code. |
55 | * |
55 | * |
56 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
56 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
57 | * optimize the code too much and accesses to l_apic and io_apic, that must |
57 | * optimize the code too much and accesses to l_apic and io_apic, that must |
58 | * always be 32-bit, would use byte oriented instructions. |
58 | * always be 32-bit, would use byte oriented instructions. |
59 | */ |
59 | */ |
60 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
60 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
61 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
61 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
62 | 62 | ||
63 | __u32 apic_id_mask = 0; |
63 | __u32 apic_id_mask = 0; |
64 | 64 | ||
65 | int apic_poll_errors(void); |
65 | static int apic_poll_errors(void); |
- | 66 | ||
- | 67 | static char *delmod_str[] = { |
|
- | 68 | "Fixed", |
|
- | 69 | "Lowest Priority", |
|
- | 70 | "SMI", |
|
- | 71 | "Reserved", |
|
- | 72 | "NMI", |
|
- | 73 | "INIT", |
|
- | 74 | "STARTUP", |
|
- | 75 | "ExtInt" |
|
- | 76 | }; |
|
- | 77 | ||
- | 78 | static char *destmod_str[] = { |
|
- | 79 | "Physical", |
|
- | 80 | "Logical" |
|
- | 81 | }; |
|
- | 82 | ||
- | 83 | static char *trigmod_str[] = { |
|
- | 84 | "Edge", |
|
- | 85 | "Level" |
|
- | 86 | }; |
|
- | 87 | ||
- | 88 | static char *mask_str[] = { |
|
- | 89 | "Unmasked", |
|
- | 90 | "Masked" |
|
- | 91 | }; |
|
- | 92 | ||
- | 93 | static char *delivs_str[] = { |
|
- | 94 | "Idle", |
|
- | 95 | "Send Pending" |
|
- | 96 | }; |
|
- | 97 | ||
- | 98 | static char *tm_mode_str[] = { |
|
- | 99 | "One-shot", |
|
- | 100 | "Periodic" |
|
- | 101 | }; |
|
- | 102 | ||
- | 103 | static char *intpol_str[] = { |
|
- | 104 | "Polarity High", |
|
- | 105 | "Polarity Low" |
|
- | 106 | }; |
|
66 | 107 | ||
67 | /** Initialize APIC on BSP. */ |
108 | /** Initialize APIC on BSP. */ |
68 | void apic_init(void) |
109 | void apic_init(void) |
69 | { |
110 | { |
70 | __u32 tmp, id, i; |
111 | __u32 tmp, id, i; |
71 | 112 | ||
72 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
113 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
73 | 114 | ||
74 | enable_irqs_function = io_apic_enable_irqs; |
115 | enable_irqs_function = io_apic_enable_irqs; |
75 | disable_irqs_function = io_apic_disable_irqs; |
116 | disable_irqs_function = io_apic_disable_irqs; |
76 | eoi_function = l_apic_eoi; |
117 | eoi_function = l_apic_eoi; |
77 | 118 | ||
78 | /* |
119 | /* |
79 | * Configure interrupt routing. |
120 | * Configure interrupt routing. |
80 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
121 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
81 | * Other interrupts will be forwarded to the lowest priority CPU. |
122 | * Other interrupts will be forwarded to the lowest priority CPU. |
82 | */ |
123 | */ |
83 | io_apic_disable_irqs(0xffff); |
124 | io_apic_disable_irqs(0xffff); |
84 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
125 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
85 | for (i=0; i<16; i++) { |
126 | for (i=0; i<16; i++) { |
86 | int pin; |
127 | int pin; |
87 | 128 | ||
88 | if ((pin = smp_irq_to_pin(i)) != -1) { |
129 | if ((pin = smp_irq_to_pin(i)) != -1) { |
89 | io_apic_change_ioredtbl(pin, 0xff, IVT_IRQBASE+i, LOPRI); |
130 | io_apic_change_ioredtbl(pin, 0xff, IVT_IRQBASE+i, LOPRI); |
90 | } |
131 | } |
91 | } |
132 | } |
92 | 133 | ||
93 | 134 | ||
94 | /* |
135 | /* |
95 | * Ensure that io_apic has unique ID. |
136 | * Ensure that io_apic has unique ID. |
96 | */ |
137 | */ |
97 | tmp = io_apic_read(IOAPICID); |
138 | tmp = io_apic_read(IOAPICID); |
98 | id = (tmp >> 24) & 0xf; |
139 | id = (tmp >> 24) & 0xf; |
99 | if ((1<<id) & apic_id_mask) { |
140 | if ((1<<id) & apic_id_mask) { |
100 | int i; |
141 | int i; |
101 | 142 | ||
102 | for (i=0; i<15; i++) { |
143 | for (i=0; i<15; i++) { |
103 | if (!((1<<i) & apic_id_mask)) { |
144 | if (!((1<<i) & apic_id_mask)) { |
104 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
145 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
105 | break; |
146 | break; |
106 | } |
147 | } |
107 | } |
148 | } |
108 | } |
149 | } |
109 | 150 | ||
110 | /* |
151 | /* |
111 | * Configure the BSP's lapic. |
152 | * Configure the BSP's lapic. |
112 | */ |
153 | */ |
113 | l_apic_init(); |
154 | l_apic_init(); |
114 | l_apic_debug(); |
155 | l_apic_debug(); |
115 | } |
156 | } |
116 | 157 | ||
- | 158 | /** APIC spurious interrupt handler. |
|
- | 159 | * |
|
- | 160 | * @param n Interrupt vector. |
|
- | 161 | * @param stack Interrupted stack. |
|
- | 162 | */ |
|
117 | void apic_spurious(__u8 n, __native stack[]) |
163 | void apic_spurious(__u8 n, __native stack[]) |
118 | { |
164 | { |
119 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
165 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
120 | } |
166 | } |
121 | 167 | ||
- | 168 | /** Poll for APIC errors. |
|
- | 169 | * |
|
- | 170 | * Examine Error Status Register and report all errors found. |
|
- | 171 | * |
|
- | 172 | * @return 0 on error, 1 on success. |
|
- | 173 | */ |
|
122 | int apic_poll_errors(void) |
174 | int apic_poll_errors(void) |
123 | { |
175 | { |
124 | __u32 esr; |
176 | esr_t esr; |
125 | 177 | ||
126 | esr = l_apic[ESR] & ~ESRClear; |
178 | esr.value = l_apic[ESR]; |
127 | 179 | ||
128 | if ((esr>>0) & 1) |
180 | if (esr.send_checksum_error) |
129 | printf("Send CS Error\n"); |
181 | printf("Send CS Error\n"); |
130 | if ((esr>>1) & 1) |
182 | if (esr.receive_checksum_error) |
131 | printf("Receive CS Error\n"); |
183 | printf("Receive CS Error\n"); |
132 | if ((esr>>2) & 1) |
184 | if (esr.send_accept_error) |
133 | printf("Send Accept Error\n"); |
185 | printf("Send Accept Error\n"); |
134 | if ((esr>>3) & 1) |
186 | if (esr.receive_accept_error) |
135 | printf("Receive Accept Error\n"); |
187 | printf("Receive Accept Error\n"); |
136 | if ((esr>>5) & 1) |
188 | if (esr.send_illegal_vector) |
137 | printf("Send Illegal Vector\n"); |
189 | printf("Send Illegal Vector\n"); |
138 | if ((esr>>6) & 1) |
190 | if (esr.received_illegal_vector) |
139 | printf("Received Illegal Vector\n"); |
191 | printf("Received Illegal Vector\n"); |
140 | if ((esr>>7) & 1) |
192 | if (esr.illegal_register_address) |
141 | printf("Illegal Register Address\n"); |
193 | printf("Illegal Register Address\n"); |
142 | 194 | ||
143 | return !esr; |
195 | return !esr.err_bitmap; |
144 | } |
196 | } |
145 | 197 | ||
- | 198 | /** Send all CPUs excluding CPU IPI vector. |
|
- | 199 | * |
|
- | 200 | * @param vector Interrupt vector to be sent. |
|
146 | /* |
201 | * |
147 | * Send all CPUs excluding CPU IPI vector. |
202 | * @return 0 on failure, 1 on success. |
148 | */ |
203 | */ |
149 | int l_apic_broadcast_custom_ipi(__u8 vector) |
204 | int l_apic_broadcast_custom_ipi(__u8 vector) |
150 | { |
205 | { |
151 | icr_t icr; |
206 | icr_t icr; |
152 | 207 | ||
153 | icr.lo = l_apic[ICRlo]; |
208 | icr.lo = l_apic[ICRlo]; |
154 | icr.delmod = DELMOD_FIXED; |
209 | icr.delmod = DELMOD_FIXED; |
155 | icr.destmod = DESTMOD_LOGIC; |
210 | icr.destmod = DESTMOD_LOGIC; |
156 | icr.level = LEVEL_ASSERT; |
211 | icr.level = LEVEL_ASSERT; |
157 | icr.shorthand = SHORTHAND_ALL_EXCL; |
212 | icr.shorthand = SHORTHAND_ALL_EXCL; |
158 | icr.trigger_mode = TRIGMOD_LEVEL; |
213 | icr.trigger_mode = TRIGMOD_LEVEL; |
159 | icr.vector = vector; |
214 | icr.vector = vector; |
160 | 215 | ||
161 | l_apic[ICRlo] = icr.lo; |
216 | l_apic[ICRlo] = icr.lo; |
162 | 217 | ||
163 | icr.lo = l_apic[ICRlo]; |
218 | icr.lo = l_apic[ICRlo]; |
164 | if (icr.lo & SEND_PENDING) |
219 | if (icr.lo & SEND_PENDING) |
165 | printf("IPI is pending.\n"); |
220 | printf("IPI is pending.\n"); |
166 | 221 | ||
167 | return apic_poll_errors(); |
222 | return apic_poll_errors(); |
168 | } |
223 | } |
169 | 224 | ||
- | 225 | /** Universal Start-up Algorithm for bringing up the AP processors. |
|
170 | /* |
226 | * |
171 | * Universal Start-up Algorithm for bringing up the AP processors. |
227 | * @param apicid APIC ID of the processor to be brought up. |
- | 228 | * |
|
- | 229 | * @return 0 on failure, 1 on success. |
|
172 | */ |
230 | */ |
173 | int l_apic_send_init_ipi(__u8 apicid) |
231 | int l_apic_send_init_ipi(__u8 apicid) |
174 | { |
232 | { |
175 | icr_t icr; |
233 | icr_t icr; |
176 | int i; |
234 | int i; |
177 | 235 | ||
178 | /* |
236 | /* |
179 | * Read the ICR register in and zero all non-reserved fields. |
237 | * Read the ICR register in and zero all non-reserved fields. |
180 | */ |
238 | */ |
181 | icr.lo = l_apic[ICRlo]; |
239 | icr.lo = l_apic[ICRlo]; |
182 | icr.hi = l_apic[ICRhi]; |
240 | icr.hi = l_apic[ICRhi]; |
183 | 241 | ||
184 | icr.delmod = DELMOD_INIT; |
242 | icr.delmod = DELMOD_INIT; |
185 | icr.destmod = DESTMOD_PHYS; |
243 | icr.destmod = DESTMOD_PHYS; |
186 | icr.level = LEVEL_ASSERT; |
244 | icr.level = LEVEL_ASSERT; |
187 | icr.trigger_mode = TRIGMOD_LEVEL; |
245 | icr.trigger_mode = TRIGMOD_LEVEL; |
188 | icr.shorthand = SHORTHAND_NONE; |
246 | icr.shorthand = SHORTHAND_NONE; |
189 | icr.vector = 0; |
247 | icr.vector = 0; |
190 | icr.dest = apicid; |
248 | icr.dest = apicid; |
191 | 249 | ||
192 | l_apic[ICRhi] = icr.hi; |
250 | l_apic[ICRhi] = icr.hi; |
193 | l_apic[ICRlo] = icr.lo; |
251 | l_apic[ICRlo] = icr.lo; |
194 | 252 | ||
195 | /* |
253 | /* |
196 | * According to MP Specification, 20us should be enough to |
254 | * According to MP Specification, 20us should be enough to |
197 | * deliver the IPI. |
255 | * deliver the IPI. |
198 | */ |
256 | */ |
199 | delay(20); |
257 | delay(20); |
200 | 258 | ||
201 | if (!apic_poll_errors()) return 0; |
259 | if (!apic_poll_errors()) return 0; |
202 | 260 | ||
203 | icr.lo = l_apic[ICRlo]; |
261 | icr.lo = l_apic[ICRlo]; |
204 | if (icr.lo & SEND_PENDING) |
262 | if (icr.lo & SEND_PENDING) |
205 | printf("IPI is pending.\n"); |
263 | printf("IPI is pending.\n"); |
206 | 264 | ||
207 | icr.delmod = DELMOD_INIT; |
265 | icr.delmod = DELMOD_INIT; |
208 | icr.destmod = DESTMOD_PHYS; |
266 | icr.destmod = DESTMOD_PHYS; |
209 | icr.level = LEVEL_DEASSERT; |
267 | icr.level = LEVEL_DEASSERT; |
210 | icr.shorthand = SHORTHAND_NONE; |
268 | icr.shorthand = SHORTHAND_NONE; |
211 | icr.trigger_mode = TRIGMOD_LEVEL; |
269 | icr.trigger_mode = TRIGMOD_LEVEL; |
212 | icr.vector = 0; |
270 | icr.vector = 0; |
213 | l_apic[ICRlo] = icr.lo; |
271 | l_apic[ICRlo] = icr.lo; |
214 | 272 | ||
215 | /* |
273 | /* |
216 | * Wait 10ms as MP Specification specifies. |
274 | * Wait 10ms as MP Specification specifies. |
217 | */ |
275 | */ |
218 | delay(10000); |
276 | delay(10000); |
219 | 277 | ||
220 | if (!is_82489DX_apic(l_apic[LAVR])) { |
278 | if (!is_82489DX_apic(l_apic[LAVR])) { |
221 | /* |
279 | /* |
222 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
280 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
223 | */ |
281 | */ |
224 | for (i = 0; i<2; i++) { |
282 | for (i = 0; i<2; i++) { |
225 | icr.lo = l_apic[ICRlo]; |
283 | icr.lo = l_apic[ICRlo]; |
226 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
284 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
227 | icr.delmod = DELMOD_STARTUP; |
285 | icr.delmod = DELMOD_STARTUP; |
228 | icr.destmod = DESTMOD_PHYS; |
286 | icr.destmod = DESTMOD_PHYS; |
229 | icr.level = LEVEL_ASSERT; |
287 | icr.level = LEVEL_ASSERT; |
230 | icr.shorthand = SHORTHAND_NONE; |
288 | icr.shorthand = SHORTHAND_NONE; |
231 | icr.trigger_mode = TRIGMOD_LEVEL; |
289 | icr.trigger_mode = TRIGMOD_LEVEL; |
232 | l_apic[ICRlo] = icr.lo; |
290 | l_apic[ICRlo] = icr.lo; |
233 | delay(200); |
291 | delay(200); |
234 | } |
292 | } |
235 | } |
293 | } |
236 | 294 | ||
237 | 295 | ||
238 | return apic_poll_errors(); |
296 | return apic_poll_errors(); |
239 | } |
297 | } |
240 | 298 | ||
- | 299 | /** Initialize Local APIC. */ |
|
241 | void l_apic_init(void) |
300 | void l_apic_init(void) |
242 | { |
301 | { |
243 | lvt_error_t error; |
302 | lvt_error_t error; |
244 | lvt_lint_t lint; |
303 | lvt_lint_t lint; |
245 | svr_t svr; |
304 | svr_t svr; |
246 | lvt_tm_t tm; |
- | |
247 | icr_t icr; |
305 | icr_t icr; |
- | 306 | tdcr_t tdcr; |
|
- | 307 | lvt_tm_t tm; |
|
248 | __u32 t1, t2; |
308 | __u32 t1, t2; |
249 | 309 | ||
250 | /* Initialize LVT Error register. */ |
310 | /* Initialize LVT Error register. */ |
251 | error.value = l_apic[LVT_Err]; |
311 | error.value = l_apic[LVT_Err]; |
252 | error.masked = true; |
312 | error.masked = true; |
253 | l_apic[LVT_Err] = error.value; |
313 | l_apic[LVT_Err] = error.value; |
254 | 314 | ||
255 | /* Initialize LVT LINT0 register. */ |
315 | /* Initialize LVT LINT0 register. */ |
256 | lint.value = l_apic[LVT_LINT0]; |
316 | lint.value = l_apic[LVT_LINT0]; |
257 | lint.masked = true; |
317 | lint.masked = true; |
258 | l_apic[LVT_LINT0] = lint.value; |
318 | l_apic[LVT_LINT0] = lint.value; |
259 | 319 | ||
260 | /* Initialize LVT LINT1 register. */ |
320 | /* Initialize LVT LINT1 register. */ |
261 | lint.value = l_apic[LVT_LINT1]; |
321 | lint.value = l_apic[LVT_LINT1]; |
262 | lint.masked = true; |
322 | lint.masked = true; |
263 | l_apic[LVT_LINT1] = lint.value; |
323 | l_apic[LVT_LINT1] = lint.value; |
264 | 324 | ||
265 | /* Spurious-Interrupt Vector Register initialization. */ |
325 | /* Spurious-Interrupt Vector Register initialization. */ |
266 | svr.value = l_apic[SVR]; |
326 | svr.value = l_apic[SVR]; |
267 | svr.vector = VECTOR_APIC_SPUR; |
327 | svr.vector = VECTOR_APIC_SPUR; |
268 | svr.lapic_enabled = true; |
328 | svr.lapic_enabled = true; |
269 | l_apic[SVR] = svr.value; |
329 | l_apic[SVR] = svr.value; |
270 | 330 | ||
271 | l_apic[TPR] &= TPRClear; |
331 | l_apic[TPR] &= TPRClear; |
272 | 332 | ||
273 | if (CPU->arch.family >= 6) |
333 | if (CPU->arch.family >= 6) |
274 | enable_l_apic_in_msr(); |
334 | enable_l_apic_in_msr(); |
275 | 335 | ||
276 | /* Interrupt Command Register initialization. */ |
336 | /* Interrupt Command Register initialization. */ |
277 | icr.lo = l_apic[ICRlo]; |
337 | icr.lo = l_apic[ICRlo]; |
278 | icr.delmod = DELMOD_INIT; |
338 | icr.delmod = DELMOD_INIT; |
279 | icr.destmod = DESTMOD_PHYS; |
339 | icr.destmod = DESTMOD_PHYS; |
280 | icr.level = LEVEL_DEASSERT; |
340 | icr.level = LEVEL_DEASSERT; |
281 | icr.shorthand = SHORTHAND_ALL_INCL; |
341 | icr.shorthand = SHORTHAND_ALL_INCL; |
282 | icr.trigger_mode = TRIGMOD_LEVEL; |
342 | icr.trigger_mode = TRIGMOD_LEVEL; |
283 | l_apic[ICRlo] = icr.lo; |
343 | l_apic[ICRlo] = icr.lo; |
284 | 344 | ||
285 | /* |
- | |
286 | * Program the timer for periodic mode and respective vector. |
345 | /* Timer Divide Configuration Register initialization. */ |
287 | */ |
346 | tdcr.value = l_apic[TDCR]; |
288 | - | ||
289 | l_apic[TDCR] &= TDCRClear; |
347 | tdcr.div_value = DIVIDE_1; |
290 | l_apic[TDCR] |= 0xb; |
348 | l_apic[TDCR] = tdcr.value; |
291 | 349 | ||
- | 350 | /* Program local timer. */ |
|
292 | tm.value = l_apic[LVT_Tm]; |
351 | tm.value = l_apic[LVT_Tm]; |
293 | tm.vector = VECTOR_CLK; |
352 | tm.vector = VECTOR_CLK; |
294 | tm.mode = TIMER_PERIODIC; |
353 | tm.mode = TIMER_PERIODIC; |
295 | tm.masked = false; |
354 | tm.masked = false; |
296 | l_apic[LVT_Tm] = tm.value; |
355 | l_apic[LVT_Tm] = tm.value; |
297 | 356 | ||
- | 357 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
|
298 | t1 = l_apic[CCRT]; |
358 | t1 = l_apic[CCRT]; |
299 | l_apic[ICRT] = 0xffffffff; |
359 | l_apic[ICRT] = 0xffffffff; |
300 | 360 | ||
301 | while (l_apic[CCRT] == t1) |
361 | while (l_apic[CCRT] == t1) |
302 | ; |
362 | ; |
303 | 363 | ||
304 | t1 = l_apic[CCRT]; |
364 | t1 = l_apic[CCRT]; |
305 | delay(1000); |
365 | delay(1000); |
306 | t2 = l_apic[CCRT]; |
366 | t2 = l_apic[CCRT]; |
307 | 367 | ||
308 | l_apic[ICRT] = t1-t2; |
368 | l_apic[ICRT] = t1-t2; |
309 | 369 | ||
310 | } |
370 | } |
311 | 371 | ||
- | 372 | /** Local APIC End of Interrupt. */ |
|
312 | void l_apic_eoi(void) |
373 | void l_apic_eoi(void) |
313 | { |
374 | { |
314 | l_apic[EOI] = 0; |
375 | l_apic[EOI] = 0; |
315 | } |
376 | } |
316 | 377 | ||
- | 378 | /** Dump content of Local APIC registers. */ |
|
317 | void l_apic_debug(void) |
379 | void l_apic_debug(void) |
318 | { |
380 | { |
319 | #ifdef LAPIC_VERBOSE |
381 | #ifdef LAPIC_VERBOSE |
- | 382 | lvt_tm_t tm; |
|
320 | int i, lint; |
383 | lvt_lint_t lint; |
- | 384 | lvt_error_t error; |
|
321 | 385 | ||
322 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
386 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
323 | 387 | ||
324 | printf("LVT_Tm: "); |
388 | tm.value = l_apic[LVT_Tm]; |
325 | if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(','); |
- | |
326 | if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
389 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
327 | if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
- | |
328 | printf("%B\n", l_apic[LVT_Tm] & 0xff); |
- | |
329 | - | ||
330 | for (i=0; i<2; i++) { |
- | |
331 | lint = i ? LVT_LINT1 : LVT_LINT0; |
390 | lint.value = l_apic[LVT_LINT0]; |
332 | printf("LVT_LINT%d: ", i); |
- | |
333 | if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
391 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
334 | if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(','); |
- | |
335 | printf("%d", l_apic[lint] & (1<<14)); putchar(','); |
- | |
336 | printf("%d", l_apic[lint] & (1<<13)); putchar(','); |
- | |
337 | if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
- | |
338 | - | ||
339 | switch ((l_apic[lint]>>8)&7) { |
- | |
340 | case 0: printf("fixed"); break; |
- | |
341 | case 4: printf("NMI"); break; |
- | |
342 | case 7: printf("ExtINT"); break; |
- | |
343 | } |
- | |
344 | putchar(','); |
- | |
345 | printf("%B\n", l_apic[lint] & 0xff); |
392 | lint.value = l_apic[LVT_LINT1]; |
346 | } |
- | |
347 | - | ||
348 | printf("LVT_Err: "); |
- | |
349 | if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
393 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
350 | if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
- | |
351 | printf("%B\n", l_apic[LVT_Err] & 0xff); |
394 | error.value = l_apic[LVT_Err]; |
352 | - | ||
353 | /* |
- | |
354 | * This register is supported only on P6 and higher. |
- | |
355 | */ |
- | |
356 | if (CPU->arch.family > 5) { |
- | |
357 | printf("LVT_PCINT: "); |
- | |
358 | if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
395 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
359 | if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
- | |
360 | switch ((l_apic[LVT_PCINT] >> 8)&7) { |
- | |
361 | case 0: printf("fixed"); break; |
- | |
362 | case 4: printf("NMI"); break; |
- | |
363 | case 7: printf("ExtINT"); break; |
- | |
364 | } |
- | |
365 | putchar(','); |
- | |
366 | printf("%B\n", l_apic[LVT_PCINT] & 0xff); |
- | |
367 | } |
- | |
368 | #endif |
396 | #endif |
369 | } |
397 | } |
370 | 398 | ||
- | 399 | /** Local APIC Timer Interrupt. |
|
- | 400 | * |
|
- | 401 | * @param n Interrupt vector number. |
|
- | 402 | * @param stack Interrupted stack. |
|
- | 403 | */ |
|
371 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
404 | void l_apic_timer_interrupt(__u8 n, __native stack[]) |
372 | { |
405 | { |
373 | l_apic_eoi(); |
406 | l_apic_eoi(); |
374 | clock(); |
407 | clock(); |
375 | } |
408 | } |
376 | 409 | ||
- | 410 | /** Get Local APIC ID. |
|
- | 411 | * |
|
- | 412 | * @return Local APIC ID. |
|
- | 413 | */ |
|
377 | __u8 l_apic_id(void) |
414 | __u8 l_apic_id(void) |
378 | { |
415 | { |
- | 416 | lapic_id_t lapic_id; |
|
- | 417 | ||
379 | return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; |
418 | lapic_id.value = l_apic[L_APIC_ID]; |
- | 419 | return lapic_id.apic_id; |
|
380 | } |
420 | } |
381 | 421 | ||
- | 422 | /** Read from IO APIC register. |
|
- | 423 | * |
|
- | 424 | * @param address IO APIC register address. |
|
- | 425 | * |
|
- | 426 | * @return Content of the addressed IO APIC register. |
|
- | 427 | */ |
|
382 | __u32 io_apic_read(__u8 address) |
428 | __u32 io_apic_read(__u8 address) |
383 | { |
429 | { |
384 | __u32 tmp; |
430 | io_regsel_t regsel; |
385 | 431 | ||
386 | tmp = io_apic[IOREGSEL] & ~0xf; |
432 | regsel.value = io_apic[IOREGSEL]; |
- | 433 | regsel.reg_addr = address; |
|
387 | io_apic[IOREGSEL] = tmp | address; |
434 | io_apic[IOREGSEL] = regsel.value; |
388 | return io_apic[IOWIN]; |
435 | return io_apic[IOWIN]; |
389 | } |
436 | } |
390 | 437 | ||
- | 438 | /** Write to IO APIC register. |
|
- | 439 | * |
|
- | 440 | * @param address IO APIC register address. |
|
- | 441 | * @param Content to be written to the addressed IO APIC register. |
|
- | 442 | */ |
|
391 | void io_apic_write(__u8 address, __u32 x) |
443 | void io_apic_write(__u8 address, __u32 x) |
392 | { |
444 | { |
393 | __u32 tmp; |
445 | io_regsel_t regsel; |
394 | 446 | ||
395 | tmp = io_apic[IOREGSEL] & ~0xf; |
447 | regsel.value = io_apic[IOREGSEL]; |
- | 448 | regsel.reg_addr = address; |
|
396 | io_apic[IOREGSEL] = tmp | address; |
449 | io_apic[IOREGSEL] = regsel.value; |
397 | io_apic[IOWIN] = x; |
450 | io_apic[IOWIN] = x; |
398 | } |
451 | } |
399 | 452 | ||
- | 453 | /** Change some attributes of one item in I/O Redirection Table. |
|
- | 454 | * |
|
- | 455 | * @param pin IO APIC pin number. |
|
- | 456 | * @param dest Interrupt destination address. |
|
- | 457 | * @param v Interrupt vector to trigger. |
|
- | 458 | * @param flags Flags. |
|
- | 459 | */ |
|
400 | void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) |
460 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
401 | { |
461 | { |
402 | io_redirection_reg_t reg; |
462 | io_redirection_reg_t reg; |
403 | int dlvr = 0; |
463 | int dlvr = DELMOD_FIXED; |
404 | 464 | ||
405 | if (flags & LOPRI) |
465 | if (flags & LOPRI) |
406 | dlvr = DELMOD_LOWPRI; |
466 | dlvr = DELMOD_LOWPRI; |
407 | 467 | ||
408 | 468 | ||
409 | reg.lo = io_apic_read(IOREDTBL + signal*2); |
469 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
410 | reg.hi = io_apic_read(IOREDTBL + signal*2 + 1); |
470 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
411 | 471 | ||
412 | reg.dest = dest; |
472 | reg.dest = dest; |
413 | reg.destmod = DESTMOD_LOGIC; |
473 | reg.destmod = DESTMOD_LOGIC; |
414 | reg.trigger_mode = TRIGMOD_EDGE; |
474 | reg.trigger_mode = TRIGMOD_EDGE; |
415 | reg.intpol = POLARITY_HIGH; |
475 | reg.intpol = POLARITY_HIGH; |
416 | reg.delmod = dlvr; |
476 | reg.delmod = dlvr; |
417 | reg.intvec = v; |
477 | reg.intvec = v; |
418 | 478 | ||
419 | io_apic_write(IOREDTBL + signal*2, reg.lo); |
479 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
420 | io_apic_write(IOREDTBL + signal*2 + 1, reg.hi); |
480 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
421 | } |
481 | } |
422 | 482 | ||
- | 483 | /** Mask IRQs in IO APIC. |
|
- | 484 | * |
|
- | 485 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
|
- | 486 | */ |
|
423 | void io_apic_disable_irqs(__u16 irqmask) |
487 | void io_apic_disable_irqs(__u16 irqmask) |
424 | { |
488 | { |
425 | io_redirection_reg_t reg; |
489 | io_redirection_reg_t reg; |
426 | int i, pin; |
490 | int i, pin; |
427 | 491 | ||
428 | for (i=0;i<16;i++) { |
492 | for (i=0;i<16;i++) { |
429 | if ((irqmask>>i) & 1) { |
493 | if ((irqmask>>i) & 1) { |
430 | /* |
494 | /* |
431 | * Mask the signal input in IO APIC if there is a |
495 | * Mask the signal input in IO APIC if there is a |
432 | * mapping for the respective IRQ number. |
496 | * mapping for the respective IRQ number. |
433 | */ |
497 | */ |
434 | pin = smp_irq_to_pin(i); |
498 | pin = smp_irq_to_pin(i); |
435 | if (pin != -1) { |
499 | if (pin != -1) { |
436 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
500 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
437 | reg.masked = true; |
501 | reg.masked = true; |
438 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
502 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
439 | } |
503 | } |
440 | 504 | ||
441 | } |
505 | } |
442 | } |
506 | } |
443 | } |
507 | } |
444 | 508 | ||
- | 509 | /** Unmask IRQs in IO APIC. |
|
- | 510 | * |
|
- | 511 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
|
- | 512 | */ |
|
445 | void io_apic_enable_irqs(__u16 irqmask) |
513 | void io_apic_enable_irqs(__u16 irqmask) |
446 | { |
514 | { |
447 | int i, pin; |
515 | int i, pin; |
448 | io_redirection_reg_t reg; |
516 | io_redirection_reg_t reg; |
449 | 517 | ||
450 | for (i=0;i<16;i++) { |
518 | for (i=0;i<16;i++) { |
451 | if ((irqmask>>i) & 1) { |
519 | if ((irqmask>>i) & 1) { |
452 | /* |
520 | /* |
453 | * Unmask the signal input in IO APIC if there is a |
521 | * Unmask the signal input in IO APIC if there is a |
454 | * mapping for the respective IRQ number. |
522 | * mapping for the respective IRQ number. |
455 | */ |
523 | */ |
456 | pin = smp_irq_to_pin(i); |
524 | pin = smp_irq_to_pin(i); |
457 | if (pin != -1) { |
525 | if (pin != -1) { |
458 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
526 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
459 | reg.masked = false; |
527 | reg.masked = false; |
460 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
528 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
461 | } |
529 | } |
462 | 530 | ||
463 | } |
531 | } |
464 | } |
532 | } |
465 | 533 | ||
466 | } |
534 | } |
467 | 535 | ||
468 | #endif /* CONFIG_SMP */ |
536 | #endif /* CONFIG_SMP */ |
469 | 537 |