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1 | # |
1 | # |
2 | # Copyright (C) 2001-2004 Jakub Jermar |
2 | # Copyright (C) 2001-2004 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | ## very low and hardware-level functions |
29 | ## very low and hardware-level functions |
30 | 30 | ||
31 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
32 | # and 1 means interrupt with error word |
32 | # and 1 means interrupt with error word |
33 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
33 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | 34 | ||
35 | .text |
35 | .text |
36 | 36 | ||
37 | .global paging_on |
37 | .global paging_on |
38 | .global enable_l_apic_in_msr |
38 | .global enable_l_apic_in_msr |
39 | .global interrupt_handlers |
39 | .global interrupt_handlers |
40 | 40 | ||
41 | ## Turn paging on |
41 | ## Turn paging on |
42 | # |
42 | # |
43 | # Enable paging and write-back caching in CR0. |
43 | # Enable paging and write-back caching in CR0. |
44 | # |
44 | # |
45 | paging_on: |
45 | paging_on: |
46 | movl %cr0,%edx |
46 | movl %cr0,%edx |
47 | orl $(1<<31),%edx # paging on |
47 | orl $(1<<31),%edx # paging on |
48 | andl $~((1<<30)|(1<<29)),%edx # clear Cache Disable and not Write Though |
48 | andl $~((1<<30)|(1<<29)),%edx # clear Cache Disable and not Write Though |
49 | movl %edx,%cr0 |
49 | movl %edx,%cr0 |
50 | jmp 0f |
50 | jmp 0f |
51 | 0: |
51 | 0: |
52 | ret |
52 | ret |
53 | 53 | ||
54 | 54 | ||
55 | ## Enable local APIC |
55 | ## Enable local APIC |
56 | # |
56 | # |
57 | # Enable local APIC in MSR. |
57 | # Enable local APIC in MSR. |
58 | # |
58 | # |
59 | enable_l_apic_in_msr: |
59 | enable_l_apic_in_msr: |
60 | push %eax |
60 | push %eax |
61 | 61 | ||
62 | movl $0x1b, %ecx |
62 | movl $0x1b, %ecx |
63 | rdmsr |
63 | rdmsr |
64 | orl $(1<<11),%eax |
64 | orl $(1<<11),%eax |
65 | orl $(0xfee00000),%eax |
65 | orl $(0xfee00000),%eax |
66 | wrmsr |
66 | wrmsr |
67 | 67 | ||
68 | pop %eax |
68 | pop %eax |
69 | ret |
69 | ret |
70 | 70 | ||
71 | 71 | ||
72 | ## Declare interrupt handlers |
72 | ## Declare interrupt handlers |
73 | # |
73 | # |
74 | # Declare interrupt handlers for n interrupt |
74 | # Declare interrupt handlers for n interrupt |
75 | # vectors starting at vector i. |
75 | # vectors starting at vector i. |
76 | # |
76 | # |
77 | # The handlers setup data segment registers |
77 | # The handlers setup data segment registers |
78 | # and call exc_dispatch(). |
78 | # and call exc_dispatch(). |
79 | # |
79 | # |
80 | .macro handler i n |
80 | .macro handler i n |
81 | push %eax |
81 | push %eax |
82 | 82 | ||
- | 83 | /* |
|
83 | # Test if this is interrupt with error word or not |
84 | * Test if this is interrupt with error word or not. |
- | 85 | * Be careful about width of the shift. |
|
- | 86 | */ |
|
- | 87 | .iflt \i-32 |
|
84 | movl $(1<<\i), %eax |
88 | movl $(1<<\i), %eax |
- | 89 | .else |
|
- | 90 | movl $0, %eax |
|
- | 91 | .endif |
|
85 | andl $ERROR_WORD_INTERRUPT_LIST,%eax |
92 | andl $ERROR_WORD_INTERRUPT_LIST,%eax |
86 | 93 | ||
87 | /* |
94 | /* |
88 | * If this interrupt/exception stores error word, |
95 | * If this interrupt/exception stores error word, |
89 | * we need to pop EAX. |
96 | * we need to pop EAX. |
90 | * If this interrupt doesn't store error word, we emulate it |
97 | * If this interrupt doesn't store error word, we emulate it |
91 | * for the sake of consistent pstate structure. In that case |
98 | * for the sake of consistent pstate structure. In that case |
92 | * we merely leave the EAX on the stack. |
99 | * we merely leave the EAX on the stack. |
93 | */ |
100 | */ |
94 | jz 0f |
101 | jz 0f |
95 | 102 | ||
96 | /* |
103 | /* |
97 | * This exception stores error word. |
104 | * This exception stores error word. |
98 | */ |
105 | */ |
99 | pop %eax |
106 | pop %eax |
100 | jmp 1f |
107 | jmp 1f |
101 | 108 | ||
102 | 0: |
109 | 0: |
103 | /* |
110 | /* |
104 | * This interrupt doesn't store error word. |
111 | * This interrupt doesn't store error word. |
105 | * Just restore EAX without doing POP. |
112 | * Just restore EAX without doing POP. |
106 | */ |
113 | */ |
107 | movl (%esp), %eax |
114 | movl (%esp), %eax |
108 | 115 | ||
109 | 1: |
116 | 1: |
110 | pusha |
117 | pusha |
111 | movl %esp, %ebp |
118 | movl %esp, %ebp |
112 | push %ds |
119 | push %ds |
113 | push %es |
120 | push %es |
114 | 121 | ||
115 | # we must fill the data segment registers |
122 | # we must fill the data segment registers |
116 | movw $16,%ax |
123 | movw $16,%ax |
117 | movw %ax,%ds |
124 | movw %ax,%ds |
118 | movw %ax,%es |
125 | movw %ax,%es |
119 | 126 | ||
120 | movl $(\i),%edi |
127 | movl $(\i),%edi |
121 | pushl %ebp |
128 | pushl %ebp |
122 | pushl %edi |
129 | pushl %edi |
123 | call exc_dispatch |
130 | call exc_dispatch |
124 | addl $8,%esp |
131 | addl $8,%esp |
125 | 132 | ||
126 | pop %es |
133 | pop %es |
127 | pop %ds |
134 | pop %ds |
128 | 135 | ||
129 | # Clear Nested Task flag. |
136 | # Clear Nested Task flag. |
130 | pushfl |
137 | pushfl |
131 | pop %eax |
138 | pop %eax |
132 | and $0xFFFFBFFF,%eax |
139 | and $0xFFFFBFFF,%eax |
133 | push %eax |
140 | push %eax |
134 | popfl |
141 | popfl |
135 | 142 | ||
136 | popa |
143 | popa |
137 | add $4,%esp # Skip error word, whether real or fake. |
144 | add $4,%esp # Skip error word, whether real or fake. |
138 | iret |
145 | iret |
139 | 146 | ||
140 | .if (\n-\i)-1 |
147 | .if (\n-\i)-1 |
141 | handler "(\i+1)",\n |
148 | handler "(\i+1)",\n |
142 | .endif |
149 | .endif |
143 | .endm |
150 | .endm |
144 | 151 | ||
145 | # keep in sync with pm.h !!! |
152 | # keep in sync with pm.h !!! |
146 | IDT_ITEMS=64 |
153 | IDT_ITEMS=64 |
147 | interrupt_handlers: |
154 | interrupt_handlers: |
148 | h_start: |
155 | h_start: |
149 | handler 0 64 |
156 | handler 0 64 |
150 | # handler 64 128 |
157 | # handler 64 128 |
151 | # handler 128 192 |
158 | # handler 128 192 |
152 | # handler 192 256 |
159 | # handler 192 256 |
153 | h_end: |
160 | h_end: |
154 | 161 | ||
155 | .data |
162 | .data |
156 | .global interrupt_handler_size |
163 | .global interrupt_handler_size |
157 | 164 | ||
158 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
165 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
159 | 166 |