Rev 513 | Rev 515 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 513 | Rev 514 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __APIC_H__ |
29 | #ifndef __APIC_H__ |
30 | #define __APIC_H__ |
30 | #define __APIC_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <cpu.h> |
33 | #include <cpu.h> |
34 | 34 | ||
35 | #define FIXED (0<<0) |
35 | #define FIXED (0<<0) |
36 | #define LOPRI (1<<0) |
36 | #define LOPRI (1<<0) |
37 | 37 | ||
38 | /* local APIC macros */ |
38 | /* local APIC macros */ |
39 | #define IPI_INIT 0 |
39 | #define IPI_INIT 0 |
40 | #define IPI_STARTUP 0 |
40 | #define IPI_STARTUP 0 |
41 | 41 | ||
42 | /** Delivery modes. */ |
42 | /** Delivery modes. */ |
43 | #define DELMOD_FIXED 0x0 |
43 | #define DELMOD_FIXED 0x0 |
44 | #define DELMOD_LOWPRI 0x1 |
44 | #define DELMOD_LOWPRI 0x1 |
45 | #define DELMOD_SMI 0x2 |
45 | #define DELMOD_SMI 0x2 |
46 | /* 0x3 reserved */ |
46 | /* 0x3 reserved */ |
47 | #define DELMOD_NMI 0x4 |
47 | #define DELMOD_NMI 0x4 |
48 | #define DELMOD_INIT 0x5 |
48 | #define DELMOD_INIT 0x5 |
49 | #define DELMOD_STARTUP 0x6 |
49 | #define DELMOD_STARTUP 0x6 |
50 | #define DELMOD_EXTINT 0x7 |
50 | #define DELMOD_EXTINT 0x7 |
51 | 51 | ||
52 | /** Destination modes. */ |
52 | /** Destination modes. */ |
53 | #define DESTMOD_PHYS 0x0 |
53 | #define DESTMOD_PHYS 0x0 |
54 | #define DESTMOD_LOGIC 0x1 |
54 | #define DESTMOD_LOGIC 0x1 |
55 | 55 | ||
56 | /** Trigger Modes. */ |
56 | /** Trigger Modes. */ |
57 | #define TRIGMOD_EDGE 0x0 |
57 | #define TRIGMOD_EDGE 0x0 |
58 | #define TRIGMOD_LEVEL 0x1 |
58 | #define TRIGMOD_LEVEL 0x1 |
59 | 59 | ||
60 | /** Levels. */ |
60 | /** Levels. */ |
61 | #define LEVEL_DEASSERT 0x0 |
61 | #define LEVEL_DEASSERT 0x0 |
62 | #define LEVEL_ASSERT 0x1 |
62 | #define LEVEL_ASSERT 0x1 |
63 | 63 | ||
64 | /** Destination Shorthands. */ |
64 | /** Destination Shorthands. */ |
65 | #define SHORTHAND_NONE 0x0 |
65 | #define SHORTHAND_NONE 0x0 |
66 | #define SHORTHAND_SELF 0x1 |
66 | #define SHORTHAND_SELF 0x1 |
67 | #define SHORTHAND_ALL_INCL 0x2 |
67 | #define SHORTHAND_ALL_INCL 0x2 |
68 | #define SHORTHAND_ALL_EXCL 0x3 |
68 | #define SHORTHAND_ALL_EXCL 0x3 |
69 | 69 | ||
70 | /** Interrupt Input Pin Polarities. */ |
70 | /** Interrupt Input Pin Polarities. */ |
71 | #define POLARITY_HIGH 0x0 |
71 | #define POLARITY_HIGH 0x0 |
72 | #define POLARITY_LOW 0x1 |
72 | #define POLARITY_LOW 0x1 |
73 | 73 | ||
- | 74 | /** Divide Values. (Bit 2 is always 0) */ |
|
- | 75 | #define DIVIDE_2 0x0 |
|
- | 76 | #define DIVIDE_4 0x1 |
|
- | 77 | #define DIVIDE_8 0x2 |
|
- | 78 | #define DIVIDE_16 0x3 |
|
- | 79 | #define DIVIDE_32 0x8 |
|
- | 80 | #define DIVIDE_64 0x9 |
|
- | 81 | #define DIVIDE_128 0xa |
|
- | 82 | #define DIVIDE_1 0xb |
|
- | 83 | ||
- | 84 | /** Timer Modes. */ |
|
- | 85 | #define TIMER_ONESHOT 0x0 |
|
- | 86 | #define TIMER_PERIODIC 0x1 |
|
- | 87 | ||
74 | #define SEND_PENDING (1<<12) |
88 | #define SEND_PENDING (1<<12) |
75 | 89 | ||
76 | /** Interrupt Command Register. */ |
90 | /** Interrupt Command Register. */ |
77 | #define ICRlo (0x300/sizeof(__u32)) |
91 | #define ICRlo (0x300/sizeof(__u32)) |
78 | #define ICRhi (0x310/sizeof(__u32)) |
92 | #define ICRhi (0x310/sizeof(__u32)) |
79 | struct icr { |
93 | struct icr { |
80 | union { |
94 | union { |
81 | __u32 lo; |
95 | __u32 lo; |
82 | struct { |
96 | struct { |
83 | __u8 vector; /**< Interrupt Vector. */ |
97 | __u8 vector; /**< Interrupt Vector. */ |
84 | unsigned delmod : 3; /**< Delivery Mode. */ |
98 | unsigned delmod : 3; /**< Delivery Mode. */ |
85 | unsigned destmod : 1; /**< Destination Mode. */ |
99 | unsigned destmod : 1; /**< Destination Mode. */ |
86 | unsigned delivs : 1; /**< Delivery status (RO). */ |
100 | unsigned delivs : 1; /**< Delivery status (RO). */ |
87 | unsigned : 1; /**< Reserved. */ |
101 | unsigned : 1; /**< Reserved. */ |
88 | unsigned level : 1; /**< Level. */ |
102 | unsigned level : 1; /**< Level. */ |
89 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
103 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
90 | unsigned : 2; /**< Reserved. */ |
104 | unsigned : 2; /**< Reserved. */ |
91 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
105 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
92 | unsigned : 12; /**< Reserved. */ |
106 | unsigned : 12; /**< Reserved. */ |
93 | } __attribute__ ((packed)); |
107 | } __attribute__ ((packed)); |
94 | }; |
108 | }; |
95 | union { |
109 | union { |
96 | __u32 hi; |
110 | __u32 hi; |
97 | struct { |
111 | struct { |
98 | unsigned : 24; /**< Reserved. */ |
112 | unsigned : 24; /**< Reserved. */ |
99 | __u8 dest; /**< Destination field. */ |
113 | __u8 dest; /**< Destination field. */ |
100 | } __attribute__ ((packed)); |
114 | } __attribute__ ((packed)); |
101 | }; |
115 | }; |
102 | } __attribute__ ((packed)); |
116 | } __attribute__ ((packed)); |
103 | typedef struct icr icr_t; |
117 | typedef struct icr icr_t; |
104 | 118 | ||
105 | /* End Of Interrupt */ |
119 | /* End Of Interrupt */ |
106 | #define EOI (0x0b0/sizeof(__u32)) |
120 | #define EOI (0x0b0/sizeof(__u32)) |
107 | 121 | ||
108 | /* Error Status Register */ |
122 | /** Error Status Register. */ |
109 | #define ESR (0x280/sizeof(__u32)) |
123 | #define ESR (0x280/sizeof(__u32)) |
- | 124 | union esr { |
|
- | 125 | __u32 value; |
|
- | 126 | __u8 err_bitmap; |
|
- | 127 | struct { |
|
- | 128 | unsigned send_checksum_error : 1; |
|
- | 129 | unsigned receive_checksum_error : 1; |
|
- | 130 | unsigned send_accept_error : 1; |
|
- | 131 | unsigned receive_accept_error : 1; |
|
- | 132 | unsigned : 1; |
|
- | 133 | unsigned send_illegal_vector : 1; |
|
- | 134 | unsigned received_illegal_vector : 1; |
|
110 | #define ESRClear ((0xffffff<<8)|(1<<4)) |
135 | unsigned illegal_register_address : 1; |
- | 136 | unsigned : 24; |
|
- | 137 | } __attribute__ ((packed)); |
|
- | 138 | }; |
|
- | 139 | typedef union esr esr_t; |
|
111 | 140 | ||
112 | /* Task Priority Register */ |
141 | /* Task Priority Register */ |
113 | #define TPR (0x080/sizeof(__u32)) |
142 | #define TPR (0x080/sizeof(__u32)) |
114 | #define TPRClear 0xffffff00 |
143 | #define TPRClear 0xffffff00 |
115 | 144 | ||
116 | /** Spurious-Interrupt Vector Register. */ |
145 | /** Spurious-Interrupt Vector Register. */ |
117 | #define SVR (0x0f0/sizeof(__u32)) |
146 | #define SVR (0x0f0/sizeof(__u32)) |
118 | union svr { |
147 | union svr { |
119 | __u32 value; |
148 | __u32 value; |
120 | struct { |
149 | struct { |
121 | __u8 vector; /**< Spurious Vector */ |
150 | __u8 vector; /**< Spurious Vector */ |
122 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
151 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
123 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
152 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
124 | unsigned : 22; /**< Reserved. */ |
153 | unsigned : 22; /**< Reserved. */ |
125 | } __attribute__ ((packed)); |
154 | } __attribute__ ((packed)); |
126 | }; |
155 | }; |
127 | typedef union svr svr_t; |
156 | typedef union svr svr_t; |
128 | 157 | ||
129 | /* Time Divide Configuration Register */ |
158 | /** Time Divide Configuration Register. */ |
130 | #define TDCR (0x3e0/sizeof(__u32)) |
159 | #define TDCR (0x3e0/sizeof(__u32)) |
- | 160 | union tdcr { |
|
- | 161 | __u32 value; |
|
- | 162 | struct { |
|
- | 163 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
|
- | 164 | unsigned : 28; /**< Reserved. */ |
|
- | 165 | } __attribute__ ((packed)); |
|
- | 166 | }; |
|
131 | #define TDCRClear (~0xb) |
167 | typedef union tdcr tdcr_t; |
132 | 168 | ||
133 | /* Initial Count Register for Timer */ |
169 | /* Initial Count Register for Timer */ |
134 | #define ICRT (0x380/sizeof(__u32)) |
170 | #define ICRT (0x380/sizeof(__u32)) |
135 | 171 | ||
136 | /* Current Count Register for Timer */ |
172 | /* Current Count Register for Timer */ |
137 | #define CCRT (0x390/sizeof(__u32)) |
173 | #define CCRT (0x390/sizeof(__u32)) |
138 | 174 | ||
139 | /** Timer Modes. */ |
- | |
140 | #define TIMER_ONESHOT 0x0 |
- | |
141 | #define TIMER_PERIODIC 0x1 |
- | |
142 | - | ||
143 | /** LVT Timer register. */ |
175 | /** LVT Timer register. */ |
144 | #define LVT_Tm (0x320/sizeof(__u32)) |
176 | #define LVT_Tm (0x320/sizeof(__u32)) |
145 | union lvt_tm { |
177 | union lvt_tm { |
146 | __u32 value; |
178 | __u32 value; |
147 | struct { |
179 | struct { |
148 | __u8 vector; /**< Local Timer Interrupt vector. */ |
180 | __u8 vector; /**< Local Timer Interrupt vector. */ |
149 | unsigned : 4; /**< Reserved. */ |
181 | unsigned : 4; /**< Reserved. */ |
150 | unsigned delivs : 1; /**< Delivery status (RO). */ |
182 | unsigned delivs : 1; /**< Delivery status (RO). */ |
151 | unsigned : 3; /**< Reserved. */ |
183 | unsigned : 3; /**< Reserved. */ |
152 | unsigned masked : 1; /**< Interrupt Mask. */ |
184 | unsigned masked : 1; /**< Interrupt Mask. */ |
153 | unsigned mode : 1; /**< Timer Mode. */ |
185 | unsigned mode : 1; /**< Timer Mode. */ |
154 | unsigned : 14; /**< Reserved. */ |
186 | unsigned : 14; /**< Reserved. */ |
155 | } __attribute__ ((packed)); |
187 | } __attribute__ ((packed)); |
156 | }; |
188 | }; |
157 | typedef union lvt_tm lvt_tm_t; |
189 | typedef union lvt_tm lvt_tm_t; |
158 | 190 | ||
159 | /** LVT LINT registers. */ |
191 | /** LVT LINT registers. */ |
160 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
192 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
161 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
193 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
162 | union lvt_lint { |
194 | union lvt_lint { |
163 | __u32 value; |
195 | __u32 value; |
164 | struct { |
196 | struct { |
165 | __u8 vector; /**< LINT Interrupt vector. */ |
197 | __u8 vector; /**< LINT Interrupt vector. */ |
166 | unsigned delmod : 3; /**< Delivery Mode. */ |
198 | unsigned delmod : 3; /**< Delivery Mode. */ |
167 | unsigned : 1; /**< Reserved. */ |
199 | unsigned : 1; /**< Reserved. */ |
168 | unsigned delivs : 1; /**< Delivery status (RO). */ |
200 | unsigned delivs : 1; /**< Delivery status (RO). */ |
169 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
201 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
170 | unsigned irr : 1; /**< Remote IRR (RO). */ |
202 | unsigned irr : 1; /**< Remote IRR (RO). */ |
171 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
203 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
172 | unsigned masked : 1; /**< Interrupt Mask. */ |
204 | unsigned masked : 1; /**< Interrupt Mask. */ |
173 | unsigned : 15; /**< Reserved. */ |
205 | unsigned : 15; /**< Reserved. */ |
174 | } __attribute__ ((packed)); |
206 | } __attribute__ ((packed)); |
175 | }; |
207 | }; |
176 | typedef union lvt_lint lvt_lint_t; |
208 | typedef union lvt_lint lvt_lint_t; |
177 | 209 | ||
178 | /** LVT Error register. */ |
210 | /** LVT Error register. */ |
179 | #define LVT_Err (0x370/sizeof(__u32)) |
211 | #define LVT_Err (0x370/sizeof(__u32)) |
180 | union lvt_error { |
212 | union lvt_error { |
181 | __u32 value; |
213 | __u32 value; |
182 | struct { |
214 | struct { |
183 | __u8 vector; /**< Local Timer Interrupt vector. */ |
215 | __u8 vector; /**< Local Timer Interrupt vector. */ |
184 | unsigned : 4; /**< Reserved. */ |
216 | unsigned : 4; /**< Reserved. */ |
185 | unsigned delivs : 1; /**< Delivery status (RO). */ |
217 | unsigned delivs : 1; /**< Delivery status (RO). */ |
186 | unsigned : 3; /**< Reserved. */ |
218 | unsigned : 3; /**< Reserved. */ |
187 | unsigned masked : 1; /**< Interrupt Mask. */ |
219 | unsigned masked : 1; /**< Interrupt Mask. */ |
188 | unsigned : 15; /**< Reserved. */ |
220 | unsigned : 15; /**< Reserved. */ |
189 | } __attribute__ ((packed)); |
221 | } __attribute__ ((packed)); |
190 | }; |
222 | }; |
191 | typedef union lvt_error lvt_error_t; |
223 | typedef union lvt_error lvt_error_t; |
192 | 224 | ||
193 | - | ||
194 | #define LVT_PCINT (0x340/sizeof(__u32)) |
- | |
195 | - | ||
196 | /* Local APIC ID Register */ |
225 | /** Local APIC ID Register. */ |
197 | #define L_APIC_ID (0x020/sizeof(__u32)) |
226 | #define L_APIC_ID (0x020/sizeof(__u32)) |
- | 227 | union lapic_id { |
|
- | 228 | __u32 value; |
|
- | 229 | struct { |
|
198 | #define L_APIC_IDClear (~(0xf<<24)) |
230 | unsigned : 24; /**< Reserved. */ |
- | 231 | __u8 apic_id; /**< Local APIC ID. */ |
|
199 | #define L_APIC_IDShift 24 |
232 | } __attribute__ ((packed)); |
- | 233 | }; |
|
200 | #define L_APIC_IDMask 0xf |
234 | typedef union lapic_id lapic_id_t; |
201 | 235 | ||
202 | /* Local APIC Version Register */ |
236 | /* Local APIC Version Register */ |
203 | #define LAVR (0x030/sizeof(__u32)) |
237 | #define LAVR (0x030/sizeof(__u32)) |
204 | #define LAVR_Mask 0xff |
238 | #define LAVR_Mask 0xff |
205 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
239 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
206 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
240 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
207 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
241 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
208 | 242 | ||
209 | /* IO APIC */ |
243 | /* IO APIC */ |
210 | #define IOREGSEL (0x00/sizeof(__u32)) |
244 | #define IOREGSEL (0x00/sizeof(__u32)) |
211 | #define IOWIN (0x10/sizeof(__u32)) |
245 | #define IOWIN (0x10/sizeof(__u32)) |
212 | 246 | ||
213 | #define IOAPICID 0x00 |
247 | #define IOAPICID 0x00 |
214 | #define IOAPICVER 0x01 |
248 | #define IOAPICVER 0x01 |
215 | #define IOAPICARB 0x02 |
249 | #define IOAPICARB 0x02 |
216 | #define IOREDTBL 0x10 |
250 | #define IOREDTBL 0x10 |
217 | 251 | ||
- | 252 | /** I/O Register Select Register. */ |
|
- | 253 | union io_regsel { |
|
- | 254 | __u32 value; |
|
- | 255 | struct { |
|
- | 256 | __u8 reg_addr; /**< APIC Register Address. */ |
|
- | 257 | unsigned : 24; /**< Reserved. */ |
|
- | 258 | } __attribute__ ((packed)); |
|
- | 259 | }; |
|
- | 260 | typedef union io_regsel io_regsel_t; |
|
- | 261 | ||
218 | /** I/O Redirection Register. */ |
262 | /** I/O Redirection Register. */ |
219 | struct io_redirection_reg { |
263 | struct io_redirection_reg { |
220 | union { |
264 | union { |
221 | __u32 lo; |
265 | __u32 lo; |
222 | struct { |
266 | struct { |
223 | __u8 intvec; /**< Interrupt Vector. */ |
267 | __u8 intvec; /**< Interrupt Vector. */ |
224 | unsigned delmod : 3; /**< Delivery Mode. */ |
268 | unsigned delmod : 3; /**< Delivery Mode. */ |
225 | unsigned destmod : 1; /**< Destination mode. */ |
269 | unsigned destmod : 1; /**< Destination mode. */ |
226 | unsigned delivs : 1; /**< Delivery status (RO). */ |
270 | unsigned delivs : 1; /**< Delivery status (RO). */ |
227 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
271 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
228 | unsigned irr : 1; /**< Remote IRR (RO). */ |
272 | unsigned irr : 1; /**< Remote IRR (RO). */ |
229 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
273 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
230 | unsigned masked : 1; /**< Interrupt Mask. */ |
274 | unsigned masked : 1; /**< Interrupt Mask. */ |
231 | unsigned : 15; /**< Reserved. */ |
275 | unsigned : 15; /**< Reserved. */ |
232 | } __attribute__ ((packed)); |
276 | } __attribute__ ((packed)); |
233 | }; |
277 | }; |
234 | union { |
278 | union { |
235 | __u32 hi; |
279 | __u32 hi; |
236 | struct { |
280 | struct { |
237 | unsigned : 24; /**< Reserved. */ |
281 | unsigned : 24; /**< Reserved. */ |
238 | __u8 dest : 8; /**< Destination Field. */ |
282 | __u8 dest : 8; /**< Destination Field. */ |
239 | } __attribute__ ((packed)); |
283 | } __attribute__ ((packed)); |
240 | }; |
284 | }; |
241 | 285 | ||
242 | } __attribute__ ((packed)); |
286 | } __attribute__ ((packed)); |
243 | 287 | ||
244 | typedef struct io_redirection_reg io_redirection_reg_t; |
288 | typedef struct io_redirection_reg io_redirection_reg_t; |
245 | 289 | ||
246 | extern volatile __u32 *l_apic; |
290 | extern volatile __u32 *l_apic; |
247 | extern volatile __u32 *io_apic; |
291 | extern volatile __u32 *io_apic; |
248 | 292 | ||
249 | extern __u32 apic_id_mask; |
293 | extern __u32 apic_id_mask; |
250 | 294 | ||
251 | extern void apic_init(void); |
295 | extern void apic_init(void); |
252 | extern void apic_spurious(__u8 n, __native stack[]); |
296 | extern void apic_spurious(__u8 n, __native stack[]); |
253 | 297 | ||
254 | extern void l_apic_init(void); |
298 | extern void l_apic_init(void); |
255 | extern void l_apic_eoi(void); |
299 | extern void l_apic_eoi(void); |
256 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
300 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
257 | extern int l_apic_send_init_ipi(__u8 apicid); |
301 | extern int l_apic_send_init_ipi(__u8 apicid); |
258 | extern void l_apic_debug(void); |
302 | extern void l_apic_debug(void); |
259 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
303 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
260 | extern __u8 l_apic_id(void); |
304 | extern __u8 l_apic_id(void); |
261 | 305 | ||
262 | extern __u32 io_apic_read(__u8 address); |
306 | extern __u32 io_apic_read(__u8 address); |
263 | extern void io_apic_write(__u8 address , __u32 x); |
307 | extern void io_apic_write(__u8 address , __u32 x); |
264 | extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags); |
308 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
265 | extern void io_apic_disable_irqs(__u16 irqmask); |
309 | extern void io_apic_disable_irqs(__u16 irqmask); |
266 | extern void io_apic_enable_irqs(__u16 irqmask); |
310 | extern void io_apic_enable_irqs(__u16 irqmask); |
267 | 311 | ||
268 | #endif |
312 | #endif |
269 | 313 |