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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup ia32 |
29 | /** @addtogroup ia32 |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #ifndef KERN_ia32_BARRIER_H_ |
35 | #ifndef KERN_ia32_BARRIER_H_ |
| 36 | #define KERN_ia32_BARRIER_H_ |
36 | #define KERN_ia32_BARRIER_H_ |
| 37 | 37 | ||
| 38 | /* |
38 | /* |
| 39 | * NOTE: |
39 | * NOTE: |
| 40 | * No barriers for critical section (i.e. spinlock) on IA-32 are needed: |
40 | * No barriers for critical section (i.e. spinlock) on IA-32 are needed: |
| 41 | * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction |
41 | * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction |
| 42 | * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers |
42 | * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers |
| 43 | */ |
43 | */ |
| 44 | 44 | ||
| 45 | /* |
45 | /* |
| 46 | * Provisions are made to prevent compiler from reordering instructions itself. |
46 | * Provisions are made to prevent compiler from reordering instructions itself. |
| 47 | */ |
47 | */ |
| 48 | 48 | ||
| 49 | #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
49 | #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
| 50 | #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
50 | #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
| 51 | 51 | ||
| 52 | static inline void cpuid_serialization(void) |
52 | static inline void cpuid_serialization(void) |
| 53 | { |
53 | { |
| 54 | asm volatile ( |
54 | asm volatile ( |
| 55 | "xorl %%eax, %%eax\n" |
55 | "xorl %%eax, %%eax\n" |
| 56 | "cpuid\n" |
56 | "cpuid\n" |
| 57 | ::: "eax", "ebx", "ecx", "edx", "memory" |
57 | ::: "eax", "ebx", "ecx", "edx", "memory" |
| 58 | ); |
58 | ); |
| 59 | } |
59 | } |
| 60 | 60 | ||
| 61 | #ifdef CONFIG_FENCES_P4 |
61 | #ifdef CONFIG_FENCES_P4 |
| 62 | # define memory_barrier() asm volatile ("mfence\n" ::: "memory") |
62 | # define memory_barrier() asm volatile ("mfence\n" ::: "memory") |
| 63 | # define read_barrier() asm volatile ("lfence\n" ::: "memory") |
63 | # define read_barrier() asm volatile ("lfence\n" ::: "memory") |
| 64 | # ifdef CONFIG_WEAK_MEMORY |
64 | # ifdef CONFIG_WEAK_MEMORY |
| 65 | # define write_barrier() asm volatile ("sfence\n" ::: "memory") |
65 | # define write_barrier() asm volatile ("sfence\n" ::: "memory") |
| 66 | # else |
66 | # else |
| 67 | # define write_barrier() asm volatile( "" ::: "memory"); |
67 | # define write_barrier() asm volatile( "" ::: "memory"); |
| 68 | # endif |
68 | # endif |
| 69 | #elif CONFIG_FENCES_P3 |
69 | #elif CONFIG_FENCES_P3 |
| 70 | # define memory_barrier() cpuid_serialization() |
70 | # define memory_barrier() cpuid_serialization() |
| 71 | # define read_barrier() cpuid_serialization() |
71 | # define read_barrier() cpuid_serialization() |
| 72 | # ifdef CONFIG_WEAK_MEMORY |
72 | # ifdef CONFIG_WEAK_MEMORY |
| 73 | # define write_barrier() asm volatile ("sfence\n" ::: "memory") |
73 | # define write_barrier() asm volatile ("sfence\n" ::: "memory") |
| 74 | # else |
74 | # else |
| 75 | # define write_barrier() asm volatile( "" ::: "memory"); |
75 | # define write_barrier() asm volatile( "" ::: "memory"); |
| 76 | # endif |
76 | # endif |
| 77 | #else |
77 | #else |
| 78 | # define memory_barrier() cpuid_serialization() |
78 | # define memory_barrier() cpuid_serialization() |
| 79 | # define read_barrier() cpuid_serialization() |
79 | # define read_barrier() cpuid_serialization() |
| 80 | # ifdef CONFIG_WEAK_MEMORY |
80 | # ifdef CONFIG_WEAK_MEMORY |
| 81 | # define write_barrier() cpuid_serialization() |
81 | # define write_barrier() cpuid_serialization() |
| 82 | # else |
82 | # else |
| 83 | # define write_barrier() asm volatile( "" ::: "memory"); |
83 | # define write_barrier() asm volatile( "" ::: "memory"); |
| 84 | # endif |
84 | # endif |
| 85 | #endif |
85 | #endif |
| 86 | 86 | ||
| - | 87 | /* |
|
| - | 88 | * On ia32, the hardware takes care about instruction and data cache coherence, |
|
| - | 89 | * even on SMP systems. We issue a write barrier to be sure that writes |
|
| - | 90 | * queueing in the store buffer drain to the memory (even though it would be |
|
| - | 91 | * sufficient for them to drain to the D-cache). |
|
| - | 92 | */ |
|
| - | 93 | #define smc_coherence(a) write_barrier() |
|
| - | 94 | ||
| 87 | #endif |
95 | #endif |
| 88 | 96 | ||
| 89 | /** @} |
97 | /** @} |
| 90 | */ |
98 | */ |
| 91 | 99 | ||