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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ia32_ATOMIC_H__ |
29 | #ifndef __ia32_ATOMIC_H__ |
30 | #define __ia32_ATOMIC_H__ |
30 | #define __ia32_ATOMIC_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | 33 | ||
34 | typedef volatile __u32 atomic_t; |
34 | typedef struct { volatile __u32 count; } atomic_t; |
- | 35 | ||
- | 36 | static inline void atomic_set(atomic_t *val, __u32 i) |
|
- | 37 | { |
|
- | 38 | val->count = i; |
|
- | 39 | } |
|
- | 40 | ||
- | 41 | static inline __u32 atomic_get(atomic_t *val) |
|
- | 42 | { |
|
- | 43 | return val->count; |
|
- | 44 | } |
|
35 | 45 | ||
36 | static inline void atomic_inc(atomic_t *val) { |
46 | static inline void atomic_inc(atomic_t *val) { |
37 | #ifdef CONFIG_SMP |
47 | #ifdef CONFIG_SMP |
38 | __asm__ volatile ("lock incl %0\n" : "=m" (*val)); |
48 | __asm__ volatile ("lock incl %0\n" : "=m" (val->count)); |
39 | #else |
49 | #else |
40 | __asm__ volatile ("incl %0\n" : "=m" (*val)); |
50 | __asm__ volatile ("incl %0\n" : "=m" (val->count)); |
41 | #endif /* CONFIG_SMP */ |
51 | #endif /* CONFIG_SMP */ |
42 | } |
52 | } |
43 | 53 | ||
44 | static inline void atomic_dec(atomic_t *val) { |
54 | static inline void atomic_dec(atomic_t *val) { |
45 | #ifdef CONFIG_SMP |
55 | #ifdef CONFIG_SMP |
46 | __asm__ volatile ("lock decl %0\n" : "=m" (*val)); |
56 | __asm__ volatile ("lock decl %0\n" : "=m" (val->count)); |
47 | #else |
57 | #else |
48 | __asm__ volatile ("decl %0\n" : "=m" (*val)); |
58 | __asm__ volatile ("decl %0\n" : "=m" (val->count)); |
49 | #endif /* CONFIG_SMP */ |
59 | #endif /* CONFIG_SMP */ |
50 | } |
60 | } |
51 | 61 | ||
52 | static inline atomic_t atomic_inc_pre(atomic_t *val) |
62 | static inline atomic_t atomic_inc_pre(atomic_t *val) |
53 | { |
63 | { |
54 | atomic_t r; |
64 | atomic_t r; |
55 | __asm__ volatile ( |
65 | __asm__ volatile ( |
56 | "movl $1, %0\n" |
66 | "movl $1, %0\n" |
57 | "lock xaddl %0, %1\n" |
67 | "lock xaddl %0, %1\n" |
58 | : "=r"(r), "=m" (*val) |
68 | : "=r"(r), "=m" (val->count) |
59 | ); |
69 | ); |
60 | return r; |
70 | return r; |
61 | } |
71 | } |
62 | 72 | ||
63 | 73 | ||
64 | 74 | ||
65 | static inline atomic_t atomic_dec_pre(atomic_t *val) |
75 | static inline atomic_t atomic_dec_pre(atomic_t *val) |
66 | { |
76 | { |
67 | atomic_t r; |
77 | atomic_t r; |
68 | __asm__ volatile ( |
78 | __asm__ volatile ( |
69 | "movl $-1, %0\n" |
79 | "movl $-1, %0\n" |
70 | "lock xaddl %0, %1\n" |
80 | "lock xaddl %0, %1\n" |
71 | : "=r"(r), "=m" (*val) |
81 | : "=r"(r), "=m" (*val) |
72 | ); |
82 | ); |
73 | return r; |
83 | return r; |
74 | } |
84 | } |
75 | 85 | ||
76 | #define atomic_inc_post(val) (atomic_inc_pre(val)+1) |
86 | #define atomic_inc_post(val) (atomic_inc_pre(val)+1) |
77 | #define atomic_dec_post(val) (atomic_dec_pre(val)-1) |
87 | #define atomic_dec_post(val) (atomic_dec_pre(val)-1) |
78 | 88 | ||
79 | static inline int test_and_set(volatile int *val) { |
89 | static inline int test_and_set(atomic_t *val) { |
80 | int v; |
90 | int v; |
81 | 91 | ||
82 | __asm__ volatile ( |
92 | __asm__ volatile ( |
83 | "movl $1, %0\n" |
93 | "movl $1, %0\n" |
84 | "xchgl %0, %1\n" |
94 | "xchgl %0, %1\n" |
85 | : "=r" (v),"=m" (*val) |
95 | : "=r" (v),"=m" (val->count) |
86 | ); |
96 | ); |
87 | 97 | ||
88 | return v; |
98 | return v; |
89 | } |
99 | } |
90 | 100 | ||
91 | 101 | ||
92 | extern void spinlock_arch(volatile int *val); |
102 | extern void spinlock_arch(volatile int *val); |
93 | 103 | ||
94 | #endif |
104 | #endif |
95 | 105 |