WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/asm.h


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern __u32 interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
 
 
 
 
extern void enable_l_apic_in_msr(void);
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
 
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Set priority level low
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_low(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Set priority level high
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_high(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        "cli\n"
        : "=r" (v)
    );
    return v;
}
 
/** Restore priority level
 *
 * Restore EFLAGS.
 */
static inline void cpu_priority_restore(pri_t pri) {
    __asm__ volatile (
        "pushl %0\n"
        "popf\n"
        : : "r" (pri)
    );
}
 
/** Return raw priority level
 *
 * Return EFLAFS.
 */
static inline pri_t cpu_priority_read(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n"
        "popl %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
static inline __u64 rdtsc(void)
{
    __u64 v;
   
    __asm__ volatile("rdtsc\n" : "=A" (v));
   
    return v;
}
 
 
#endif
 

Rev 353	Rev 356
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia32_ASM_H__	29	#ifndef __ia32_ASM_H__
30	#define __ia32_ASM_H__	30	#define __ia32_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	extern __u32 interrupt_handler_size;	35	extern __u32 interrupt_handler_size;
36		36
37	extern void paging_on(void);	37	extern void paging_on(void);
38		38
39	extern void interrupt_handlers(void);	39	extern void interrupt_handlers(void);
40		40
41	extern __u8 inb(int port);	-
42	extern __u16 inw(int port);	-
43	extern __u32 inl(int port);	-
44		-
45	extern void enable_l_apic_in_msr(void);	41	extern void enable_l_apic_in_msr(void);
46		42
47		43
48	void asm_delay_loop(__u32 t);	44	void asm_delay_loop(__u32 t);
49	void asm_fake_loop(__u32 t);	45	void asm_fake_loop(__u32 t);
50		46
51		47
52	/** Halt CPU	48	/** Halt CPU
53	*	49	*
54	* Halt the current CPU until interrupt event.	50	* Halt the current CPU until interrupt event.
55	*/	51	*/
56	static inline void cpu_halt(void) { __asm__("hlt\n"); };	52	static inline void cpu_halt(void) { __asm__("hlt\n"); };
57	static inline void cpu_sleep(void) { __asm__("hlt\n"); };	53	static inline void cpu_sleep(void) { __asm__("hlt\n"); };
58		54
59	/** Read CR2	55	/** Read CR2
60	*	56	*
61	* Return value in CR2	57	* Return value in CR2
62	*	58	*
63	* @return Value read.	59	* @return Value read.
64	*/	60	*/
65	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }	61	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
66		62
67	/** Write CR3	63	/** Write CR3
68	*	64	*
69	* Write value to CR3.	65	* Write value to CR3.
70	*	66	*
71	* @param v Value to be written.	67	* @param v Value to be written.
72	*/	68	*/
73	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }	69	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
74		70
75	/** Read CR3	71	/** Read CR3
76	*	72	*
77	* Return value in CR3	73	* Return value in CR3
78	*	74	*
79	* @return Value read.	75	* @return Value read.
80	*/	76	*/
81	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }	77	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
82		78
83	/** Byte to port	79	/** Byte to port
84	*	80	*
85	* Output byte to port	81	* Output byte to port
86	*	82	*
87	* @param port Port to write to	83	* @param port Port to write to
88	* @param val Value to write	84	* @param val Value to write
89	*/	85	*/
90	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	86	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
91		87
92	/** Word to port	88	/** Word to port
93	*	89	*
94	* Output word to port	90	* Output word to port
95	*	91	*
96	* @param port Port to write to	92	* @param port Port to write to
97	* @param val Value to write	93	* @param val Value to write
98	*/	94	*/
99	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }	95	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
100		96
101		-
102		-
103	/** Double word to port	97	/** Double word to port
104	*	98	*
105	* Output double word to port	99	* Output double word to port
106	*	100	*
107	* @param port Port to write to	101	* @param port Port to write to
108	* @param val Value to write	102	* @param val Value to write
109	*/	103	*/
110	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }	104	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
111		105
-		106	/** Byte from port
-		107	*
-		108	* Get byte from port
-		109	*
-		110	* @param port Port to read from
-		111	* @return Value read
-		112	*/
-		113	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
-		114
-		115	/** Word from port
-		116	*
-		117	* Get word from port
-		118	*
-		119	* @param port Port to read from
-		120	* @return Value read
-		121	*/
-		122	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
-		123
-		124	/** Double word from port
-		125	*
-		126	* Get double word from port
-		127	*
-		128	* @param port Port to read from
-		129	* @return Value read
-		130	*/
-		131	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
-		132
112	/** Set priority level low	133	/** Set priority level low
113	*	134	*
114	* Enable interrupts and return previous	135	* Enable interrupts and return previous
115	* value of EFLAGS.	136	* value of EFLAGS.
116	*/	137	*/
117	static inline pri_t cpu_priority_low(void) {	138	static inline pri_t cpu_priority_low(void) {
118	pri_t v;	139	pri_t v;
119	__asm__ volatile (	140	__asm__ volatile (
120	"pushf\n"	141	"pushf\n"
121	"popl %0\n"	142	"popl %0\n"
122	"sti\n"	143	"sti\n"
123	: "=r" (v)	144	: "=r" (v)
124	);	145	);
125	return v;	146	return v;
126	}	147	}
127		148
128	/** Set priority level high	149	/** Set priority level high
129	*	150	*
130	* Disable interrupts and return previous	151	* Disable interrupts and return previous
131	* value of EFLAGS.	152	* value of EFLAGS.
132	*/	153	*/
133	static inline pri_t cpu_priority_high(void) {	154	static inline pri_t cpu_priority_high(void) {
134	pri_t v;	155	pri_t v;
135	__asm__ volatile (	156	__asm__ volatile (
136	"pushf\n"	157	"pushf\n"
137	"popl %0\n"	158	"popl %0\n"
138	"cli\n"	159	"cli\n"
139	: "=r" (v)	160	: "=r" (v)
140	);	161	);
141	return v;	162	return v;
142	}	163	}
143		164
144	/** Restore priority level	165	/** Restore priority level
145	*	166	*
146	* Restore EFLAGS.	167	* Restore EFLAGS.
147	*/	168	*/
148	static inline void cpu_priority_restore(pri_t pri) {	169	static inline void cpu_priority_restore(pri_t pri) {
149	__asm__ volatile (	170	__asm__ volatile (
150	"pushl %0\n"	171	"pushl %0\n"
151	"popf\n"	172	"popf\n"
152	: : "r" (pri)	173	: : "r" (pri)
153	);	174	);
154	}	175	}
155		176
156	/** Return raw priority level	177	/** Return raw priority level
157	*	178	*
158	* Return EFLAFS.	179	* Return EFLAFS.
159	*/	180	*/
160	static inline pri_t cpu_priority_read(void) {	181	static inline pri_t cpu_priority_read(void) {
161	pri_t v;	182	pri_t v;
162	__asm__ volatile (	183	__asm__ volatile (
163	"pushf\n"	184	"pushf\n"
164	"popl %0\n"	185	"popl %0\n"
165	: "=r" (v)	186	: "=r" (v)
166	);	187	);
167	return v;	188	return v;
168	}	189	}
169		190
170	/** Return base address of current stack	191	/** Return base address of current stack
171	*	192	*
172	* Return the base address of the current stack.	193	* Return the base address of the current stack.
173	* The stack is assumed to be STACK_SIZE bytes long.	194	* The stack is assumed to be STACK_SIZE bytes long.
174	* The stack must start on page boundary.	195	* The stack must start on page boundary.
175	*/	196	*/
176	static inline __address get_stack_base(void)	197	static inline __address get_stack_base(void)
177	{	198	{
178	__address v;	199	__address v;
179		200
180	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	201	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
181		202
182	return v;	203	return v;
183	}	204	}
184		205
185	static inline __u64 rdtsc(void)	206	static inline __u64 rdtsc(void)
186	{	207	{
187	__u64 v;	208	__u64 v;
188		209
189	__asm__ volatile("rdtsc\n" : "=A" (v));	210	__asm__ volatile("rdtsc\n" : "=A" (v));
190		211
191	return v;	212	return v;
192	}	213	}
193		214
194		215
195	#endif	216	#endif
196		217

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(root)/trunk/kernel/arch/ia32/include/asm.h @ 3381 – Rev 353 → 356