WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/asm.h


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
extern __u32 interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
extern void enable_l_apic_in_msr(void);
 
 
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
 
/** Read CR2
 *
 * Return value in CR2
 *
 * @return Value read.
 */
static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
 
/** Write CR3
 *
 * Write value to CR3.
 *
 * @param v Value to be written.
 */
static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
 *
 * Return value in CR3
 *
 * @return Value read.
 */
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Set priority level low
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_low(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Set priority level high
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 */
static inline pri_t cpu_priority_high(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "cli\n"
        : "=r" (v)
    );
    return v;
}
 
/** Restore priority level
 *
 * Restore EFLAGS.
 */
static inline void cpu_priority_restore(pri_t pri) {
    __asm__ volatile (
        "pushl %0\n\t"
        "popf\n"
        : : "r" (pri)
    );
}
 
/** Return raw priority level
 *
 * Return EFLAFS.
 */
static inline pri_t cpu_priority_read(void) {
    pri_t v;
    __asm__ volatile (
        "pushf\n\t"
        "popl %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
static inline __u64 rdtsc(void)
{
    __u64 v;
   
    __asm__ volatile("rdtsc\n" : "=A" (v));
   
    return v;
}
 
#endif
 

Rev 361	Rev 363
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* Copyright (C) 2005 HelenOS project	-
4	* All rights reserved.	3	* All rights reserved.
5	*	4	*
6	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
8	* are met:	7	* are met:
9	*	8	*
10	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
17	*	16	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	27	*/
29		28
30	#ifndef __ia32_ASM_H__	29	#ifndef __ia32_ASM_H__
31	#define __ia32_ASM_H__	30	#define __ia32_ASM_H__
32		31
33	#include <arch/types.h>	32	#include <arch/types.h>
34	#include <config.h>	33	#include <config.h>
35		34
36	extern __u32 interrupt_handler_size;	35	extern __u32 interrupt_handler_size;
37		36
38	extern void paging_on(void);	37	extern void paging_on(void);
39		38
40	extern void interrupt_handlers(void);	39	extern void interrupt_handlers(void);
41		40
42	extern void enable_l_apic_in_msr(void);	41	extern void enable_l_apic_in_msr(void);
43		42
44		43
45	void asm_delay_loop(__u32 t);	44	void asm_delay_loop(__u32 t);
46	void asm_fake_loop(__u32 t);	45	void asm_fake_loop(__u32 t);
47		46
48		47
49	/** Halt CPU	48	/** Halt CPU
50	*	49	*
51	* Halt the current CPU until interrupt event.	50	* Halt the current CPU until interrupt event.
52	*/	51	*/
53	static inline void cpu_halt(void) { __asm__("hlt\n"); };	52	static inline void cpu_halt(void) { __asm__("hlt\n"); };
54	static inline void cpu_sleep(void) { __asm__("hlt\n"); };	53	static inline void cpu_sleep(void) { __asm__("hlt\n"); };
55		54
56	/** Read CR2	55	/** Read CR2
57	*	56	*
58	* Return value in CR2	57	* Return value in CR2
59	*	58	*
60	* @return Value read.	59	* @return Value read.
61	*/	60	*/
62	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }	61	static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
63		62
64	/** Write CR3	63	/** Write CR3
65	*	64	*
66	* Write value to CR3.	65	* Write value to CR3.
67	*	66	*
68	* @param v Value to be written.	67	* @param v Value to be written.
69	*/	68	*/
70	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }	69	static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
71		70
72	/** Read CR3	71	/** Read CR3
73	*	72	*
74	* Return value in CR3	73	* Return value in CR3
75	*	74	*
76	* @return Value read.	75	* @return Value read.
77	*/	76	*/
78	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }	77	static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
79		78
80	/** Byte to port	79	/** Byte to port
81	*	80	*
82	* Output byte to port	81	* Output byte to port
83	*	82	*
84	* @param port Port to write to	83	* @param port Port to write to
85	* @param val Value to write	84	* @param val Value to write
86	*/	85	*/
87	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	86	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
88		87
89	/** Word to port	88	/** Word to port
90	*	89	*
91	* Output word to port	90	* Output word to port
92	*	91	*
93	* @param port Port to write to	92	* @param port Port to write to
94	* @param val Value to write	93	* @param val Value to write
95	*/	94	*/
96	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }	95	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
97		96
98	/** Double word to port	97	/** Double word to port
99	*	98	*
100	* Output double word to port	99	* Output double word to port
101	*	100	*
102	* @param port Port to write to	101	* @param port Port to write to
103	* @param val Value to write	102	* @param val Value to write
104	*/	103	*/
105	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }	104	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
106		105
107	/** Byte from port	106	/** Byte from port
108	*	107	*
109	* Get byte from port	108	* Get byte from port
110	*	109	*
111	* @param port Port to read from	110	* @param port Port to read from
112	* @return Value read	111	* @return Value read
113	*/	112	*/
114	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	113	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
115		114
116	/** Word from port	115	/** Word from port
117	*	116	*
118	* Get word from port	117	* Get word from port
119	*	118	*
120	* @param port Port to read from	119	* @param port Port to read from
121	* @return Value read	120	* @return Value read
122	*/	121	*/
123	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }	122	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
124		123
125	/** Double word from port	124	/** Double word from port
126	*	125	*
127	* Get double word from port	126	* Get double word from port
128	*	127	*
129	* @param port Port to read from	128	* @param port Port to read from
130	* @return Value read	129	* @return Value read
131	*/	130	*/
132	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }	131	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
133		132
134	/** Set priority level low	133	/** Set priority level low
135	*	134	*
136	* Enable interrupts and return previous	135	* Enable interrupts and return previous
137	* value of EFLAGS.	136	* value of EFLAGS.
138	*/	137	*/
139	static inline pri_t cpu_priority_low(void) {	138	static inline pri_t cpu_priority_low(void) {
140	pri_t v;	139	pri_t v;
141	__asm__ volatile (	140	__asm__ volatile (
142	"pushf\n\t"	141	"pushf\n\t"
143	"popl %0\n\t"	142	"popl %0\n\t"
144	"sti\n"	143	"sti\n"
145	: "=r" (v)	144	: "=r" (v)
146	);	145	);
147	return v;	146	return v;
148	}	147	}
149		148
150	/** Set priority level high	149	/** Set priority level high
151	*	150	*
152	* Disable interrupts and return previous	151	* Disable interrupts and return previous
153	* value of EFLAGS.	152	* value of EFLAGS.
154	*/	153	*/
155	static inline pri_t cpu_priority_high(void) {	154	static inline pri_t cpu_priority_high(void) {
156	pri_t v;	155	pri_t v;
157	__asm__ volatile (	156	__asm__ volatile (
158	"pushf\n\t"	157	"pushf\n\t"
159	"popl %0\n\t"	158	"popl %0\n\t"
160	"cli\n"	159	"cli\n"
161	: "=r" (v)	160	: "=r" (v)
162	);	161	);
163	return v;	162	return v;
164	}	163	}
165		164
166	/** Restore priority level	165	/** Restore priority level
167	*	166	*
168	* Restore EFLAGS.	167	* Restore EFLAGS.
169	*/	168	*/
170	static inline void cpu_priority_restore(pri_t pri) {	169	static inline void cpu_priority_restore(pri_t pri) {
171	__asm__ volatile (	170	__asm__ volatile (
172	"pushl %0\n\t"	171	"pushl %0\n\t"
173	"popf\n"	172	"popf\n"
174	: : "r" (pri)	173	: : "r" (pri)
175	);	174	);
176	}	175	}
177		176
178	/** Return raw priority level	177	/** Return raw priority level
179	*	178	*
180	* Return EFLAFS.	179	* Return EFLAFS.
181	*/	180	*/
182	static inline pri_t cpu_priority_read(void) {	181	static inline pri_t cpu_priority_read(void) {
183	pri_t v;	182	pri_t v;
184	__asm__ volatile (	183	__asm__ volatile (
185	"pushf\n\t"	184	"pushf\n\t"
186	"popl %0\n"	185	"popl %0\n"
187	: "=r" (v)	186	: "=r" (v)
188	);	187	);
189	return v;	188	return v;
190	}	189	}
191		190
192	/** Return base address of current stack	191	/** Return base address of current stack
193	*	192	*
194	* Return the base address of the current stack.	193	* Return the base address of the current stack.
195	* The stack is assumed to be STACK_SIZE bytes long.	194	* The stack is assumed to be STACK_SIZE bytes long.
196	* The stack must start on page boundary.	195	* The stack must start on page boundary.
197	*/	196	*/
198	static inline __address get_stack_base(void)	197	static inline __address get_stack_base(void)
199	{	198	{
200	__address v;	199	__address v;
201		200
202	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	201	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
203		202
204	return v;	203	return v;
205	}	204	}
206		205
207	static inline __u64 rdtsc(void)	206	static inline __u64 rdtsc(void)
208	{	207	{
209	__u64 v;	208	__u64 v;
210		209
211	__asm__ volatile("rdtsc\n" : "=A" (v));	210	__asm__ volatile("rdtsc\n" : "=A" (v));
212		211
213	return v;	212	return v;
214	}	213	}
215		214
216	#endif	215	#endif
217		216

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(root)/trunk/kernel/arch/ia32/include/asm.h @ 2697 – Rev 361 → 363