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1 | /* |
1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
3 | * Copyright (c) 2005 Sergey Bondari |
3 | * Copyright (c) 2005 Sergey Bondari |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup ia32 |
30 | /** @addtogroup ia32 |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef KERN_ia32_ASM_H_ |
36 | #ifndef KERN_ia32_ASM_H_ |
37 | #define KERN_ia32_ASM_H_ |
37 | #define KERN_ia32_ASM_H_ |
38 | 38 | ||
39 | #include <arch/pm.h> |
39 | #include <arch/pm.h> |
40 | #include <arch/types.h> |
40 | #include <arch/types.h> |
41 | #include <config.h> |
41 | #include <config.h> |
42 | 42 | ||
43 | extern uint32_t interrupt_handler_size; |
43 | extern uint32_t interrupt_handler_size; |
44 | 44 | ||
45 | extern void paging_on(void); |
45 | extern void paging_on(void); |
46 | 46 | ||
47 | extern void interrupt_handlers(void); |
47 | extern void interrupt_handlers(void); |
48 | 48 | ||
49 | extern void enable_l_apic_in_msr(void); |
49 | extern void enable_l_apic_in_msr(void); |
50 | 50 | ||
51 | 51 | ||
52 | extern void asm_delay_loop(uint32_t t); |
52 | extern void asm_delay_loop(uint32_t t); |
53 | extern void asm_fake_loop(uint32_t t); |
53 | extern void asm_fake_loop(uint32_t t); |
54 | 54 | ||
55 | 55 | ||
56 | /** Halt CPU |
56 | /** Halt CPU |
57 | * |
57 | * |
58 | * Halt the current CPU until interrupt event. |
58 | * Halt the current CPU until interrupt event. |
59 | */ |
59 | */ |
60 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
60 | static inline void cpu_halt(void) |
- | 61 | { |
|
- | 62 | asm("hlt\n"); |
|
- | 63 | }; |
|
- | 64 | ||
61 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
65 | static inline void cpu_sleep(void) |
- | 66 | { |
|
- | 67 | asm("hlt\n"); |
|
- | 68 | }; |
|
62 | 69 | ||
63 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
70 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
64 | { \ |
71 | { \ |
65 | unative_t res; \ |
72 | unative_t res; \ |
66 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
73 | asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
67 | return res; \ |
74 | return res; \ |
68 | } |
75 | } |
69 | 76 | ||
70 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
77 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
71 | { \ |
78 | { \ |
72 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
79 | asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
73 | } |
80 | } |
74 | 81 | ||
75 | GEN_READ_REG(cr0); |
82 | GEN_READ_REG(cr0); |
76 | GEN_READ_REG(cr2); |
83 | GEN_READ_REG(cr2); |
77 | GEN_READ_REG(cr3); |
84 | GEN_READ_REG(cr3); |
78 | GEN_WRITE_REG(cr3); |
85 | GEN_WRITE_REG(cr3); |
79 | 86 | ||
80 | GEN_READ_REG(dr0); |
87 | GEN_READ_REG(dr0); |
81 | GEN_READ_REG(dr1); |
88 | GEN_READ_REG(dr1); |
82 | GEN_READ_REG(dr2); |
89 | GEN_READ_REG(dr2); |
83 | GEN_READ_REG(dr3); |
90 | GEN_READ_REG(dr3); |
84 | GEN_READ_REG(dr6); |
91 | GEN_READ_REG(dr6); |
85 | GEN_READ_REG(dr7); |
92 | GEN_READ_REG(dr7); |
86 | 93 | ||
87 | GEN_WRITE_REG(dr0); |
94 | GEN_WRITE_REG(dr0); |
88 | GEN_WRITE_REG(dr1); |
95 | GEN_WRITE_REG(dr1); |
89 | GEN_WRITE_REG(dr2); |
96 | GEN_WRITE_REG(dr2); |
90 | GEN_WRITE_REG(dr3); |
97 | GEN_WRITE_REG(dr3); |
91 | GEN_WRITE_REG(dr6); |
98 | GEN_WRITE_REG(dr6); |
92 | GEN_WRITE_REG(dr7); |
99 | GEN_WRITE_REG(dr7); |
93 | 100 | ||
94 | /** Byte to port |
101 | /** Byte to port |
95 | * |
102 | * |
96 | * Output byte to port |
103 | * Output byte to port |
97 | * |
104 | * |
98 | * @param port Port to write to |
105 | * @param port Port to write to |
99 | * @param val Value to write |
106 | * @param val Value to write |
100 | */ |
107 | */ |
- | 108 | static inline void outb(uint16_t port, uint8_t val) |
|
- | 109 | { |
|
101 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
110 | asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); |
- | 111 | } |
|
102 | 112 | ||
103 | /** Word to port |
113 | /** Word to port |
104 | * |
114 | * |
105 | * Output word to port |
115 | * Output word to port |
106 | * |
116 | * |
107 | * @param port Port to write to |
117 | * @param port Port to write to |
108 | * @param val Value to write |
118 | * @param val Value to write |
109 | */ |
119 | */ |
- | 120 | static inline void outw(uint16_t port, uint16_t val) |
|
- | 121 | { |
|
110 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
122 | asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); |
- | 123 | } |
|
111 | 124 | ||
112 | /** Double word to port |
125 | /** Double word to port |
113 | * |
126 | * |
114 | * Output double word to port |
127 | * Output double word to port |
115 | * |
128 | * |
116 | * @param port Port to write to |
129 | * @param port Port to write to |
117 | * @param val Value to write |
130 | * @param val Value to write |
118 | */ |
131 | */ |
- | 132 | static inline void outl(uint16_t port, uint32_t val) |
|
- | 133 | { |
|
119 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
134 | asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); |
- | 135 | } |
|
120 | 136 | ||
121 | /** Byte from port |
137 | /** Byte from port |
122 | * |
138 | * |
123 | * Get byte from port |
139 | * Get byte from port |
124 | * |
140 | * |
125 | * @param port Port to read from |
141 | * @param port Port to read from |
126 | * @return Value read |
142 | * @return Value read |
127 | */ |
143 | */ |
- | 144 | static inline uint8_t inb(uint16_t port) |
|
- | 145 | { |
|
- | 146 | uint8_t val; |
|
- | 147 | ||
128 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
148 | asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); |
- | 149 | return val; |
|
- | 150 | } |
|
129 | 151 | ||
130 | /** Word from port |
152 | /** Word from port |
131 | * |
153 | * |
132 | * Get word from port |
154 | * Get word from port |
133 | * |
155 | * |
134 | * @param port Port to read from |
156 | * @param port Port to read from |
135 | * @return Value read |
157 | * @return Value read |
136 | */ |
158 | */ |
- | 159 | static inline uint16_t inw(uint16_t port) |
|
- | 160 | { |
|
- | 161 | uint16_t val; |
|
- | 162 | ||
137 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
163 | asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); |
- | 164 | return val; |
|
- | 165 | } |
|
138 | 166 | ||
139 | /** Double word from port |
167 | /** Double word from port |
140 | * |
168 | * |
141 | * Get double word from port |
169 | * Get double word from port |
142 | * |
170 | * |
143 | * @param port Port to read from |
171 | * @param port Port to read from |
144 | * @return Value read |
172 | * @return Value read |
145 | */ |
173 | */ |
- | 174 | static inline uint32_t inl(uint16_t port) |
|
- | 175 | { |
|
- | 176 | uint32_t val; |
|
- | 177 | ||
146 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
178 | asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); |
- | 179 | return val; |
|
- | 180 | } |
|
147 | 181 | ||
148 | /** Enable interrupts. |
182 | /** Enable interrupts. |
149 | * |
183 | * |
150 | * Enable interrupts and return previous |
184 | * Enable interrupts and return previous |
151 | * value of EFLAGS. |
185 | * value of EFLAGS. |
152 | * |
186 | * |
153 | * @return Old interrupt priority level. |
187 | * @return Old interrupt priority level. |
154 | */ |
188 | */ |
155 | static inline ipl_t interrupts_enable(void) |
189 | static inline ipl_t interrupts_enable(void) |
156 | { |
190 | { |
157 | ipl_t v; |
191 | ipl_t v; |
158 | __asm__ volatile ( |
192 | asm volatile ( |
159 | "pushf\n\t" |
193 | "pushf\n\t" |
160 | "popl %0\n\t" |
194 | "popl %0\n\t" |
161 | "sti\n" |
195 | "sti\n" |
162 | : "=r" (v) |
196 | : "=r" (v) |
163 | ); |
197 | ); |
164 | return v; |
198 | return v; |
165 | } |
199 | } |
166 | 200 | ||
167 | /** Disable interrupts. |
201 | /** Disable interrupts. |
168 | * |
202 | * |
169 | * Disable interrupts and return previous |
203 | * Disable interrupts and return previous |
170 | * value of EFLAGS. |
204 | * value of EFLAGS. |
171 | * |
205 | * |
172 | * @return Old interrupt priority level. |
206 | * @return Old interrupt priority level. |
173 | */ |
207 | */ |
174 | static inline ipl_t interrupts_disable(void) |
208 | static inline ipl_t interrupts_disable(void) |
175 | { |
209 | { |
176 | ipl_t v; |
210 | ipl_t v; |
177 | __asm__ volatile ( |
211 | asm volatile ( |
178 | "pushf\n\t" |
212 | "pushf\n\t" |
179 | "popl %0\n\t" |
213 | "popl %0\n\t" |
180 | "cli\n" |
214 | "cli\n" |
181 | : "=r" (v) |
215 | : "=r" (v) |
182 | ); |
216 | ); |
183 | return v; |
217 | return v; |
184 | } |
218 | } |
185 | 219 | ||
186 | /** Restore interrupt priority level. |
220 | /** Restore interrupt priority level. |
187 | * |
221 | * |
188 | * Restore EFLAGS. |
222 | * Restore EFLAGS. |
189 | * |
223 | * |
190 | * @param ipl Saved interrupt priority level. |
224 | * @param ipl Saved interrupt priority level. |
191 | */ |
225 | */ |
192 | static inline void interrupts_restore(ipl_t ipl) |
226 | static inline void interrupts_restore(ipl_t ipl) |
193 | { |
227 | { |
194 | __asm__ volatile ( |
228 | asm volatile ( |
195 | "pushl %0\n\t" |
229 | "pushl %0\n\t" |
196 | "popf\n" |
230 | "popf\n" |
197 | : : "r" (ipl) |
231 | : : "r" (ipl) |
198 | ); |
232 | ); |
199 | } |
233 | } |
200 | 234 | ||
201 | /** Return interrupt priority level. |
235 | /** Return interrupt priority level. |
202 | * |
236 | * |
203 | * @return EFLAFS. |
237 | * @return EFLAFS. |
204 | */ |
238 | */ |
205 | static inline ipl_t interrupts_read(void) |
239 | static inline ipl_t interrupts_read(void) |
206 | { |
240 | { |
207 | ipl_t v; |
241 | ipl_t v; |
208 | __asm__ volatile ( |
242 | asm volatile ( |
209 | "pushf\n\t" |
243 | "pushf\n\t" |
210 | "popl %0\n" |
244 | "popl %0\n" |
211 | : "=r" (v) |
245 | : "=r" (v) |
212 | ); |
246 | ); |
213 | return v; |
247 | return v; |
214 | } |
248 | } |
215 | 249 | ||
216 | /** Return base address of current stack |
250 | /** Return base address of current stack |
217 | * |
251 | * |
218 | * Return the base address of the current stack. |
252 | * Return the base address of the current stack. |
219 | * The stack is assumed to be STACK_SIZE bytes long. |
253 | * The stack is assumed to be STACK_SIZE bytes long. |
220 | * The stack must start on page boundary. |
254 | * The stack must start on page boundary. |
221 | */ |
255 | */ |
222 | static inline uintptr_t get_stack_base(void) |
256 | static inline uintptr_t get_stack_base(void) |
223 | { |
257 | { |
224 | uintptr_t v; |
258 | uintptr_t v; |
225 | 259 | ||
226 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
260 | asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
227 | 261 | ||
228 | return v; |
262 | return v; |
229 | } |
263 | } |
230 | 264 | ||
231 | /** Return current IP address */ |
265 | /** Return current IP address */ |
232 | static inline uintptr_t * get_ip() |
266 | static inline uintptr_t * get_ip() |
233 | { |
267 | { |
234 | uintptr_t *ip; |
268 | uintptr_t *ip; |
235 | 269 | ||
236 | __asm__ volatile ( |
270 | asm volatile ( |
237 | "mov %%eip, %0" |
271 | "mov %%eip, %0" |
238 | : "=r" (ip) |
272 | : "=r" (ip) |
239 | ); |
273 | ); |
240 | return ip; |
274 | return ip; |
241 | } |
275 | } |
242 | 276 | ||
243 | /** Invalidate TLB Entry. |
277 | /** Invalidate TLB Entry. |
244 | * |
278 | * |
245 | * @param addr Address on a page whose TLB entry is to be invalidated. |
279 | * @param addr Address on a page whose TLB entry is to be invalidated. |
246 | */ |
280 | */ |
247 | static inline void invlpg(uintptr_t addr) |
281 | static inline void invlpg(uintptr_t addr) |
248 | { |
282 | { |
249 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
283 | asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
250 | } |
284 | } |
251 | 285 | ||
252 | /** Load GDTR register from memory. |
286 | /** Load GDTR register from memory. |
253 | * |
287 | * |
254 | * @param gdtr_reg Address of memory from where to load GDTR. |
288 | * @param gdtr_reg Address of memory from where to load GDTR. |
255 | */ |
289 | */ |
256 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
290 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
257 | { |
291 | { |
258 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
292 | asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
259 | } |
293 | } |
260 | 294 | ||
261 | /** Store GDTR register to memory. |
295 | /** Store GDTR register to memory. |
262 | * |
296 | * |
263 | * @param gdtr_reg Address of memory to where to load GDTR. |
297 | * @param gdtr_reg Address of memory to where to load GDTR. |
264 | */ |
298 | */ |
265 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
299 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
266 | { |
300 | { |
267 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
301 | asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
268 | } |
302 | } |
269 | 303 | ||
270 | /** Load IDTR register from memory. |
304 | /** Load IDTR register from memory. |
271 | * |
305 | * |
272 | * @param idtr_reg Address of memory from where to load IDTR. |
306 | * @param idtr_reg Address of memory from where to load IDTR. |
273 | */ |
307 | */ |
274 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
308 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
275 | { |
309 | { |
276 | __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
310 | asm volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
277 | } |
311 | } |
278 | 312 | ||
279 | /** Load TR from descriptor table. |
313 | /** Load TR from descriptor table. |
280 | * |
314 | * |
281 | * @param sel Selector specifying descriptor of TSS segment. |
315 | * @param sel Selector specifying descriptor of TSS segment. |
282 | */ |
316 | */ |
283 | static inline void tr_load(uint16_t sel) |
317 | static inline void tr_load(uint16_t sel) |
284 | { |
318 | { |
285 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
319 | asm volatile ("ltr %0" : : "r" (sel)); |
286 | } |
320 | } |
287 | 321 | ||
288 | #endif |
322 | #endif |
289 | 323 | ||
290 | /** @} |
324 | /** @} |
291 | */ |
325 | */ |
292 | 326 |