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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Page fault related functions. |
33 | * @brief Page fault related functions. |
34 | */ |
34 | */ |
35 | #include <panic.h> |
35 | #include <panic.h> |
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug/print.h> |
37 | #include <arch/debug/print.h> |
38 | #include <arch/mm/page_fault.h> |
38 | #include <arch/mm/page_fault.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <genarch/mm/page_pt.h> |
40 | #include <genarch/mm/page_pt.h> |
41 | #include <arch.h> |
41 | #include <arch.h> |
42 | #include <interrupt.h> |
42 | #include <interrupt.h> |
43 | #include <print.h> |
43 | #include <print.h> |
44 | 44 | ||
45 | /** Returns value stored in fault status register. |
45 | /** Returns value stored in fault status register. |
46 | * |
46 | * |
47 | * @return Value stored in CP15 fault status register (FSR). |
47 | * @return Value stored in CP15 fault status register (FSR). |
48 | */ |
48 | */ |
49 | static inline fault_status_t read_fault_status_register(void) |
49 | static inline fault_status_t read_fault_status_register(void) |
50 | { |
50 | { |
51 | fault_status_union_t fsu; |
51 | fault_status_union_t fsu; |
52 | 52 | ||
53 | /* fault status is stored in CP15 register 5 */ |
53 | /* fault status is stored in CP15 register 5 */ |
54 | asm volatile ( |
54 | asm volatile ( |
55 | "mrc p15, 0, %0, c5, c0, 0" |
55 | "mrc p15, 0, %0, c5, c0, 0" |
56 | : "=r"(fsu.dummy) |
56 | : "=r"(fsu.dummy) |
57 | ); |
57 | ); |
58 | return fsu.fs; |
58 | return fsu.fs; |
59 | } |
59 | } |
60 | 60 | ||
61 | /** Returns FAR (fault address register) content. |
61 | /** Returns FAR (fault address register) content. |
62 | * |
62 | * |
63 | * @return FAR (fault address register) content (address that caused a page |
63 | * @return FAR (fault address register) content (address that caused a page |
64 | * fault) |
64 | * fault) |
65 | */ |
65 | */ |
66 | static inline uintptr_t read_fault_address_register(void) |
66 | static inline uintptr_t read_fault_address_register(void) |
67 | { |
67 | { |
68 | uintptr_t ret; |
68 | uintptr_t ret; |
69 | 69 | ||
70 | /* fault adress is stored in CP15 register 6 */ |
70 | /* fault adress is stored in CP15 register 6 */ |
71 | asm volatile ( |
71 | asm volatile ( |
72 | "mrc p15, 0, %0, c6, c0, 0" |
72 | "mrc p15, 0, %0, c6, c0, 0" |
73 | : "=r"(ret) |
73 | : "=r"(ret) |
74 | ); |
74 | ); |
75 | return ret; |
75 | return ret; |
76 | } |
76 | } |
77 | 77 | ||
78 | /** Decides whether the instruction is load/store or not. |
78 | /** Decides whether the instruction is load/store or not. |
79 | * |
79 | * |
80 | * @param instr Instruction |
80 | * @param instr Instruction |
81 | * |
81 | * |
82 | * @return true when instruction is load/store, false otherwise |
82 | * @return true when instruction is load/store, false otherwise |
83 | */ |
83 | */ |
84 | static inline bool is_load_store_instruction(instruction_t instr) |
84 | static inline bool is_load_store_instruction(instruction_t instr) |
85 | { |
85 | { |
86 | /* load store immediate offset */ |
86 | /* load store immediate offset */ |
87 | if (instr.type == 0x2) { |
87 | if (instr.type == 0x2) { |
88 | return true; |
88 | return true; |
89 | } |
89 | } |
90 | 90 | ||
91 | /* load store register offset */ |
91 | /* load store register offset */ |
92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
93 | return true; |
93 | return true; |
94 | } |
94 | } |
95 | 95 | ||
96 | /* load store multiple */ |
96 | /* load store multiple */ |
97 | if (instr.type == 0x4) { |
97 | if (instr.type == 0x4) { |
98 | return true; |
98 | return true; |
99 | } |
99 | } |
100 | 100 | ||
101 | /* oprocessor load/store */ |
101 | /* oprocessor load/store */ |
102 | if (instr.type == 0x6) { |
102 | if (instr.type == 0x6) { |
103 | return true; |
103 | return true; |
104 | } |
104 | } |
105 | 105 | ||
106 | return false; |
106 | return false; |
107 | } |
107 | } |
108 | 108 | ||
109 | /** Decides whether the instruction is swap or not. |
109 | /** Decides whether the instruction is swap or not. |
110 | * |
110 | * |
111 | * @param instr Instruction |
111 | * @param instr Instruction |
112 | * |
112 | * |
113 | * @return true when instruction is swap, false otherwise |
113 | * @return true when instruction is swap, false otherwise |
114 | */ |
114 | */ |
115 | static inline bool is_swap_instruction(instruction_t instr) |
115 | static inline bool is_swap_instruction(instruction_t instr) |
116 | { |
116 | { |
117 | /* swap, swapb instruction */ |
117 | /* swap, swapb instruction */ |
118 | if (instr.type == 0x0 && |
118 | if (instr.type == 0x0 && |
119 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
119 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
120 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
120 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
121 | return true; |
121 | return true; |
122 | } |
122 | } |
123 | 123 | ||
124 | return false; |
124 | return false; |
125 | } |
125 | } |
126 | 126 | ||
127 | /** Decides whether read or write into memory is requested. |
127 | /** Decides whether read or write into memory is requested. |
128 | * |
128 | * |
129 | * @param instr_addr Address of instruction which tries to access memory. |
129 | * @param instr_addr Address of instruction which tries to access memory. |
130 | * @param badvaddr Virtual address the instruction tries to access. |
130 | * @param badvaddr Virtual address the instruction tries to access. |
131 | * |
131 | * |
132 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
132 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
133 | * requested. |
133 | * requested. |
134 | */ |
134 | */ |
135 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
135 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
136 | uintptr_t badvaddr) |
136 | uintptr_t badvaddr) |
137 | { |
137 | { |
138 | instruction_union_t instr_union; |
138 | instruction_union_t instr_union; |
139 | instr_union.pc = instr_addr; |
139 | instr_union.pc = instr_addr; |
140 | 140 | ||
141 | instruction_t instr = *(instr_union.instr); |
141 | instruction_t instr = *(instr_union.instr); |
142 | 142 | ||
143 | /* undefined instructions */ |
143 | /* undefined instructions */ |
144 | if (instr.condition == 0xf) { |
144 | if (instr.condition == 0xf) { |
145 | panic("page_fault - instruction doesn't access memory " |
145 | panic("page_fault - instruction does not access memory " |
146 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
146 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
147 | return PF_ACCESS_EXEC; |
147 | return PF_ACCESS_EXEC; |
148 | } |
148 | } |
149 | 149 | ||
150 | /* load store instructions */ |
150 | /* load store instructions */ |
151 | if (is_load_store_instruction(instr)) { |
151 | if (is_load_store_instruction(instr)) { |
152 | if (instr.access == 1) { |
152 | if (instr.access == 1) { |
153 | return PF_ACCESS_READ; |
153 | return PF_ACCESS_READ; |
154 | } else { |
154 | } else { |
155 | return PF_ACCESS_WRITE; |
155 | return PF_ACCESS_WRITE; |
156 | } |
156 | } |
157 | } |
157 | } |
158 | 158 | ||
159 | /* swap, swpb instruction */ |
159 | /* swap, swpb instruction */ |
160 | if (is_swap_instruction(instr)) { |
160 | if (is_swap_instruction(instr)) { |
161 | return PF_ACCESS_WRITE; |
161 | return PF_ACCESS_WRITE; |
162 | } |
162 | } |
163 | 163 | ||
164 | panic("page_fault - instruction doesn't access memory " |
164 | panic("page_fault - instruction doesn't access memory " |
165 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
165 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
166 | 166 | ||
167 | return PF_ACCESS_EXEC; |
167 | return PF_ACCESS_EXEC; |
168 | } |
168 | } |
169 | 169 | ||
170 | /** Handles "data abort" exception (load or store at invalid address). |
170 | /** Handles "data abort" exception (load or store at invalid address). |
171 | * |
171 | * |
172 | * @param exc_no Exception number. |
172 | * @param exc_no Exception number. |
173 | * @param istate CPU state when exception occured. |
173 | * @param istate CPU state when exception occured. |
174 | */ |
174 | */ |
175 | void data_abort(int exc_no, istate_t *istate) |
175 | void data_abort(int exc_no, istate_t *istate) |
176 | { |
176 | { |
177 | fault_status_t fsr __attribute__ ((unused)) = |
177 | fault_status_t fsr __attribute__ ((unused)) = |
178 | read_fault_status_register(); |
178 | read_fault_status_register(); |
179 | uintptr_t badvaddr = read_fault_address_register(); |
179 | uintptr_t badvaddr = read_fault_address_register(); |
180 | 180 | ||
181 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
181 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
182 | 182 | ||
183 | int ret = as_page_fault(badvaddr, access, istate); |
183 | int ret = as_page_fault(badvaddr, access, istate); |
184 | 184 | ||
185 | if (ret == AS_PF_FAULT) { |
185 | if (ret == AS_PF_FAULT) { |
186 | print_istate(istate); |
186 | print_istate(istate); |
187 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
187 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
188 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
188 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
189 | access); |
189 | access); |
190 | 190 | ||
191 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
191 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
192 | panic("Page fault\n"); |
192 | panic("Page fault."); |
193 | } |
193 | } |
194 | } |
194 | } |
195 | 195 | ||
196 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
196 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
197 | * |
197 | * |
198 | * @param exc_no Exception number. |
198 | * @param exc_no Exception number. |
199 | * @param istate CPU state when exception occured. |
199 | * @param istate CPU state when exception occured. |
200 | */ |
200 | */ |
201 | void prefetch_abort(int exc_no, istate_t *istate) |
201 | void prefetch_abort(int exc_no, istate_t *istate) |
202 | { |
202 | { |
203 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
203 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
204 | 204 | ||
205 | if (ret == AS_PF_FAULT) { |
205 | if (ret == AS_PF_FAULT) { |
206 | dprintf("prefetch_abort\n"); |
206 | dprintf("prefetch_abort\n"); |
207 | print_istate(istate); |
207 | print_istate(istate); |
208 | panic("page fault - prefetch_abort at address: %x\n", |
208 | panic("page fault - prefetch_abort at address: %x.", |
209 | istate->pc); |
209 | istate->pc); |
210 | } |
210 | } |
211 | } |
211 | } |
212 | 212 | ||
213 | /** @} |
213 | /** @} |
214 | */ |
214 | */ |
215 | 215 |