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/*
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/*
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 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
7
 * are met:
8
 *
8
 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup arm32mm
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/** @addtogroup arm32mm
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 *  @brief Page fault related functions.
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 *  @brief Page fault related functions.
34
 */
34
 */
35
#include <panic.h>
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#include <panic.h>
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#include <arch/exception.h>
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#include <arch/exception.h>
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#include <arch/debug/print.h>
37
#include <arch/debug/print.h>
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#include <arch/mm/page_fault.h>
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#include <arch/mm/page_fault.h>
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#include <mm/as.h>
39
#include <mm/as.h>
40
#include <genarch/mm/page_pt.h>
40
#include <genarch/mm/page_pt.h>
41
#include <arch.h>
41
#include <arch.h>
42
#include <interrupt.h>
42
#include <interrupt.h>
43
#include <print.h>
43
#include <print.h>
44
 
44
 
45
/** Returns value stored in fault status register.
45
/** Returns value stored in fault status register.
46
 *
46
 *
47
 *  @return Value stored in CP15 fault status register (FSR).
47
 *  @return Value stored in CP15 fault status register (FSR).
48
 */
48
 */
49
static inline fault_status_t read_fault_status_register(void)
49
static inline fault_status_t read_fault_status_register(void)
50
{
50
{
51
    fault_status_union_t fsu;
51
    fault_status_union_t fsu;
52
 
52
   
53
    /* fault status is stored in CP15 register 5 */
53
    /* fault status is stored in CP15 register 5 */
54
    asm volatile (
54
    asm volatile (
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        "mrc p15, 0, %0, c5, c0, 0"
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        "mrc p15, 0, %[dummy], c5, c0, 0"
56
        : "=r"(fsu.dummy)
56
        : [dummy] "=r" (fsu.dummy)
57
    );
57
    );
-
 
58
   
58
    return fsu.fs;
59
    return fsu.fs;
59
}
60
}
60
 
61
 
61
/** Returns FAR (fault address register) content.
62
/** Returns FAR (fault address register) content.
62
 *
63
 *
63
 * @return FAR (fault address register) content (address that caused a page
64
 * @return FAR (fault address register) content (address that caused a page
64
 *     fault)
65
 *         fault)
65
 */
66
 */
66
static inline uintptr_t read_fault_address_register(void)
67
static inline uintptr_t read_fault_address_register(void)
67
{
68
{
68
    uintptr_t ret;
69
    uintptr_t ret;
69
 
70
   
70
    /* fault adress is stored in CP15 register 6 */
71
    /* fault adress is stored in CP15 register 6 */
71
    asm volatile (
72
    asm volatile (
72
        "mrc p15, 0, %0, c6, c0, 0"
73
        "mrc p15, 0, %[ret], c6, c0, 0"
73
        : "=r"(ret)
74
        : [ret] "=r" (ret)
74
    );
75
    );
-
 
76
   
75
    return ret;
77
    return ret;
76
}
78
}
77
 
79
 
78
/** Decides whether the instruction is load/store or not.
80
/** Decides whether the instruction is load/store or not.
79
 *
81
 *
80
 * @param instr Instruction
82
 * @param instr Instruction
81
 *
83
 *
82
 * @return true when instruction is load/store, false otherwise
84
 * @return true when instruction is load/store, false otherwise
-
 
85
 *
83
 */
86
 */
84
static inline bool is_load_store_instruction(instruction_t instr)
87
static inline bool is_load_store_instruction(instruction_t instr)
85
{
88
{
86
    /* load store immediate offset */
89
    /* load store immediate offset */
87
    if (instr.type == 0x2) {
90
    if (instr.type == 0x2)
88
        return true;
91
        return true;
89
    }
92
   
90
 
-
 
91
    /* load store register offset */
93
    /* load store register offset */
92
    if (instr.type == 0x3 && instr.bit4 == 0) {
94
    if ((instr.type == 0x3) && (instr.bit4 == 0))
93
        return true;
95
        return true;
94
    }
96
   
95
 
-
 
96
    /* load store multiple */
97
    /* load store multiple */
97
    if (instr.type == 0x4) {
98
    if (instr.type == 0x4)
98
        return true;
99
        return true;
99
    }
100
   
100
 
-
 
101
    /* oprocessor load/store */
101
    /* oprocessor load/store */
102
    if (instr.type == 0x6) {
102
    if (instr.type == 0x6)
103
        return true;
103
        return true;
104
    }
104
   
105
 
-
 
106
    return false;
105
    return false;
107
}
106
}
108
 
107
 
109
/** Decides whether the instruction is swap or not.
108
/** Decides whether the instruction is swap or not.
110
 *
109
 *
111
 * @param instr Instruction
110
 * @param instr Instruction
112
 *
111
 *
113
 * @return true when instruction is swap, false otherwise
112
 * @return true when instruction is swap, false otherwise
114
 */
113
 */
115
static inline bool is_swap_instruction(instruction_t instr)
114
static inline bool is_swap_instruction(instruction_t instr)
116
{
115
{
117
    /* swap, swapb instruction */
116
    /* swap, swapb instruction */
118
    if (instr.type == 0x0 &&
117
    if ((instr.type == 0x0) &&
119
        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
118
        ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
120
        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
119
        (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
121
        return true;
120
        return true;
122
    }
121
   
123
 
-
 
124
    return false;
122
    return false;
125
}
123
}
126
 
124
 
127
/** Decides whether read or write into memory is requested.
125
/** Decides whether read or write into memory is requested.
128
 *
126
 *
129
 * @param instr_addr   Address of instruction which tries to access memory.
127
 * @param instr_addr   Address of instruction which tries to access memory.
130
 * @param badvaddr     Virtual address the instruction tries to access.
128
 * @param badvaddr     Virtual address the instruction tries to access.
131
 *
129
 *
132
 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
130
 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
133
 *     requested.
131
 *     requested.
134
 */
132
 */
135
static pf_access_t get_memory_access_type(uint32_t instr_addr,
133
static pf_access_t get_memory_access_type(uint32_t instr_addr,
136
    uintptr_t badvaddr)
134
    uintptr_t badvaddr)
137
{
135
{
138
    instruction_union_t instr_union;
136
    instruction_union_t instr_union;
139
    instr_union.pc = instr_addr;
137
    instr_union.pc = instr_addr;
140
 
138
 
141
    instruction_t instr = *(instr_union.instr);
139
    instruction_t instr = *(instr_union.instr);
142
 
140
 
143
    /* undefined instructions */
141
    /* undefined instructions */
144
    if (instr.condition == 0xf) {
142
    if (instr.condition == 0xf) {
145
        panic("page_fault - instruction does not access memory "
143
        panic("page_fault - instruction does not access memory "
146
            "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
144
            "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
147
        return PF_ACCESS_EXEC;
145
        return PF_ACCESS_EXEC;
148
    }
146
    }
149
 
147
 
150
    /* load store instructions */
148
    /* load store instructions */
151
    if (is_load_store_instruction(instr)) {
149
    if (is_load_store_instruction(instr)) {
152
        if (instr.access == 1) {
150
        if (instr.access == 1) {
153
            return PF_ACCESS_READ;
151
            return PF_ACCESS_READ;
154
        } else {
152
        } else {
155
            return PF_ACCESS_WRITE;
153
            return PF_ACCESS_WRITE;
156
        }
154
        }
157
    }
155
    }
158
 
156
 
159
    /* swap, swpb instruction */
157
    /* swap, swpb instruction */
160
    if (is_swap_instruction(instr)) {
158
    if (is_swap_instruction(instr)) {
161
        return PF_ACCESS_WRITE;
159
        return PF_ACCESS_WRITE;
162
    }
160
    }
163
 
161
 
164
    panic("page_fault - instruction doesn't access memory "
162
    panic("page_fault - instruction doesn't access memory "
165
        "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
163
        "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
166
 
164
 
167
    return PF_ACCESS_EXEC;
165
    return PF_ACCESS_EXEC;
168
}
166
}
169
 
167
 
170
/** Handles "data abort" exception (load or store at invalid address).
168
/** Handles "data abort" exception (load or store at invalid address).
171
 *
169
 *
172
 * @param exc_no    Exception number.
170
 * @param exc_no    Exception number.
173
 * @param istate    CPU state when exception occured.
171
 * @param istate    CPU state when exception occured.
174
 */
172
 */
175
void data_abort(int exc_no, istate_t *istate)
173
void data_abort(int exc_no, istate_t *istate)
176
{
174
{
177
    fault_status_t fsr __attribute__ ((unused)) =
175
    fault_status_t fsr __attribute__ ((unused)) =
178
        read_fault_status_register();
176
        read_fault_status_register();
179
    uintptr_t badvaddr = read_fault_address_register();
177
    uintptr_t badvaddr = read_fault_address_register();
180
 
178
 
181
    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
179
    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
182
 
180
 
183
    int ret = as_page_fault(badvaddr, access, istate);
181
    int ret = as_page_fault(badvaddr, access, istate);
184
 
182
 
185
    if (ret == AS_PF_FAULT) {
183
    if (ret == AS_PF_FAULT) {
186
        print_istate(istate);
184
        print_istate(istate);
187
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
185
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
188
            "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
186
            "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
189
            access);
187
            access);
190
 
188
 
191
        fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
189
        fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
192
        panic("Page fault.");
190
        panic("Page fault.");
193
    }
191
    }
194
}
192
}
195
 
193
 
196
/** Handles "prefetch abort" exception (instruction couldn't be executed).
194
/** Handles "prefetch abort" exception (instruction couldn't be executed).
197
 *
195
 *
198
 * @param exc_no    Exception number.
196
 * @param exc_no    Exception number.
199
 * @param istate    CPU state when exception occured.
197
 * @param istate    CPU state when exception occured.
200
 */
198
 */
201
void prefetch_abort(int exc_no, istate_t *istate)
199
void prefetch_abort(int exc_no, istate_t *istate)
202
{
200
{
203
    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
201
    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
204
 
202
 
205
    if (ret == AS_PF_FAULT) {
203
    if (ret == AS_PF_FAULT) {
206
        dprintf("prefetch_abort\n");
204
        dprintf("prefetch_abort\n");
207
        print_istate(istate);
205
        print_istate(istate);
208
        panic("page fault - prefetch_abort at address: %x.",
206
        panic("page fault - prefetch_abort at address: %x.",
209
            istate->pc);
207
            istate->pc);
210
    }
208
    }
211
}
209
}
212
 
210
 
213
/** @}
211
/** @}
214
 */
212
 */
215
 
213