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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | 36 | ||
37 | #include <arch/exception.h> |
37 | #include <arch/exception.h> |
38 | #include <arch/debug/print.h> |
38 | #include <arch/debug/print.h> |
39 | #include <arch/memstr.h> |
39 | #include <arch/memstr.h> |
40 | #include <arch/regutils.h> |
40 | #include <arch/regutils.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | #include <arch/machine.h> |
42 | #include <arch/machine.h> |
43 | #include <arch/mm/page_fault.h> |
43 | #include <arch/mm/page_fault.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <syscall/syscall.h> |
45 | #include <syscall/syscall.h> |
46 | 46 | ||
47 | /** Offset used in calculation of exception handler's relative address. |
47 | /** Offset used in calculation of exception handler's relative address. |
48 | * |
48 | * |
49 | * @see install_handler() |
49 | * @see install_handler() |
50 | */ |
50 | */ |
51 | #define PREFETCH_OFFSET 0x8 |
51 | #define PREFETCH_OFFSET 0x8 |
52 | 52 | ||
53 | /** LDR instruction's code */ |
53 | /** LDR instruction's code */ |
54 | #define LDR_OPCODE 0xe59ff000 |
54 | #define LDR_OPCODE 0xe59ff000 |
55 | 55 | ||
56 | /** Number of exception vectors. */ |
56 | /** Number of exception vectors. */ |
57 | #define EXC_VECTORS 8 |
57 | #define EXC_VECTORS 8 |
58 | 58 | ||
59 | /** Size of memory block occupied by exception vectors. */ |
59 | /** Size of memory block occupied by exception vectors. */ |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
61 | 61 | ||
62 | 62 | ||
63 | /** Switches to kernel stack and saves all registers there. |
63 | /** Switches to kernel stack and saves all registers there. |
64 | * |
64 | * |
65 | * Temporary exception stack is used to save a few registers |
65 | * Temporary exception stack is used to save a few registers |
66 | * before stack switch takes place. |
66 | * before stack switch takes place. |
67 | */ |
67 | */ |
68 | inline static void setup_stack_and_save_regs() |
68 | inline static void setup_stack_and_save_regs() |
69 | { |
69 | { |
70 | asm volatile("ldr r13, =exc_stack \n\ |
70 | asm volatile("ldr r13, =exc_stack \n\ |
71 | stmfd r13!, {r0} \n\ |
71 | stmfd r13!, {r0} \n\ |
72 | mrs r0, spsr \n\ |
72 | mrs r0, spsr \n\ |
73 | and r0, r0, #0x1f \n\ |
73 | and r0, r0, #0x1f \n\ |
74 | cmp r0, #0x10 \n\ |
74 | cmp r0, #0x10 \n\ |
75 | bne 1f \n\ |
75 | bne 1f \n\ |
76 | \n\ |
76 | \n\ |
77 | @prev mode was usermode \n\ |
77 | @prev mode was usermode \n\ |
78 | ldmfd r13!, {r0} \n\ |
78 | ldmfd r13!, {r0} \n\ |
79 | ldr r13, =supervisor_sp \n\ |
79 | ldr r13, =supervisor_sp \n\ |
80 | ldr r13, [r13] \n\ |
80 | ldr r13, [r13] \n\ |
81 | stmfd r13!, {lr} \n\ |
81 | stmfd r13!, {lr} \n\ |
82 | stmfd r13!, {r0-r12} \n\ |
82 | stmfd r13!, {r0-r12} \n\ |
83 | stmfd r13!, {r13, lr}^ \n\ |
83 | stmfd r13!, {r13, lr}^ \n\ |
84 | mrs r0, spsr \n\ |
84 | mrs r0, spsr \n\ |
85 | stmfd r13!, {r0} \n\ |
85 | stmfd r13!, {r0} \n\ |
86 | b 2f \n\ |
86 | b 2f \n\ |
87 | \n\ |
87 | \n\ |
88 | @prev mode was not usermode \n\ |
88 | @prev mode was not usermode \n\ |
89 | 1: \n\ |
89 | 1: \n\ |
90 | stmfd r13!, {r1, r2, r3} \n\ |
90 | stmfd r13!, {r1, r2, r3} \n\ |
91 | mrs r1, cpsr \n\ |
91 | mrs r1, cpsr \n\ |
92 | mov r2, lr \n\ |
92 | mov r2, lr \n\ |
93 | bic r1, r1, #0x1f \n\ |
93 | bic r1, r1, #0x1f \n\ |
94 | orr r1, r1, r0 \n\ |
94 | orr r1, r1, r0 \n\ |
95 | mrs r0, cpsr \n\ |
95 | mrs r0, cpsr \n\ |
96 | msr cpsr_c, r1 \n\ |
96 | msr cpsr_c, r1 \n\ |
97 | \n\ |
97 | \n\ |
98 | mov r3, r13 \n\ |
98 | mov r3, r13 \n\ |
99 | stmfd r13!, {r2} \n\ |
99 | stmfd r13!, {r2} \n\ |
100 | mov r2, lr \n\ |
100 | mov r2, lr \n\ |
101 | stmfd r13!, {r4-r12} \n\ |
101 | stmfd r13!, {r4-r12} \n\ |
102 | mov r1, r13 \n\ |
102 | mov r1, r13 \n\ |
103 | @following two lines are for debugging \n\ |
103 | @following two lines are for debugging \n\ |
104 | mov sp, #0 \n\ |
104 | mov sp, #0 \n\ |
105 | mov lr, #0 \n\ |
105 | mov lr, #0 \n\ |
106 | msr cpsr_c, r0 \n\ |
106 | msr cpsr_c, r0 \n\ |
107 | \n\ |
107 | \n\ |
108 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
108 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
109 | stmfd r1!, {r4, r5, r6} \n\ |
109 | stmfd r1!, {r4, r5, r6} \n\ |
110 | stmfd r1!, {r7} \n\ |
110 | stmfd r1!, {r7} \n\ |
111 | stmfd r1!, {r2} \n\ |
111 | stmfd r1!, {r2} \n\ |
112 | stmfd r1!, {r3} \n\ |
112 | stmfd r1!, {r3} \n\ |
113 | mrs r0, spsr \n\ |
113 | mrs r0, spsr \n\ |
114 | stmfd r1!, {r0} \n\ |
114 | stmfd r1!, {r0} \n\ |
115 | mov r13, r1 \n\ |
115 | mov r13, r1 \n\ |
116 | 2:" |
116 | 2:" |
117 | ); |
117 | ); |
118 | } |
118 | } |
119 | 119 | ||
120 | 120 | ||
121 | /** Returns from exception mode. |
121 | /** Returns from exception mode. |
122 | * |
122 | * |
123 | * Previously saved state of registers (including control register) |
123 | * Previously saved state of registers (including control register) |
124 | * is restored from the stack. |
124 | * is restored from the stack. |
125 | */ |
125 | */ |
126 | inline static void load_regs() |
126 | inline static void load_regs() |
127 | { |
127 | { |
128 | asm volatile( "ldmfd r13!, {r0} \n\ |
128 | asm volatile( "ldmfd r13!, {r0} \n\ |
129 | msr spsr, r0 \n\ |
129 | msr spsr, r0 \n\ |
130 | and r0, r0, #0x1f \n\ |
130 | and r0, r0, #0x1f \n\ |
131 | cmp r0, #0x10 \n\ |
131 | cmp r0, #0x10 \n\ |
132 | bne 3f \n\ |
132 | bne 3f \n\ |
133 | \n\ |
133 | \n\ |
134 | @return to user mode \n\ |
134 | @return to user mode \n\ |
135 | ldmfd r13!, {r13, lr}^ \n\ |
135 | ldmfd r13!, {r13, lr}^ \n\ |
136 | b 4f \n\ |
136 | b 4f \n\ |
137 | \n\ |
137 | \n\ |
138 | @return to non-user mode \n\ |
138 | @return to non-user mode \n\ |
139 | 3: \n\ |
139 | 3: \n\ |
140 | ldmfd r13!, {r1, r2} \n\ |
140 | ldmfd r13!, {r1, r2} \n\ |
141 | mrs r3, cpsr \n\ |
141 | mrs r3, cpsr \n\ |
142 | bic r3, r3, #0x1f \n\ |
142 | bic r3, r3, #0x1f \n\ |
143 | orr r3, r3, r0 \n\ |
143 | orr r3, r3, r0 \n\ |
144 | mrs r0, cpsr \n\ |
144 | mrs r0, cpsr \n\ |
145 | msr cpsr_c, r3 \n\ |
145 | msr cpsr_c, r3 \n\ |
146 | \n\ |
146 | \n\ |
147 | mov r13, r1 \n\ |
147 | mov r13, r1 \n\ |
148 | mov lr, r2 \n\ |
148 | mov lr, r2 \n\ |
149 | msr cpsr_c, r0 \n\ |
149 | msr cpsr_c, r0 \n\ |
150 | \n\ |
150 | \n\ |
151 | @actual return \n\ |
151 | @actual return \n\ |
152 | 4: ldmfd r13, {r0-r12, pc}^" |
152 | 4: ldmfd r13, {r0-r12, pc}^" |
153 | ); |
153 | ); |
154 | } |
154 | } |
155 | 155 | ||
156 | /** Switch CPU to mode in which interrupts are serviced (currently it |
156 | /** Switch CPU to mode in which interrupts are serviced (currently it |
157 | * is Undefined mode). |
157 | * is Undefined mode). |
158 | * |
158 | * |
159 | * The default mode for interrupt servicing (Interrupt Mode) |
159 | * The default mode for interrupt servicing (Interrupt Mode) |
160 | * can not be used because of nested interrupts (which can occur |
160 | * can not be used because of nested interrupts (which can occur |
161 | * because interrupt are enabled in higher levels of interrupt handler). |
161 | * because interrupt are enabled in higher levels of interrupt handler). |
162 | */ |
162 | */ |
163 | inline static void switchToIrqServicingMode() |
163 | inline static void switchToIrqServicingMode() |
164 | { |
164 | { |
165 | /* switch to Undefined mode */ |
165 | /* switch to Undefined mode */ |
166 | asm volatile( |
166 | asm volatile( |
167 | /* save regs used during switching */ |
167 | /* save regs used during switching */ |
168 | "stmfd sp!, {r0-r3} \n" |
168 | "stmfd sp!, {r0-r3} \n" |
169 | 169 | ||
170 | /* save stack pointer and link register to r1, r2 */ |
170 | /* save stack pointer and link register to r1, r2 */ |
171 | "mov r1, sp \n" |
171 | "mov r1, sp \n" |
172 | "mov r2, lr \n" |
172 | "mov r2, lr \n" |
173 | 173 | ||
174 | /* mode switch */ |
174 | /* mode switch */ |
175 | "mrs r0, cpsr \n" |
175 | "mrs r0, cpsr \n" |
176 | "bic r0, r0, #0x1f \n" |
176 | "bic r0, r0, #0x1f \n" |
177 | "orr r0, r0, #0x1b \n" |
177 | "orr r0, r0, #0x1b \n" |
178 | "msr cpsr_c, r0 \n" |
178 | "msr cpsr_c, r0 \n" |
179 | 179 | ||
180 | /* restore saved sp and lr */ |
180 | /* restore saved sp and lr */ |
181 | "mov sp, r1 \n" |
181 | "mov sp, r1 \n" |
182 | "mov lr, r2 \n" |
182 | "mov lr, r2 \n" |
183 | 183 | ||
184 | /* restore original regs */ |
184 | /* restore original regs */ |
185 | "ldmfd sp!, {r0-r3} \n" |
185 | "ldmfd sp!, {r0-r3} \n" |
186 | ); |
186 | ); |
187 | } |
187 | } |
188 | 188 | ||
189 | /** Calls exception dispatch routine. */ |
189 | /** Calls exception dispatch routine. */ |
190 | #define CALL_EXC_DISPATCH(exception) \ |
190 | #define CALL_EXC_DISPATCH(exception) \ |
191 | asm("mov r0, %0" : : "i" (exception)); \ |
191 | asm("mov r0, %0" : : "i" (exception)); \ |
192 | asm("mov r1, r13"); \ |
192 | asm("mov r1, r13"); \ |
193 | asm("bl exc_dispatch"); |
193 | asm("bl exc_dispatch"); |
194 | 194 | ||
195 | 195 | ||
196 | /** General exception handler. |
196 | /** General exception handler. |
197 | * |
197 | * |
198 | * Stores registers, dispatches the exception, |
198 | * Stores registers, dispatches the exception, |
199 | * and finally restores registers and returns from exception processing. |
199 | * and finally restores registers and returns from exception processing. |
200 | * |
200 | * |
201 | * @param exception Exception number. |
201 | * @param exception Exception number. |
202 | */ |
202 | */ |
203 | #define PROCESS_EXCEPTION(exception) \ |
203 | #define PROCESS_EXCEPTION(exception) \ |
204 | setup_stack_and_save_regs(); \ |
204 | setup_stack_and_save_regs(); \ |
205 | CALL_EXC_DISPATCH(exception) \ |
205 | CALL_EXC_DISPATCH(exception) \ |
206 | load_regs(); |
206 | load_regs(); |
207 | 207 | ||
208 | 208 | ||
209 | /** Updates specified exception vector to jump to given handler. |
209 | /** Updates specified exception vector to jump to given handler. |
210 | * |
210 | * |
211 | * Addresses of handlers are stored in memory following exception vectors. |
211 | * Addresses of handlers are stored in memory following exception vectors. |
212 | */ |
212 | */ |
213 | static void install_handler (unsigned handler_addr, unsigned* vector) |
213 | static void install_handler (unsigned handler_addr, unsigned* vector) |
214 | { |
214 | { |
215 | /* relative address (related to exc. vector) of the word |
215 | /* relative address (related to exc. vector) of the word |
216 | * where handler's address is stored |
216 | * where handler's address is stored |
217 | */ |
217 | */ |
218 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
218 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
219 | 219 | ||
220 | /* make it LDR instruction and store at exception vector */ |
220 | /* make it LDR instruction and store at exception vector */ |
221 | *vector = handler_address_ptr | LDR_OPCODE; |
221 | *vector = handler_address_ptr | LDR_OPCODE; |
222 | 222 | ||
223 | /* store handler's address */ |
223 | /* store handler's address */ |
224 | *(vector + EXC_VECTORS) = handler_addr; |
224 | *(vector + EXC_VECTORS) = handler_addr; |
225 | 225 | ||
226 | } |
226 | } |
227 | 227 | ||
228 | 228 | ||
229 | /** Low-level Reset Exception handler. */ |
229 | /** Low-level Reset Exception handler. */ |
230 | static void reset_exception_entry() |
230 | static void reset_exception_entry() |
231 | { |
231 | { |
232 | PROCESS_EXCEPTION(EXC_RESET); |
232 | PROCESS_EXCEPTION(EXC_RESET); |
233 | } |
233 | } |
234 | 234 | ||
235 | 235 | ||
236 | /** Low-level Software Interrupt Exception handler. */ |
236 | /** Low-level Software Interrupt Exception handler. */ |
237 | static void swi_exception_entry() |
237 | static void swi_exception_entry() |
238 | { |
238 | { |
239 | PROCESS_EXCEPTION(EXC_SWI); |
239 | PROCESS_EXCEPTION(EXC_SWI); |
240 | } |
240 | } |
241 | 241 | ||
242 | 242 | ||
243 | /** Low-level Undefined Instruction Exception handler. */ |
243 | /** Low-level Undefined Instruction Exception handler. */ |
244 | static void undef_instr_exception_entry() |
244 | static void undef_instr_exception_entry() |
245 | { |
245 | { |
246 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
246 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
247 | } |
247 | } |
248 | 248 | ||
249 | 249 | ||
250 | /** Low-level Fast Interrupt Exception handler. */ |
250 | /** Low-level Fast Interrupt Exception handler. */ |
251 | static void fiq_exception_entry() |
251 | static void fiq_exception_entry() |
252 | { |
252 | { |
253 | PROCESS_EXCEPTION(EXC_FIQ); |
253 | PROCESS_EXCEPTION(EXC_FIQ); |
254 | } |
254 | } |
255 | 255 | ||
256 | 256 | ||
257 | /** Low-level Prefetch Abort Exception handler. */ |
257 | /** Low-level Prefetch Abort Exception handler. */ |
258 | static void prefetch_abort_exception_entry() |
258 | static void prefetch_abort_exception_entry() |
259 | { |
259 | { |
260 | asm("sub lr, lr, #4"); |
260 | asm("sub lr, lr, #4"); |
261 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
261 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
262 | } |
262 | } |
263 | 263 | ||
264 | 264 | ||
265 | /** Low-level Data Abort Exception handler. */ |
265 | /** Low-level Data Abort Exception handler. */ |
266 | static void data_abort_exception_entry() |
266 | static void data_abort_exception_entry() |
267 | { |
267 | { |
268 | asm("sub lr, lr, #8"); |
268 | asm("sub lr, lr, #8"); |
269 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
269 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
270 | } |
270 | } |
271 | 271 | ||
272 | 272 | ||
273 | /** Low-level Interrupt Exception handler. |
273 | /** Low-level Interrupt Exception handler. |
274 | * |
274 | * |
275 | * CPU is switched to Undefined mode before further interrupt processing |
275 | * CPU is switched to Undefined mode before further interrupt processing |
276 | * because of possible occurence of nested interrupt exception, which |
276 | * because of possible occurence of nested interrupt exception, which |
277 | * would overwrite (and thus spoil) stack pointer. |
277 | * would overwrite (and thus spoil) stack pointer. |
278 | */ |
278 | */ |
279 | static void irq_exception_entry() |
279 | static void irq_exception_entry() |
280 | { |
280 | { |
281 | asm("sub lr, lr, #4"); |
281 | asm("sub lr, lr, #4"); |
282 | setup_stack_and_save_regs(); |
282 | setup_stack_and_save_regs(); |
283 | 283 | ||
284 | switchToIrqServicingMode(); |
284 | switchToIrqServicingMode(); |
285 | 285 | ||
286 | CALL_EXC_DISPATCH(EXC_IRQ) |
286 | CALL_EXC_DISPATCH(EXC_IRQ) |
287 | 287 | ||
288 | load_regs(); |
288 | load_regs(); |
289 | } |
289 | } |
290 | 290 | ||
291 | 291 | ||
292 | /** Software Interrupt handler. |
292 | /** Software Interrupt handler. |
293 | * |
293 | * |
294 | * Dispatches the syscall. |
294 | * Dispatches the syscall. |
295 | */ |
295 | */ |
296 | static void swi_exception(int exc_no, istate_t *istate) |
296 | static void swi_exception(int exc_no, istate_t *istate) |
297 | { |
297 | { |
298 | /* |
298 | /* |
299 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
299 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
300 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
300 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
301 | */ |
301 | */ |
302 | 302 | ||
303 | istate->r0 = syscall_handler( |
303 | istate->r0 = syscall_handler( |
304 | istate->r0, |
304 | istate->r0, |
305 | istate->r1, |
305 | istate->r1, |
306 | istate->r2, |
306 | istate->r2, |
307 | istate->r3, |
307 | istate->r3, |
308 | istate->r4); |
308 | istate->r4); |
309 | } |
309 | } |
310 | 310 | ||
311 | 311 | ||
312 | /** Interrupt Exception handler. |
312 | /** Interrupt Exception handler. |
313 | * |
313 | * |
314 | * Determines the sources of interrupt, and calls their handlers. |
314 | * Determines the sources of interrupt, and calls their handlers. |
315 | */ |
315 | */ |
316 | static void irq_exception(int exc_no, istate_t *istate) |
316 | static void irq_exception(int exc_no, istate_t *istate) |
317 | { |
317 | { |
318 | machine_irq_exception(exc_no, istate); |
318 | machine_irq_exception(exc_no, istate); |
319 | } |
319 | } |
320 | 320 | ||
321 | 321 | ||
322 | /** Fills exception vectors with appropriate exception handlers. */ |
322 | /** Fills exception vectors with appropriate exception handlers. */ |
323 | void install_exception_handlers(void) |
323 | void install_exception_handlers(void) |
324 | { |
324 | { |
325 | install_handler((unsigned)reset_exception_entry, |
325 | install_handler((unsigned)reset_exception_entry, |
326 | (unsigned*)EXC_RESET_VEC); |
326 | (unsigned*)EXC_RESET_VEC); |
327 | 327 | ||
328 | install_handler((unsigned)undef_instr_exception_entry, |
328 | install_handler((unsigned)undef_instr_exception_entry, |
329 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
329 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
330 | 330 | ||
331 | install_handler((unsigned)swi_exception_entry, |
331 | install_handler((unsigned)swi_exception_entry, |
332 | (unsigned*)EXC_SWI_VEC); |
332 | (unsigned*)EXC_SWI_VEC); |
333 | 333 | ||
334 | install_handler((unsigned)prefetch_abort_exception_entry, |
334 | install_handler((unsigned)prefetch_abort_exception_entry, |
335 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
335 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
336 | 336 | ||
337 | install_handler((unsigned)data_abort_exception_entry, |
337 | install_handler((unsigned)data_abort_exception_entry, |
338 | (unsigned*)EXC_DATA_ABORT_VEC); |
338 | (unsigned*)EXC_DATA_ABORT_VEC); |
339 | 339 | ||
340 | install_handler((unsigned)irq_exception_entry, |
340 | install_handler((unsigned)irq_exception_entry, |
341 | (unsigned*)EXC_IRQ_VEC); |
341 | (unsigned*)EXC_IRQ_VEC); |
342 | 342 | ||
343 | install_handler((unsigned)fiq_exception_entry, |
343 | install_handler((unsigned)fiq_exception_entry, |
344 | (unsigned*)EXC_FIQ_VEC); |
344 | (unsigned*)EXC_FIQ_VEC); |
345 | } |
345 | } |
346 | 346 | ||
347 | 347 | ||
348 | #ifdef HIGH_EXCEPTION_VECTORS |
348 | #ifdef HIGH_EXCEPTION_VECTORS |
349 | /** Activates use of high exception vectors addresses. */ |
349 | /** Activates use of high exception vectors addresses. */ |
350 | static void high_vectors() |
350 | static void high_vectors() |
351 | { |
351 | { |
352 | uint32_t control_reg; |
352 | uint32_t control_reg; |
353 | 353 | ||
354 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
354 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
355 | 355 | ||
356 | //switch on the high vectors bit |
356 | //switch on the high vectors bit |
357 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
357 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
358 | 358 | ||
359 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
359 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
360 | } |
360 | } |
361 | #endif |
361 | #endif |
362 | 362 | ||
363 | 363 | ||
364 | /** Initializes exception handling. |
364 | /** Initializes exception handling. |
365 | * |
365 | * |
366 | * Installs low-level exception handlers and then registers |
366 | * Installs low-level exception handlers and then registers |
367 | * exceptions and their handlers to kernel exception dispatcher. |
367 | * exceptions and their handlers to kernel exception dispatcher. |
368 | */ |
368 | */ |
369 | void exception_init(void) |
369 | void exception_init(void) |
370 | { |
370 | { |
371 | #ifdef HIGH_EXCEPTION_VECTORS |
371 | #ifdef HIGH_EXCEPTION_VECTORS |
372 | high_vectors(); |
372 | high_vectors(); |
373 | #endif |
373 | #endif |
374 | install_exception_handlers(); |
374 | install_exception_handlers(); |
375 | 375 | ||
376 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
376 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
377 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
377 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
378 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
378 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
379 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
379 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
380 | } |
380 | } |
381 | 381 | ||
382 | 382 | ||
383 | /** Prints #istate_t structure content. |
383 | /** Prints #istate_t structure content. |
384 | * |
384 | * |
385 | * @param istate Structure to be printed. |
385 | * @param istate Structure to be printed. |
386 | */ |
386 | */ |
387 | void print_istate(istate_t *istate) |
387 | void print_istate(istate_t *istate) |
388 | { |
388 | { |
389 | dprintf("istate dump:\n"); |
389 | dprintf("istate dump:\n"); |
390 | 390 | ||
391 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
391 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
392 | istate->r0, istate->r1, istate->r2, istate->r3); |
392 | istate->r0, istate->r1, istate->r2, istate->r3); |
393 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
393 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
394 | istate->r4, istate->r5, istate->r6, istate->r7); |
394 | istate->r4, istate->r5, istate->r6, istate->r7); |
395 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
395 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
396 | istate->r8, istate->r9, istate->r10, istate->r11); |
396 | istate->r8, istate->r9, istate->r10, istate->r11); |
397 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
397 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
398 | istate->r12, istate->sp, istate->lr, istate->spsr); |
398 | istate->r12, istate->sp, istate->lr, istate->spsr); |
399 | 399 | ||
400 | dprintf(" pc: %x\n", istate->pc); |
400 | dprintf(" pc: %x\n", istate->pc); |
401 | } |
401 | } |
402 | 402 | ||
403 | 403 | ||
404 | /** @} |
404 | /** @} |
405 | */ |
405 | */ |
406 | 406 |