WebSVN – HelenOS – Diff – /trunk/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
    @brief  Exception handlers and exception initialization routines.
 */
 
#include <arch/exception.h>
#include <arch/debug_print/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/drivers/gxemul.h>
#include <arch/mm/page_fault.h>
#include <print.h>
#include <syscall/syscall.h>
 
#define PREFETCH_OFFSET     0x8
#define BRANCH_OPCODE       0xea000000
#define LDR_OPCODE      0xe59ff000
#define VALID_BRANCH_MASK   0xff000000
#define EXC_VECTORS_SIZE    0x20
#define EXC_VECTORS     0x8
 
extern uintptr_t supervisor_sp;
extern uintptr_t exc_stack;
 
inline static void setup_stack_and_save_regs()
{
asm volatile(   "ldr r13, =exc_stack        \n\
    stmfd r13!, {r0}            \n\
    mrs r0, spsr                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 1f                  \n\
                        \n\
    @prev mode was usermode         \n\
    ldmfd r13!, {r0}            \n\
    ldr r13, =supervisor_sp         \n\
    stmfd r13!, {lr}            \n\
    stmfd r13!, {r0-r12}            \n\
    stmfd r13!, {r13, lr}^          \n\
    mrs r0, spsr                \n\
    stmfd r13!, {r0}            \n\
    b 2f                    \n\
                        \n\
    @prev mode was not usermode     \n\
1:                      \n\
    stmfd r13!, {r1, r2, r3}        \n\
    mrs r1, cpsr                \n\
    mov r2, lr              \n\
    bic r1, r1, #0x1f           \n\
    orr r1, r1, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r1              \n\
                        \n\
    mov r3, r13             \n\
    stmfd r13!, {r2}            \n\
 
 
    mov r2, lr              \n\
    stmfd r13!, {r4-r12}            \n\
    mov r1, r13             \n\
    mov lr, #0              \n\
    mov sp, #0              \n\
    msr cpsr_c, r0              \n\
                        \n\
    ldmfd r13!, {r4, r5, r6, r7}        \n\
    stmfd r1!, {r4, r5, r6}         \n\
    stmfd r1!, {r7}             \n\
    stmfd r1!, {r2}             \n\
    stmfd r1!, {r3}             \n\
    mrs r0, spsr                \n\
    stmfd r1!, {r0}             \n\
    mov r13, r1             \n\
2:"
);
}
 
 
inline static void load_regs()
{
asm volatile(   "ldmfd r13!, {r0}       \n\
    msr spsr, r0                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 3f                  \n\
                        \n\
    @return to user mode            \n\
    ldmfd r13!, {r13, lr}^          \n\
    b 4f                    \n\
                        \n\
    @return to non-user mode        \n\
3:                      \n\
    ldmfd r13!, {r1, r2}            \n\
    mrs r3, cpsr                \n\
    bic r3, r3, #0x1f           \n\
    orr r3, r3, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r3              \n\
                        \n\
    mov r13, r1             \n\
    mov lr, r2              \n\
    msr cpsr_c, r0              \n\
                        \n\
    @actual return              \n\
                        \n\
    ldmfd r13, {r0-r12, pc}^        \n\
4:"
);
}
 
 
 
/*#define SAVE_REGS_TO_STACK            \
    asm("stmfd r13!, {r0-r12, r13, lr}");   \
    asm("mrs r14, spsr");           \
    asm("stmfd r13!, {r14}");
*/
 
 
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
 
/**Loads registers from the stack and resets SPSR before exitting exception
 * handler.
 
#define LOAD_REGS_FROM_STACK            \
    asm("ldmfd r13!, {r14}");       \
    asm("msr spsr, r14");           \
    asm("ldmfd r13!, {r0-r12, r13, pc}^");
 */
 
   
/** General exception handler.
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 */
 
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
/* #define PROCESS_EXCEPTION(exception)     \
    SAVE_REGS_TO_STACK      \
    CALL_EXC_DISPATCH(exception)        \
    LOAD_REGS_FROM_STACK*/
 
/** Updates specified exception vector to jump to given handler.
 * Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
 
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
/** Low-level Software Interrupt Exception handler */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
/** Low-level Undefined Instruction Exception handler */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
/** Low-level Fast Interrupt Exception handler */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
/** Low-level Prefetch Abort Exception handler */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
/** Low-level Data Abort Exception handler */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
 
 
 
    PROCESS_EXCEPTION(EXC_IRQ);
}
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
 
static void swi_exception(int exc_no, istate_t* istate)
{
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
}
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t* istate)
{
// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar
// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM
#if MACHINE == MACHINE_GXEMUL_TESTARM
    uint32_t sources = gxemul_irqc_get_sources();
    int i = 0;
    for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {
        if (sources & (1 << i)) {
            irq_t *irq = irq_dispatch_and_lock(i);
            if (irq) {
                /* The IRQ handler was found. */
                irq->handler(irq, irq->arg);
                spinlock_unlock(&irq->lock);
            } else {
                /* Spurious interrupt.*/
                dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);
            }
        }
    }
#endif
/* TODO remove after testing the above code
            noirq = 0;
            if (i == CONSOLE_IRQ) {
                char readchar = *(char*)0x10000000;
                if (readchar == 0) {
                    aux_puts("?");
                }
                else {
                    dprintf("%c", readchar);
                }
               
            }
            else if (i == TIMER_IRQ) {
                dprintf("\n.\n");
                //acknowledge
                *(uint32_t*)0x15000110 = 0;
            }
        }
    }
 
    if (noirq)
    aux_puts("IRQ exception without source\n");*/
}
 
/** Fills exception vectors with appropriate exception handlers.
*/
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates using high exception vectors addresses. */
 static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
    /* TODO add next */
}
 
/** Sets stack pointers in all supported exception modes.
 *
 * @param stack_ptr stack pointer
 */
void setup_exception_stacks()
{
        /* switch to particular mode and set "r13" there */
 
        uint32_t cspr = current_status_reg_read();
 
        /* IRQ stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* abort stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* TODO if you want to test other exceptions than IRQ,
        make stack analogous to irq_stack (in start.S),
        and then set stack pointer here */
 
        current_status_reg_control_write(cspr);
 
}
 
/** @}
 */
 

Rev 2284	Rev 2286
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	@brief Exception handlers and exception initialization routines.	33	@brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36	#include <arch/exception.h>	36	#include <arch/exception.h>
37	#include <arch/debug_print/print.h>	37	#include <arch/debug_print/print.h>
38	#include <arch/memstr.h>	38	#include <arch/memstr.h>
39	#include <arch/regutils.h>	39	#include <arch/regutils.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41	#include <arch/drivers/gxemul.h>	41	#include <arch/drivers/gxemul.h>
42	#include <arch/mm/page_fault.h>	42	#include <arch/mm/page_fault.h>
43	#include <print.h>	43	#include <print.h>
-		44	#include <syscall/syscall.h>
44		45
45	#define PREFETCH_OFFSET 0x8	46	#define PREFETCH_OFFSET 0x8
46	#define BRANCH_OPCODE 0xea000000	47	#define BRANCH_OPCODE 0xea000000
47	#define LDR_OPCODE 0xe59ff000	48	#define LDR_OPCODE 0xe59ff000
48	#define VALID_BRANCH_MASK 0xff000000	49	#define VALID_BRANCH_MASK 0xff000000
49	#define EXC_VECTORS_SIZE 0x20	50	#define EXC_VECTORS_SIZE 0x20
50	#define EXC_VECTORS 0x8	51	#define EXC_VECTORS 0x8
51		52
52	extern uintptr_t supervisor_sp;	53	extern uintptr_t supervisor_sp;
53	extern uintptr_t exc_stack;	54	extern uintptr_t exc_stack;
54		55
55	inline static void setup_stack_and_save_regs()	56	inline static void setup_stack_and_save_regs()
56	{	57	{
57	asm volatile( "ldr r13, =exc_stack \n\	58	asm volatile( "ldr r13, =exc_stack \n\
58	stmfd r13!, {r0} \n\	59	stmfd r13!, {r0} \n\
59	mrs r0, spsr \n\	60	mrs r0, spsr \n\
60	and r0, r0, #0x1f \n\	61	and r0, r0, #0x1f \n\
61	cmp r0, #0x10 \n\	62	cmp r0, #0x10 \n\
62	bne 1f \n\	63	bne 1f \n\
63	\n\	64	\n\
64	@prev mode was usermode \n\	65	@prev mode was usermode \n\
65	ldmfd r13!, {r0} \n\	66	ldmfd r13!, {r0} \n\
66	ldr r13, =supervisor_sp \n\	67	ldr r13, =supervisor_sp \n\
-		68	stmfd r13!, {lr} \n\
67	stmfd r13!, {r0-r12, r13, lr} \n\	69	stmfd r13!, {r0-r12} \n\
68	stmfd r13!, {r13, lr}^ \n\	70	stmfd r13!, {r13, lr}^ \n\
69	mrs r0, spsr \n\	71	mrs r0, spsr \n\
70	stmfd r13!, {r0} \n\	72	stmfd r13!, {r0} \n\
71	b 2f \n\	73	b 2f \n\
72	\n\	74	\n\
73	@prev mode was not usermode \n\	75	@prev mode was not usermode \n\
74	1: \n\	76	1: \n\
75	stmfd r13!, {r1, r2, r3} \n\	77	stmfd r13!, {r1, r2, r3} \n\
76	mrs r1, cpsr \n\	78	mrs r1, cpsr \n\
77	mov r2, lr \n\	79	mov r2, lr \n\
78	bic r1, r1, #0x1f \n\	80	bic r1, r1, #0x1f \n\
79	orr r1, r1, r0 \n\	81	orr r1, r1, r0 \n\
80	mrs r0, cpsr \n\	82	mrs r0, cpsr \n\
81	msr cpsr_c, r1 \n\	83	msr cpsr_c, r1 \n\
82	\n\	84	\n\
83	mov r3, r13 \n\	85	mov r3, r13 \n\
84	stmfd r13!, {r2} \n\	86	stmfd r13!, {r2} \n\
85	stmfd r13!, {r3} \n\	-
86	stmfd r13!, {r4-r12} \n\	-
87	mov r2, lr \n\	87	mov r2, lr \n\
-		88	stmfd r13!, {r4-r12} \n\
88	mov r1, r13 \n\	89	mov r1, r13 \n\
-		90	mov lr, #0 \n\
-		91	mov sp, #0 \n\
89	msr cpsr_c, r0 \n\	92	msr cpsr_c, r0 \n\
90	\n\	93	\n\
91	ldmfd r13!, {r4, r5, r6, r7} \n\	94	ldmfd r13!, {r4, r5, r6, r7} \n\
92	stmfd r1!, {r4, r5, r6} \n\	95	stmfd r1!, {r4, r5, r6} \n\
93	stmfd r1!, {r7} \n\	96	stmfd r1!, {r7} \n\
94	stmfd r1!, {r2} \n\	97	stmfd r1!, {r2} \n\
95	stmfd r1!, {r3} \n\	98	stmfd r1!, {r3} \n\
96	mrs r0, spsr \n\	99	mrs r0, spsr \n\
97	stmfd r1!, {r0} \n\	100	stmfd r1!, {r0} \n\
98	mov r13, r1 \n\	101	mov r13, r1 \n\
99	2:"	102	2:"
100	);	103	);
101	}	104	}
102		105
103		106
104	inline static void load_regs()	107	inline static void load_regs()
105	{	108	{
106	asm volatile( "ldmfd r13!, {r0} \n\	109	asm volatile( "ldmfd r13!, {r0} \n\
107	msr spsr, r0 \n\	110	msr spsr, r0 \n\
108	and r0, r0, #0x1f \n\	111	and r0, r0, #0x1f \n\
109	cmp r0, #0x10 \n\	112	cmp r0, #0x10 \n\
110	bne 3f \n\	113	bne 3f \n\
111	\n\	114	\n\
112	@return to user mode \n\	115	@return to user mode \n\
113	ldmfd r13!, {r13, lr}^ \n\	116	ldmfd r13!, {r13, lr}^ \n\
114	b 4f \n\	117	b 4f \n\
115	\n\	118	\n\
116	@return to non-user mode \n\	119	@return to non-user mode \n\
117	3: \n\	120	3: \n\
118	ldmfd r13!, {r1, r2} \n\	121	ldmfd r13!, {r1, r2} \n\
119	mrs r3, cpsr \n\	122	mrs r3, cpsr \n\
120	bic r3, r3, #0x1f \n\	123	bic r3, r3, #0x1f \n\
121	orr r3, r3, r0 \n\	124	orr r3, r3, r0 \n\
122	mrs r0, cpsr \n\	125	mrs r0, cpsr \n\
123	msr cpsr_c, r3 \n\	126	msr cpsr_c, r3 \n\
124	\n\	127	\n\
125	mov r13, r1 \n\	128	mov r13, r1 \n\
126	mov lr, r2 \n\	129	mov lr, r2 \n\
127	msr cpsr_c, r0 \n\	130	msr cpsr_c, r0 \n\
128	\n\	131	\n\
129	@actual return \n\	132	@actual return \n\
130	4: \n\	133	\n\
131	ldmfd r13!, {r0-r12, r13, pc}^"	134	ldmfd r13, {r0-r12, pc}^ \n\
-		135	4:"
132	);	136	);
133	}	137	}
134		138
135		139
-		140
136	#define SAVE_REGS_TO_STACK \	141	/*#define SAVE_REGS_TO_STACK \
137	asm("stmfd r13!, {r0-r12, r13, lr}"); \	142	asm("stmfd r13!, {r0-r12, r13, lr}"); \
138	asm("mrs r14, spsr"); \	143	asm("mrs r14, spsr"); \
139	asm("stmfd r13!, {r14}");	144	asm("stmfd r13!, {r14}");
140		145	*/
141		146
142		147
143	#define CALL_EXC_DISPATCH(exception) \	148	#define CALL_EXC_DISPATCH(exception) \
144	asm("mov r0, %0" : : "i" (exception)); \	149	asm("mov r0, %0" : : "i" (exception)); \
145	asm("mov r1, r13"); \	150	asm("mov r1, r13"); \
146	asm("bl exc_dispatch");	151	asm("bl exc_dispatch");
147		152
148		153
149	/**Loads registers from the stack and resets SPSR before exitting exception	154	/**Loads registers from the stack and resets SPSR before exitting exception
150	* handler.	155	* handler.
151	*/	156
152	#define LOAD_REGS_FROM_STACK \	157	#define LOAD_REGS_FROM_STACK \
153	asm("ldmfd r13!, {r14}"); \	158	asm("ldmfd r13!, {r14}"); \
154	asm("msr spsr, r14"); \	159	asm("msr spsr, r14"); \
155	asm("ldmfd r13!, {r0-r12, r13, pc}^");	160	asm("ldmfd r13!, {r0-r12, r13, pc}^");
156		161	*/
157		162
158		163
159	/** General exception handler.	164	/** General exception handler.
160	* Stores registers, dispatches the exception,	165	* Stores registers, dispatches the exception,
161	* and finally restores registers and returns from exception processing.	166	* and finally restores registers and returns from exception processing.
162	*/	167	*/
163		168
164	#define PROCESS_EXCEPTION(exception) \	169	#define PROCESS_EXCEPTION(exception) \
165	setup_stack_and_save_regs(); \	170	setup_stack_and_save_regs(); \
166	CALL_EXC_DISPATCH(exception) \	171	CALL_EXC_DISPATCH(exception) \
167	load_regs();	172	load_regs();
168		173
169	/* #define PROCESS_EXCEPTION(exception) \	174	/* #define PROCESS_EXCEPTION(exception) \
170	SAVE_REGS_TO_STACK \	175	SAVE_REGS_TO_STACK \
171	CALL_EXC_DISPATCH(exception) \	176	CALL_EXC_DISPATCH(exception) \
172	LOAD_REGS_FROM_STACK*/	177	LOAD_REGS_FROM_STACK*/
173		178
174	/** Updates specified exception vector to jump to given handler.	179	/** Updates specified exception vector to jump to given handler.
175	* Addresses of handlers are stored in memory following exception vectors.	180	* Addresses of handlers are stored in memory following exception vectors.
176	*/	181	*/
177	static void install_handler (unsigned handler_addr, unsigned* vector)	182	static void install_handler (unsigned handler_addr, unsigned* vector)
178	{	183	{
179	/* relative address (related to exc. vector) of the word	184	/* relative address (related to exc. vector) of the word
180	* where handler's address is stored	185	* where handler's address is stored
181	*/	186	*/
182	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	187	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
183		188
184	/* make it LDR instruction and store at exception vector */	189	/* make it LDR instruction and store at exception vector */
185	*vector = handler_address_ptr \| LDR_OPCODE;	190	*vector = handler_address_ptr \| LDR_OPCODE;
186		191
187	/* store handler's address */	192	/* store handler's address */
188	*(vector + EXC_VECTORS) = handler_addr;	193	*(vector + EXC_VECTORS) = handler_addr;
189		194
190	}	195	}
191		196
192		197
193	static void reset_exception_entry()	198	static void reset_exception_entry()
194	{	199	{
195	PROCESS_EXCEPTION(EXC_RESET);	200	PROCESS_EXCEPTION(EXC_RESET);
196	}	201	}
197		202
198	/** Low-level Software Interrupt Exception handler */	203	/** Low-level Software Interrupt Exception handler */
199	static void swi_exception_entry()	204	static void swi_exception_entry()
200	{	205	{
201	PROCESS_EXCEPTION(EXC_SWI);	206	PROCESS_EXCEPTION(EXC_SWI);
202	}	207	}
203		208
204	/** Low-level Undefined Instruction Exception handler */	209	/** Low-level Undefined Instruction Exception handler */
205	static void undef_instr_exception_entry()	210	static void undef_instr_exception_entry()
206	{	211	{
207	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	212	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
208	}	213	}
209		214
210	/** Low-level Fast Interrupt Exception handler */	215	/** Low-level Fast Interrupt Exception handler */
211	static void fiq_exception_entry()	216	static void fiq_exception_entry()
212	{	217	{
213	PROCESS_EXCEPTION(EXC_FIQ);	218	PROCESS_EXCEPTION(EXC_FIQ);
214	}	219	}
215		220
216	/** Low-level Prefetch Abort Exception handler */	221	/** Low-level Prefetch Abort Exception handler */
217	static void prefetch_abort_exception_entry()	222	static void prefetch_abort_exception_entry()
218	{	223	{
219	asm("sub lr, lr, #4");	224	asm("sub lr, lr, #4");
220	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	225	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
221	}	226	}
222		227
223	/** Low-level Data Abort Exception handler */	228	/** Low-level Data Abort Exception handler */
224	static void data_abort_exception_entry()	229	static void data_abort_exception_entry()
225	{	230	{
226	asm("sub lr, lr, #8");	231	asm("sub lr, lr, #8");
227	PROCESS_EXCEPTION(EXC_DATA_ABORT);	232	PROCESS_EXCEPTION(EXC_DATA_ABORT);
228	}	233	}
229		234
230		235
231	/** Low-level Interrupt Exception handler */	236	/** Low-level Interrupt Exception handler */
232	static void irq_exception_entry()	237	static void irq_exception_entry()
233	{	238	{
234	asm("sub lr, lr, #4");	239	asm("sub lr, lr, #4");
235	// SAVE_REGS_TO_STACK	-
236	// CALL_EXC_DISPATCH(EXC_IRQ)	-
237	// LOAD_REGS_FROM_STACK;	-
238	PROCESS_EXCEPTION(EXC_IRQ);	240	PROCESS_EXCEPTION(EXC_IRQ);
239	}	241	}
240		242
241	// static void prefetch_abort_exception(int exc_no, istate_t* istate)	243	/** Software Interrupt handler.
242	// {	244	*
243	// dputs("(PREFETCH\|DATA) ABORT exception caught, not processed.\n");	245	* Dispatches the syscall.
244	// }	246	*/
245		-
246	static void swi_exception(int exc_no, istate_t* istate)	247	static void swi_exception(int exc_no, istate_t* istate)
247	{	248	{
248	dprintf("\nIstate dump:\n");	249	istate->r0 = syscall_handler(
249	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);	250	istate->r0,
250	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);	251	istate->r1,
251	dprintf(" r8:%X r9:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);	252	istate->r2,
252	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);	253	istate->r3,
253	dprintf(" prev_lr:%X prev_sp:%X\n", istate->prev_lr, istate->prev_sp);	254	istate->r4);
254	}	255	}
255		256
256	/** Interrupt Exception handler.	257	/** Interrupt Exception handler.
-		258	*
257	* Determines the sources of interrupt, and calls their handlers.	259	* Determines the sources of interrupt, and calls their handlers.
258	*/	260	*/
259	static void irq_exception(int exc_no, istate_t* istate)	261	static void irq_exception(int exc_no, istate_t* istate)
260	{	262	{
261	// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar	263	// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar
262	// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM	264	// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM
263	#if MACHINE == MACHINE_GXEMUL_TESTARM	265	#if MACHINE == MACHINE_GXEMUL_TESTARM
264	uint32_t sources = gxemul_irqc_get_sources();	266	uint32_t sources = gxemul_irqc_get_sources();
265	int i = 0;	267	int i = 0;
266	for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {	268	for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {
267	if (sources & (1 << i)) {	269	if (sources & (1 << i)) {
268	irq_t *irq = irq_dispatch_and_lock(i);	270	irq_t *irq = irq_dispatch_and_lock(i);
269	if (irq) {	271	if (irq) {
270	/* The IRQ handler was found. */	272	/* The IRQ handler was found. */
271	irq->handler(irq, irq->arg);	273	irq->handler(irq, irq->arg);
272	spinlock_unlock(&irq->lock);	274	spinlock_unlock(&irq->lock);
273	} else {	275	} else {
274	/* Spurious interrupt.*/	276	/* Spurious interrupt.*/
275	dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);	277	dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);
276	}	278	}
277	}	279	}
278	}	280	}
279	#endif	281	#endif
280	/* TODO remove after testing the above code	282	/* TODO remove after testing the above code
281	noirq = 0;	283	noirq = 0;
282	if (i == CONSOLE_IRQ) {	284	if (i == CONSOLE_IRQ) {
283	char readchar = (char)0x10000000;	285	char readchar = (char)0x10000000;
284	if (readchar == 0) {	286	if (readchar == 0) {
285	aux_puts("?");	287	aux_puts("?");
286	}	288	}
287	else {	289	else {
288	dprintf("%c", readchar);	290	dprintf("%c", readchar);
289	}	291	}
290		292
291	}	293	}
292	else if (i == TIMER_IRQ) {	294	else if (i == TIMER_IRQ) {
293	dprintf("\n.\n");	295	dprintf("\n.\n");
294	//acknowledge	296	//acknowledge
295	(uint32_t)0x15000110 = 0;	297	(uint32_t)0x15000110 = 0;
296	}	298	}
297	}	299	}
298	}	300	}
299		301
300	if (noirq)	302	if (noirq)
301	aux_puts("IRQ exception without source\n");*/	303	aux_puts("IRQ exception without source\n");*/
302	}	304	}
303		305
304	/** Fills exception vectors with appropriate exception handlers.	306	/** Fills exception vectors with appropriate exception handlers.
305	*/	307	*/
306	void install_exception_handlers(void)	308	void install_exception_handlers(void)
307	{	309	{
308	install_handler((unsigned)reset_exception_entry,	310	install_handler((unsigned)reset_exception_entry,
309	(unsigned*)EXC_RESET_VEC);	311	(unsigned*)EXC_RESET_VEC);
310		312
311	install_handler((unsigned)undef_instr_exception_entry,	313	install_handler((unsigned)undef_instr_exception_entry,
312	(unsigned*)EXC_UNDEF_INSTR_VEC);	314	(unsigned*)EXC_UNDEF_INSTR_VEC);
313		315
314	install_handler((unsigned)swi_exception_entry,	316	install_handler((unsigned)swi_exception_entry,
315	(unsigned*)EXC_SWI_VEC);	317	(unsigned*)EXC_SWI_VEC);
316		318
317	install_handler((unsigned)prefetch_abort_exception_entry,	319	install_handler((unsigned)prefetch_abort_exception_entry,
318	(unsigned*)EXC_PREFETCH_ABORT_VEC);	320	(unsigned*)EXC_PREFETCH_ABORT_VEC);
319		321
320	install_handler((unsigned)data_abort_exception_entry,	322	install_handler((unsigned)data_abort_exception_entry,
321	(unsigned*)EXC_DATA_ABORT_VEC);	323	(unsigned*)EXC_DATA_ABORT_VEC);
322		324
323	install_handler((unsigned)irq_exception_entry,	325	install_handler((unsigned)irq_exception_entry,
324	(unsigned*)EXC_IRQ_VEC);	326	(unsigned*)EXC_IRQ_VEC);
325		327
326	install_handler((unsigned)fiq_exception_entry,	328	install_handler((unsigned)fiq_exception_entry,
327	(unsigned*)EXC_FIQ_VEC);	329	(unsigned*)EXC_FIQ_VEC);
328	}	330	}
329		331
330	#ifdef HIGH_EXCEPTION_VECTORS	332	#ifdef HIGH_EXCEPTION_VECTORS
331	/** Activates using high exception vectors addresses. */	333	/** Activates using high exception vectors addresses. */
332	static void high_vectors()	334	static void high_vectors()
333	{	335	{
334	uint32_t control_reg;	336	uint32_t control_reg;
335		337
336	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	338	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
337		339
338	//switch on the high vectors bit	340	//switch on the high vectors bit
339	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	341	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
340		342
341	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	343	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
342	}	344	}
343	#endif	345	#endif
344		346
345	/** Initializes exception handling.	347	/** Initializes exception handling.
346	*	348	*
347	* Installs low-level exception handlers and then registers	349	* Installs low-level exception handlers and then registers
348	* exceptions and their handlers to kernel exception dispatcher.	350	* exceptions and their handlers to kernel exception dispatcher.
349	*/	351	*/
350	void exception_init(void)	352	void exception_init(void)
351	{	353	{
352	#ifdef HIGH_EXCEPTION_VECTORS	354	#ifdef HIGH_EXCEPTION_VECTORS
353	high_vectors();	355	high_vectors();
354	#endif	356	#endif
355	install_exception_handlers();	357	install_exception_handlers();
356		358
357	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	359	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
358	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);	360	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
359	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	361	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
360	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	362	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
361	/* TODO add next */	363	/* TODO add next */
362	}	364	}
363		365
364	/** Sets stack pointers in all supported exception modes.	366	/** Sets stack pointers in all supported exception modes.
365	*	367	*
366	* @param stack_ptr stack pointer	368	* @param stack_ptr stack pointer
367	*/	369	*/
368	void setup_exception_stacks()	370	void setup_exception_stacks()
369	{	371	{
370	/* switch to particular mode and set "r13" there */	372	/* switch to particular mode and set "r13" there */
371		373
372	uint32_t cspr = current_status_reg_read();	374	uint32_t cspr = current_status_reg_read();
373		375
374	/* IRQ stack */	376	/* IRQ stack */
375	current_status_reg_control_write(	377	current_status_reg_control_write(
376	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE	378	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE
377	);	379	);
378	asm("ldr r13, =exc_stack");	380	asm("ldr r13, =exc_stack");
379		381
380	/* abort stack */	382	/* abort stack */
381	current_status_reg_control_write(	383	current_status_reg_control_write(
382	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE	384	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE
383	);	385	);
384	asm("ldr r13, =exc_stack");	386	asm("ldr r13, =exc_stack");
385		387
386	/* TODO if you want to test other exceptions than IRQ,	388	/* TODO if you want to test other exceptions than IRQ,
387	make stack analogous to irq_stack (in start.S),	389	make stack analogous to irq_stack (in start.S),
388	and then set stack pointer here */	390	and then set stack pointer here */
389		391
390	current_status_reg_control_write( cspr);	392	current_status_reg_control_write(cspr);
391		393
392	}	394	}
393		395
394	/** @}	396	/** @}
395	*/	397	*/
396		398

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(root)/trunk/kernel/arch/arm32/src/exception.c @ 3861 – Rev 2284 → 2286