WebSVN – HelenOS – Diff – /trunk/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
    @brief  Exception handlers and exception initialization routines.
 */
 
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <print.h>
#include <syscall/syscall.h>
 
 
#define PREFETCH_OFFSET      0x8
#define BRANCH_OPCODE        0xea000000
#define LDR_OPCODE           0xe59ff000
#define VALID_BRANCH_MASK    0xff000000
#define EXC_VECTORS_SIZE     0x20
#define EXC_VECTORS          0x8
 
 
extern uintptr_t supervisor_sp;
extern uintptr_t exc_stack;
 
 
inline static void setup_stack_and_save_regs()
{
asm volatile(   "ldr r13, =exc_stack        \n\
    stmfd r13!, {r0}            \n\
    mrs r0, spsr                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 1f                  \n\
                        \n\
    @prev mode was usermode         \n\
    ldmfd r13!, {r0}            \n\
    ldr r13, =supervisor_sp         \n\
    ldr r13, [r13]              \n\
    stmfd r13!, {lr}            \n\
    stmfd r13!, {r0-r12}            \n\
    stmfd r13!, {r13, lr}^          \n\
    mrs r0, spsr                \n\
    stmfd r13!, {r0}            \n\
    b 2f                    \n\
                        \n\
    @prev mode was not usermode     \n\
1:                      \n\
    stmfd r13!, {r1, r2, r3}        \n\
    mrs r1, cpsr                \n\
    mov r2, lr              \n\
    bic r1, r1, #0x1f           \n\
    orr r1, r1, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r1              \n\
                        \n\
    mov r3, r13             \n\
    stmfd r13!, {r2}            \n\
    mov r2, lr              \n\
    stmfd r13!, {r4-r12}            \n\
    mov r1, r13             \n\
    @following two lines are for debugging  \n\
    mov sp, #0              \n\
    mov lr, #0              \n\
    msr cpsr_c, r0              \n\
                        \n\
    ldmfd r13!, {r4, r5, r6, r7}        \n\
    stmfd r1!, {r4, r5, r6}         \n\
    stmfd r1!, {r7}             \n\
    stmfd r1!, {r2}             \n\
    stmfd r1!, {r3}             \n\
    mrs r0, spsr                \n\
    stmfd r1!, {r0}             \n\
    mov r13, r1             \n\
2:"
);
}
 
 
inline static void load_regs()
{
asm volatile(   "ldmfd r13!, {r0}       \n\
    msr spsr, r0                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 3f                  \n\
                        \n\
    @return to user mode            \n\
    ldmfd r13!, {r13, lr}^          \n\
    b 4f                    \n\
                        \n\
    @return to non-user mode        \n\
3:                      \n\
    ldmfd r13!, {r1, r2}            \n\
    mrs r3, cpsr                \n\
    bic r3, r3, #0x1f           \n\
    orr r3, r3, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r3              \n\
                        \n\
    mov r13, r1             \n\
    mov lr, r2              \n\
    msr cpsr_c, r0              \n\
                        \n\
    @actual return              \n\
4:  ldmfd r13, {r0-r12, pc}^"
);
}
 
 
 
/*#define SAVE_REGS_TO_STACK            \
    asm("stmfd r13!, {r0-r12, r13, lr}");   \
    asm("mrs r14, spsr");           \
    asm("stmfd r13!, {r14}");
*/
 
 
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
 
/**Loads registers from the stack and resets SPSR before exitting exception
 * handler.
 
#define LOAD_REGS_FROM_STACK            \
    asm("ldmfd r13!, {r14}");       \
    asm("msr spsr, r14");           \
    asm("ldmfd r13!, {r0-r12, r13, pc}^");
 */
 
   
/** General exception handler.
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
 
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
/* #define PROCESS_EXCEPTION(exception)     \
    SAVE_REGS_TO_STACK      \
    CALL_EXC_DISPATCH(exception)        \
    LOAD_REGS_FROM_STACK*/
 
 
/** Updates specified exception vector to jump to given handler.
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler. */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_IRQ);
}
 
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
        istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
 
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
}
 
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
 
/** Fills exception vectors with appropriate exception handlers. */
 
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
    /* TODO add next */
}
 
 
/** Sets stack pointers in all supported exception modes. */
 
void setup_exception_stacks()
{
        /* switch to particular mode and set "r13" there */
 
        uint32_t cspr = current_status_reg_read();
 
        /* IRQ stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* abort stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* TODO if you want to test other exceptions than IRQ,
        make stack analogous to irq_stack (in start.S),
        and then set stack pointer here */
 
        current_status_reg_control_write(cspr);
}
 
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
 
/** @}
 */
 

Rev 2326	Rev 2329
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	@brief Exception handlers and exception initialization routines.	33	@brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
-		36
36	#include <arch/exception.h>	37	#include <arch/exception.h>
37	#include <arch/debug/print.h>	38	#include <arch/debug/print.h>
38	#include <arch/memstr.h>	39	#include <arch/memstr.h>
39	#include <arch/regutils.h>	40	#include <arch/regutils.h>
40	#include <interrupt.h>	41	#include <interrupt.h>
41	#include <arch/machine.h>	42	#include <arch/machine.h>
42	#include <arch/mm/page_fault.h>	43	#include <arch/mm/page_fault.h>
43	#include <print.h>	44	#include <print.h>
44	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
45		46
-		47
46	#define PREFETCH_OFFSET 0x8	48	#define PREFETCH_OFFSET 0x8
47	#define BRANCH_OPCODE 0xea000000	49	#define BRANCH_OPCODE 0xea000000
48	#define LDR_OPCODE 0xe59ff000	50	#define LDR_OPCODE 0xe59ff000
49	#define VALID_BRANCH_MASK 0xff000000	51	#define VALID_BRANCH_MASK 0xff000000
50	#define EXC_VECTORS_SIZE 0x20	52	#define EXC_VECTORS_SIZE 0x20
51	#define EXC_VECTORS 0x8	53	#define EXC_VECTORS 0x8
52		54
-		55
53	extern uintptr_t supervisor_sp;	56	extern uintptr_t supervisor_sp;
54	extern uintptr_t exc_stack;	57	extern uintptr_t exc_stack;
55		58
-		59
56	inline static void setup_stack_and_save_regs()	60	inline static void setup_stack_and_save_regs()
57	{	61	{
58	asm volatile( "ldr r13, =exc_stack \n\	62	asm volatile( "ldr r13, =exc_stack \n\
59	stmfd r13!, {r0} \n\	63	stmfd r13!, {r0} \n\
60	mrs r0, spsr \n\	64	mrs r0, spsr \n\
61	and r0, r0, #0x1f \n\	65	and r0, r0, #0x1f \n\
62	cmp r0, #0x10 \n\	66	cmp r0, #0x10 \n\
63	bne 1f \n\	67	bne 1f \n\
64	\n\	68	\n\
65	@prev mode was usermode \n\	69	@prev mode was usermode \n\
66	ldmfd r13!, {r0} \n\	70	ldmfd r13!, {r0} \n\
67	ldr r13, =supervisor_sp \n\	71	ldr r13, =supervisor_sp \n\
68	ldr r13, [r13] \n\	72	ldr r13, [r13] \n\
69	stmfd r13!, {lr} \n\	73	stmfd r13!, {lr} \n\
70	stmfd r13!, {r0-r12} \n\	74	stmfd r13!, {r0-r12} \n\
71	stmfd r13!, {r13, lr}^ \n\	75	stmfd r13!, {r13, lr}^ \n\
72	mrs r0, spsr \n\	76	mrs r0, spsr \n\
73	stmfd r13!, {r0} \n\	77	stmfd r13!, {r0} \n\
74	b 2f \n\	78	b 2f \n\
75	\n\	79	\n\
76	@prev mode was not usermode \n\	80	@prev mode was not usermode \n\
77	1: \n\	81	1: \n\
78	stmfd r13!, {r1, r2, r3} \n\	82	stmfd r13!, {r1, r2, r3} \n\
79	mrs r1, cpsr \n\	83	mrs r1, cpsr \n\
80	mov r2, lr \n\	84	mov r2, lr \n\
81	bic r1, r1, #0x1f \n\	85	bic r1, r1, #0x1f \n\
82	orr r1, r1, r0 \n\	86	orr r1, r1, r0 \n\
83	mrs r0, cpsr \n\	87	mrs r0, cpsr \n\
84	msr cpsr_c, r1 \n\	88	msr cpsr_c, r1 \n\
85	\n\	89	\n\
86	mov r3, r13 \n\	90	mov r3, r13 \n\
87	stmfd r13!, {r2} \n\	91	stmfd r13!, {r2} \n\
88	mov r2, lr \n\	92	mov r2, lr \n\
89	stmfd r13!, {r4-r12} \n\	93	stmfd r13!, {r4-r12} \n\
90	mov r1, r13 \n\	94	mov r1, r13 \n\
91	@following two lines are for debugging \n\	95	@following two lines are for debugging \n\
92	mov sp, #0 \n\	96	mov sp, #0 \n\
93	mov lr, #0 \n\	97	mov lr, #0 \n\
94	msr cpsr_c, r0 \n\	98	msr cpsr_c, r0 \n\
95	\n\	99	\n\
96	ldmfd r13!, {r4, r5, r6, r7} \n\	100	ldmfd r13!, {r4, r5, r6, r7} \n\
97	stmfd r1!, {r4, r5, r6} \n\	101	stmfd r1!, {r4, r5, r6} \n\
98	stmfd r1!, {r7} \n\	102	stmfd r1!, {r7} \n\
99	stmfd r1!, {r2} \n\	103	stmfd r1!, {r2} \n\
100	stmfd r1!, {r3} \n\	104	stmfd r1!, {r3} \n\
101	mrs r0, spsr \n\	105	mrs r0, spsr \n\
102	stmfd r1!, {r0} \n\	106	stmfd r1!, {r0} \n\
103	mov r13, r1 \n\	107	mov r13, r1 \n\
104	2:"	108	2:"
105	);	109	);
106	}	110	}
107		111
108		112
109	inline static void load_regs()	113	inline static void load_regs()
110	{	114	{
111	asm volatile( "ldmfd r13!, {r0} \n\	115	asm volatile( "ldmfd r13!, {r0} \n\
112	msr spsr, r0 \n\	116	msr spsr, r0 \n\
113	and r0, r0, #0x1f \n\	117	and r0, r0, #0x1f \n\
114	cmp r0, #0x10 \n\	118	cmp r0, #0x10 \n\
115	bne 3f \n\	119	bne 3f \n\
116	\n\	120	\n\
117	@return to user mode \n\	121	@return to user mode \n\
118	ldmfd r13!, {r13, lr}^ \n\	122	ldmfd r13!, {r13, lr}^ \n\
119	b 4f \n\	123	b 4f \n\
120	\n\	124	\n\
121	@return to non-user mode \n\	125	@return to non-user mode \n\
122	3: \n\	126	3: \n\
123	ldmfd r13!, {r1, r2} \n\	127	ldmfd r13!, {r1, r2} \n\
124	mrs r3, cpsr \n\	128	mrs r3, cpsr \n\
125	bic r3, r3, #0x1f \n\	129	bic r3, r3, #0x1f \n\
126	orr r3, r3, r0 \n\	130	orr r3, r3, r0 \n\
127	mrs r0, cpsr \n\	131	mrs r0, cpsr \n\
128	msr cpsr_c, r3 \n\	132	msr cpsr_c, r3 \n\
129	\n\	133	\n\
130	mov r13, r1 \n\	134	mov r13, r1 \n\
131	mov lr, r2 \n\	135	mov lr, r2 \n\
132	msr cpsr_c, r0 \n\	136	msr cpsr_c, r0 \n\
133	\n\	137	\n\
134	@actual return \n\	138	@actual return \n\
135	4: ldmfd r13, {r0-r12, pc}^"	139	4: ldmfd r13, {r0-r12, pc}^"
136	);	140	);
137	}	141	}
138		142
139		143
140		144
141	/*#define SAVE_REGS_TO_STACK \	145	/*#define SAVE_REGS_TO_STACK \
142	asm("stmfd r13!, {r0-r12, r13, lr}"); \	146	asm("stmfd r13!, {r0-r12, r13, lr}"); \
143	asm("mrs r14, spsr"); \	147	asm("mrs r14, spsr"); \
144	asm("stmfd r13!, {r14}");	148	asm("stmfd r13!, {r14}");
145	*/	149	*/
146		150
147		151
148	#define CALL_EXC_DISPATCH(exception) \	152	#define CALL_EXC_DISPATCH(exception) \
149	asm("mov r0, %0" : : "i" (exception)); \	153	asm("mov r0, %0" : : "i" (exception)); \
150	asm("mov r1, r13"); \	154	asm("mov r1, r13"); \
151	asm("bl exc_dispatch");	155	asm("bl exc_dispatch");
152		156
153		157
154	/**Loads registers from the stack and resets SPSR before exitting exception	158	/**Loads registers from the stack and resets SPSR before exitting exception
155	* handler.	159	* handler.
156		160
157	#define LOAD_REGS_FROM_STACK \	161	#define LOAD_REGS_FROM_STACK \
158	asm("ldmfd r13!, {r14}"); \	162	asm("ldmfd r13!, {r14}"); \
159	asm("msr spsr, r14"); \	163	asm("msr spsr, r14"); \
160	asm("ldmfd r13!, {r0-r12, r13, pc}^");	164	asm("ldmfd r13!, {r0-r12, r13, pc}^");
161	*/	165	*/
162		166
163		167
164	/** General exception handler.	168	/** General exception handler.
165	* Stores registers, dispatches the exception,	169	* Stores registers, dispatches the exception,
166	* and finally restores registers and returns from exception processing.	170	* and finally restores registers and returns from exception processing.
-		171	*
-		172	* @param exception Exception number.
167	*/	173	*/
168		-
169	#define PROCESS_EXCEPTION(exception) \	174	#define PROCESS_EXCEPTION(exception) \
170	setup_stack_and_save_regs(); \	175	setup_stack_and_save_regs(); \
171	CALL_EXC_DISPATCH(exception) \	176	CALL_EXC_DISPATCH(exception) \
172	load_regs();	177	load_regs();
173		178
174	/* #define PROCESS_EXCEPTION(exception) \	179	/* #define PROCESS_EXCEPTION(exception) \
175	SAVE_REGS_TO_STACK \	180	SAVE_REGS_TO_STACK \
176	CALL_EXC_DISPATCH(exception) \	181	CALL_EXC_DISPATCH(exception) \
177	LOAD_REGS_FROM_STACK*/	182	LOAD_REGS_FROM_STACK*/
178		183
-		184
179	/** Updates specified exception vector to jump to given handler.	185	/** Updates specified exception vector to jump to given handler.
180	* Addresses of handlers are stored in memory following exception vectors.	186	* Addresses of handlers are stored in memory following exception vectors.
181	*/	187	*/
182	static void install_handler (unsigned handler_addr, unsigned* vector)	188	static void install_handler (unsigned handler_addr, unsigned* vector)
183	{	189	{
184	/* relative address (related to exc. vector) of the word	190	/* relative address (related to exc. vector) of the word
185	* where handler's address is stored	191	* where handler's address is stored
186	*/	192	*/
187	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	193	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
188		194
189	/* make it LDR instruction and store at exception vector */	195	/* make it LDR instruction and store at exception vector */
190	*vector = handler_address_ptr \| LDR_OPCODE;	196	*vector = handler_address_ptr \| LDR_OPCODE;
191		197
192	/* store handler's address */	198	/* store handler's address */
193	*(vector + EXC_VECTORS) = handler_addr;	199	*(vector + EXC_VECTORS) = handler_addr;
194		200
195	}	201	}
196		202
197		203
-		204	/** Low-level Reset Exception handler. */
198	static void reset_exception_entry()	205	static void reset_exception_entry()
199	{	206	{
200	PROCESS_EXCEPTION(EXC_RESET);	207	PROCESS_EXCEPTION(EXC_RESET);
201	}	208	}
202		209
-		210
203	/** Low-level Software Interrupt Exception handler */	211	/** Low-level Software Interrupt Exception handler. */
204	static void swi_exception_entry()	212	static void swi_exception_entry()
205	{	213	{
206	PROCESS_EXCEPTION(EXC_SWI);	214	PROCESS_EXCEPTION(EXC_SWI);
207	}	215	}
208		216
-		217
209	/** Low-level Undefined Instruction Exception handler */	218	/** Low-level Undefined Instruction Exception handler. */
210	static void undef_instr_exception_entry()	219	static void undef_instr_exception_entry()
211	{	220	{
212	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	221	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
213	}	222	}
214		223
-		224
215	/** Low-level Fast Interrupt Exception handler */	225	/** Low-level Fast Interrupt Exception handler. */
216	static void fiq_exception_entry()	226	static void fiq_exception_entry()
217	{	227	{
218	PROCESS_EXCEPTION(EXC_FIQ);	228	PROCESS_EXCEPTION(EXC_FIQ);
219	}	229	}
220		230
-		231
221	/** Low-level Prefetch Abort Exception handler */	232	/** Low-level Prefetch Abort Exception handler. */
222	static void prefetch_abort_exception_entry()	233	static void prefetch_abort_exception_entry()
223	{	234	{
224	asm("sub lr, lr, #4");	235	asm("sub lr, lr, #4");
225	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	236	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
226	}	237	}
227		238
-		239
228	/** Low-level Data Abort Exception handler */	240	/** Low-level Data Abort Exception handler. */
229	static void data_abort_exception_entry()	241	static void data_abort_exception_entry()
230	{	242	{
231	asm("sub lr, lr, #8");	243	asm("sub lr, lr, #8");
232	PROCESS_EXCEPTION(EXC_DATA_ABORT);	244	PROCESS_EXCEPTION(EXC_DATA_ABORT);
233	}	245	}
234		246
235		247
236	/** Low-level Interrupt Exception handler */	248	/** Low-level Interrupt Exception handler. */
237	static void irq_exception_entry()	249	static void irq_exception_entry()
238	{	250	{
239	asm("sub lr, lr, #4");	251	asm("sub lr, lr, #4");
240	PROCESS_EXCEPTION(EXC_IRQ);	252	PROCESS_EXCEPTION(EXC_IRQ);
241	}	253	}
242		254
-		255
243	/** Software Interrupt handler.	256	/** Software Interrupt handler.
244	*	257	*
245	* Dispatches the syscall.	258	* Dispatches the syscall.
246	*/	259	*/
247	static void swi_exception(int exc_no, istate_t *istate)	260	static void swi_exception(int exc_no, istate_t *istate)
248	{	261	{
249	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,	262	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
250	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);	263	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
251		264
252	istate->r0 = syscall_handler(	265	istate->r0 = syscall_handler(
253	istate->r0,	266	istate->r0,
254	istate->r1,	267	istate->r1,
255	istate->r2,	268	istate->r2,
256	istate->r3,	269	istate->r3,
257	istate->r4);	270	istate->r4);
258	}	271	}
259		272
-		273
260	/** Interrupt Exception handler.	274	/** Interrupt Exception handler.
261	*	275	*
262	* Determines the sources of interrupt, and calls their handlers.	276	* Determines the sources of interrupt, and calls their handlers.
263	*/	277	*/
264	static void irq_exception(int exc_no, istate_t *istate)	278	static void irq_exception(int exc_no, istate_t *istate)
265	{	279	{
266	machine_irq_exception(exc_no, istate);	280	machine_irq_exception(exc_no, istate);
267	}	281	}
268		282
-		283
269	/** Fills exception vectors with appropriate exception handlers.	284	/** Fills exception vectors with appropriate exception handlers. */
270	*/	-
271	void install_exception_handlers(void)	285	void install_exception_handlers(void)
272	{	286	{
273	install_handler((unsigned)reset_exception_entry,	287	install_handler((unsigned)reset_exception_entry,
274	(unsigned*)EXC_RESET_VEC);	288	(unsigned*)EXC_RESET_VEC);
275		289
276	install_handler((unsigned)undef_instr_exception_entry,	290	install_handler((unsigned)undef_instr_exception_entry,
277	(unsigned*)EXC_UNDEF_INSTR_VEC);	291	(unsigned*)EXC_UNDEF_INSTR_VEC);
278		292
279	install_handler((unsigned)swi_exception_entry,	293	install_handler((unsigned)swi_exception_entry,
280	(unsigned*)EXC_SWI_VEC);	294	(unsigned*)EXC_SWI_VEC);
281		295
282	install_handler((unsigned)prefetch_abort_exception_entry,	296	install_handler((unsigned)prefetch_abort_exception_entry,
283	(unsigned*)EXC_PREFETCH_ABORT_VEC);	297	(unsigned*)EXC_PREFETCH_ABORT_VEC);
284		298
285	install_handler((unsigned)data_abort_exception_entry,	299	install_handler((unsigned)data_abort_exception_entry,
286	(unsigned*)EXC_DATA_ABORT_VEC);	300	(unsigned*)EXC_DATA_ABORT_VEC);
287		301
288	install_handler((unsigned)irq_exception_entry,	302	install_handler((unsigned)irq_exception_entry,
289	(unsigned*)EXC_IRQ_VEC);	303	(unsigned*)EXC_IRQ_VEC);
290		304
291	install_handler((unsigned)fiq_exception_entry,	305	install_handler((unsigned)fiq_exception_entry,
292	(unsigned*)EXC_FIQ_VEC);	306	(unsigned*)EXC_FIQ_VEC);
293	}	307	}
294		308
-		309
295	#ifdef HIGH_EXCEPTION_VECTORS	310	#ifdef HIGH_EXCEPTION_VECTORS
296	/** Activates using high exception vectors addresses. */	311	/** Activates use of high exception vectors addresses. */
297	static void high_vectors()	312	static void high_vectors()
298	{	313	{
299	uint32_t control_reg;	314	uint32_t control_reg;
300		315
301	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	316	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
302		317
303	//switch on the high vectors bit	318	//switch on the high vectors bit
304	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	319	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
305		320
306	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	321	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
307	}	322	}
308	#endif	323	#endif
309		324
310		325
311	/** Initializes exception handling.	326	/** Initializes exception handling.
312	*	327	*
313	* Installs low-level exception handlers and then registers	328	* Installs low-level exception handlers and then registers
314	* exceptions and their handlers to kernel exception dispatcher.	329	* exceptions and their handlers to kernel exception dispatcher.
315	*/	330	*/
316	void exception_init(void)	331	void exception_init(void)
317	{	332	{
318	#ifdef HIGH_EXCEPTION_VECTORS	333	#ifdef HIGH_EXCEPTION_VECTORS
319	high_vectors();	334	high_vectors();
320	#endif	335	#endif
321	install_exception_handlers();	336	install_exception_handlers();
322		337
323	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	338	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
324	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);	339	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
325	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	340	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
326	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	341	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
327	/* TODO add next */	342	/* TODO add next */
328	}	343	}
329		344
330		345
331	/** Sets stack pointers in all supported exception modes.	346	/** Sets stack pointers in all supported exception modes. */
332	*/	-
333	void setup_exception_stacks()	347	void setup_exception_stacks()
334	{	348	{
335	/* switch to particular mode and set "r13" there */	349	/* switch to particular mode and set "r13" there */
336		350
337	uint32_t cspr = current_status_reg_read();	351	uint32_t cspr = current_status_reg_read();
338		352
339	/* IRQ stack */	353	/* IRQ stack */
340	current_status_reg_control_write(	354	current_status_reg_control_write(
341	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE	355	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE
342	);	356	);
343	asm("ldr r13, =exc_stack");	357	asm("ldr r13, =exc_stack");
344		358
345	/* abort stack */	359	/* abort stack */
346	current_status_reg_control_write(	360	current_status_reg_control_write(
347	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE	361	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE
348	);	362	);
349	asm("ldr r13, =exc_stack");	363	asm("ldr r13, =exc_stack");
350		364
351	/* TODO if you want to test other exceptions than IRQ,	365	/* TODO if you want to test other exceptions than IRQ,
352	make stack analogous to irq_stack (in start.S),	366	make stack analogous to irq_stack (in start.S),
353	and then set stack pointer here */	367	and then set stack pointer here */
354		368
355	current_status_reg_control_write(cspr);	369	current_status_reg_control_write(cspr);
356	}	370	}
357		371
358		372
359	/** Prints #istate_t structure content.	373	/** Prints #istate_t structure content.
360	*	374	*
361	* @param istate Structure to be printed.	375	* @param istate Structure to be printed.
362	*/	376	*/
363	void print_istate(istate_t *istate)	377	void print_istate(istate_t *istate)
364	{	378	{
365	dprintf("istate dump:\n");	379	dprintf("istate dump:\n");
366		380
367	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	381	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
368	istate->r0, istate->r1, istate->r2, istate->r3);	382	istate->r0, istate->r1, istate->r2, istate->r3);
369	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	383	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
370	istate->r4, istate->r5, istate->r6, istate->r7);	384	istate->r4, istate->r5, istate->r6, istate->r7);
371	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	385	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
372	istate->r8, istate->r9, istate->r10, istate->r11);	386	istate->r8, istate->r9, istate->r10, istate->r11);
373	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	387	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
374	istate->r12, istate->sp, istate->lr, istate->spsr);	388	istate->r12, istate->sp, istate->lr, istate->spsr);
375		389
376	dprintf(" pc: %x\n", istate->pc);	390	dprintf(" pc: %x\n", istate->pc);
377	}	391	}
378		392
379		393
380	/** @}	394	/** @}
381	*/	395	*/
382		396

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(root)/trunk/kernel/arch/arm32/src/exception.c @ 2465 – Rev 2326 → 2329