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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <ipc/irq.h> |
36 | #include <ipc/irq.h> |
37 | #include <console/chardev.h> |
37 | #include <console/chardev.h> |
38 | #include <arch/drivers/gxemul.h> |
38 | #include <arch/drivers/gxemul.h> |
39 | #include <console/console.h> |
39 | #include <console/console.h> |
40 | #include <sysinfo/sysinfo.h> |
40 | #include <sysinfo/sysinfo.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <ddi/device.h> |
42 | #include <ddi/device.h> |
43 | #include <mm/page.h> |
43 | #include <mm/page.h> |
- | 44 | #include <arch/machine.h> |
|
44 | 45 | ||
45 | /** Address of devices. */ |
46 | /** Address of devices. */ |
46 | #define GXEMUL_VIDEORAM 0x10000000 |
47 | #define GXEMUL_VIDEORAM 0x10000000 |
47 | #define GXEMUL_KBD 0x10000000 |
48 | #define GXEMUL_KBD 0x10000000 |
48 | #define GXEMUL_RTC 0x15000000 |
49 | #define GXEMUL_RTC 0x15000000 |
49 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
50 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
50 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
51 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
51 | #define GXEMUL_IRQC 0x16000000 |
52 | #define GXEMUL_IRQC 0x16000000 |
52 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
53 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
53 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
54 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
54 | #define GXEMUL_MP 0x11000000 |
55 | #define GXEMUL_MP 0x11000000 |
55 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
56 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
56 | 57 | ||
57 | 58 | ||
58 | /** IRQs */ |
59 | /** IRQs */ |
59 | #define GXEMUL_KBD_IRQ 2 |
60 | #define GXEMUL_KBD_IRQ 2 |
60 | #define GXEMUL_TIMER_IRQ 4 |
61 | #define GXEMUL_TIMER_IRQ 4 |
61 | 62 | ||
62 | static gxemul_hw_map_t gxemul_hw_map; |
63 | static gxemul_hw_map_t gxemul_hw_map; |
63 | static chardev_t console; |
64 | static chardev_t console; |
64 | static irq_t gxemul_irq; |
65 | static irq_t gxemul_irq; |
65 | static irq_t gxemul_timer_irq; |
66 | static irq_t gxemul_timer_irq; |
66 | 67 | ||
67 | static void gxemul_write(chardev_t *dev, const char ch); |
68 | static void gxemul_write(chardev_t *dev, const char ch); |
68 | static void gxemul_enable(chardev_t *dev); |
69 | static void gxemul_enable(chardev_t *dev); |
69 | static void gxemul_disable(chardev_t *dev); |
70 | static void gxemul_disable(chardev_t *dev); |
70 | static char gxemul_do_read(chardev_t *dev); |
71 | static char gxemul_do_read(chardev_t *dev); |
71 | 72 | ||
72 | static chardev_operations_t gxemul_ops = { |
73 | static chardev_operations_t gxemul_ops = { |
73 | .resume = gxemul_enable, |
74 | .resume = gxemul_enable, |
74 | .suspend = gxemul_disable, |
75 | .suspend = gxemul_disable, |
75 | .write = gxemul_write, |
76 | .write = gxemul_write, |
76 | .read = gxemul_do_read, |
77 | .read = gxemul_do_read, |
77 | }; |
78 | }; |
78 | 79 | ||
79 | 80 | ||
80 | /** Initializes #gxemul_hw_map. */ |
81 | /** Initializes #gxemul_hw_map. */ |
81 | void gxemul_hw_map_init(void) |
82 | void machine_hw_map_init(void) |
82 | { |
83 | { |
83 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
84 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
84 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
85 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
85 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
86 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
86 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
87 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
87 | 88 | ||
88 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
89 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
89 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
90 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
90 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
91 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
91 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
92 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
92 | 93 | ||
93 | } |
94 | } |
94 | 95 | ||
95 | /** Putchar that works with gxemul */ |
96 | /** Putchar that works with gxemul */ |
96 | void gxemul_write(chardev_t *dev, const char ch) |
97 | void gxemul_write(chardev_t *dev, const char ch) |
97 | { |
98 | { |
98 | *((char *) gxemul_hw_map.videoram) = ch; |
99 | *((char *) gxemul_hw_map.videoram) = ch; |
99 | } |
100 | } |
100 | 101 | ||
101 | /* Called from getc(). */ |
102 | /* Called from getc(). */ |
102 | void gxemul_enable(chardev_t *dev) |
103 | void gxemul_enable(chardev_t *dev) |
103 | { |
104 | { |
104 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
105 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
105 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
106 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
106 | } |
107 | } |
107 | 108 | ||
108 | /* Called from getc(). */ |
109 | /* Called from getc(). */ |
109 | void gxemul_disable(chardev_t *dev) |
110 | void gxemul_disable(chardev_t *dev) |
110 | { |
111 | { |
111 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
112 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
112 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
113 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
113 | } |
114 | } |
114 | 115 | ||
115 | /** Read character using polling, assume interrupts disabled */ |
116 | /** Read character using polling, assume interrupts disabled */ |
116 | static char gxemul_do_read(chardev_t *dev) |
117 | static char gxemul_do_read(chardev_t *dev) |
117 | { |
118 | { |
118 | char ch; |
119 | char ch; |
119 | 120 | ||
120 | while (1) { |
121 | while (1) { |
121 | ch = *((volatile char *) gxemul_hw_map.kbd); |
122 | ch = *((volatile char *) gxemul_hw_map.kbd); |
122 | if (ch) { |
123 | if (ch) { |
123 | if (ch == '\r') |
124 | if (ch == '\r') |
124 | return '\n'; |
125 | return '\n'; |
125 | if (ch == 0x7f) |
126 | if (ch == 0x7f) |
126 | return '\b'; |
127 | return '\b'; |
127 | return ch; |
128 | return ch; |
128 | } |
129 | } |
129 | } |
130 | } |
130 | } |
131 | } |
131 | 132 | ||
132 | /** Process keyboard interrupt. */ |
133 | /** Process keyboard interrupt. */ |
133 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
134 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
134 | { |
135 | { |
135 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
136 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
136 | ipc_irq_send_notif(irq); |
137 | ipc_irq_send_notif(irq); |
137 | else { |
138 | else { |
138 | char ch = 0; |
139 | char ch = 0; |
139 | 140 | ||
140 | ch = *((char *) gxemul_hw_map.kbd); |
141 | ch = *((char *) gxemul_hw_map.kbd); |
141 | if (ch =='\r') |
142 | if (ch =='\r') |
142 | ch = '\n'; |
143 | ch = '\n'; |
143 | if (ch == 0x7f) |
144 | if (ch == 0x7f) |
144 | ch = '\b'; |
145 | ch = '\b'; |
145 | //chardev_push_character(&console, ch); |
146 | //chardev_push_character(&console, ch); |
146 | printf("%c", ch); |
147 | printf("%c", ch); |
147 | } |
148 | } |
148 | } |
149 | } |
149 | 150 | ||
150 | static irq_ownership_t gxemul_claim(void) |
151 | static irq_ownership_t gxemul_claim(void) |
151 | { |
152 | { |
152 | return IRQ_ACCEPT; |
153 | return IRQ_ACCEPT; |
153 | } |
154 | } |
154 | 155 | ||
155 | void gxemul_kbd_grab(void) |
156 | void machine_grab_console(void) |
156 | { |
157 | { |
157 | ipl_t ipl = interrupts_disable(); |
158 | ipl_t ipl = interrupts_disable(); |
158 | spinlock_lock(&gxemul_irq.lock); |
159 | spinlock_lock(&gxemul_irq.lock); |
159 | gxemul_irq.notif_cfg.notify = false; |
160 | gxemul_irq.notif_cfg.notify = false; |
160 | spinlock_unlock(&gxemul_irq.lock); |
161 | spinlock_unlock(&gxemul_irq.lock); |
161 | interrupts_restore(ipl); |
162 | interrupts_restore(ipl); |
162 | } |
163 | } |
163 | 164 | ||
164 | void gxemul_kbd_release(void) |
165 | void machine_release_console(void) |
165 | { |
166 | { |
166 | ipl_t ipl = interrupts_disable(); |
167 | ipl_t ipl = interrupts_disable(); |
167 | spinlock_lock(&gxemul_irq.lock); |
168 | spinlock_lock(&gxemul_irq.lock); |
168 | if (gxemul_irq.notif_cfg.answerbox) |
169 | if (gxemul_irq.notif_cfg.answerbox) |
169 | gxemul_irq.notif_cfg.notify = true; |
170 | gxemul_irq.notif_cfg.notify = true; |
170 | spinlock_unlock(&gxemul_irq.lock); |
171 | spinlock_unlock(&gxemul_irq.lock); |
171 | interrupts_restore(ipl); |
172 | interrupts_restore(ipl); |
172 | } |
173 | } |
173 | 174 | ||
174 | 175 | ||
175 | /** Return console object representing gxemul console */ |
176 | /** Return console object representing gxemul console */ |
176 | void gxemul_console(devno_t devno) |
177 | void machine_console_init(devno_t devno) |
177 | { |
178 | { |
178 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
179 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
179 | stdin = &console; |
180 | stdin = &console; |
180 | stdout = &console; |
181 | stdout = &console; |
181 | 182 | ||
182 | irq_initialize(&gxemul_irq); |
183 | irq_initialize(&gxemul_irq); |
183 | gxemul_irq.devno = devno; |
184 | gxemul_irq.devno = devno; |
184 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
185 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
185 | gxemul_irq.claim = gxemul_claim; |
186 | gxemul_irq.claim = gxemul_claim; |
186 | gxemul_irq.handler = gxemul_irq_handler; |
187 | gxemul_irq.handler = gxemul_irq_handler; |
187 | irq_register(&gxemul_irq); |
188 | irq_register(&gxemul_irq); |
188 | 189 | ||
189 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
190 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
190 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
191 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
191 | 192 | ||
192 | sysinfo_set_item_val("kbd", NULL, true); |
193 | sysinfo_set_item_val("kbd", NULL, true); |
193 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
194 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
194 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
195 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
195 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
196 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
196 | } |
197 | } |
197 | 198 | ||
198 | /** Return the mask of active interrupts. */ |
199 | /** Return the mask of active interrupts. */ |
199 | inline uint32_t gxemul_irqc_get_sources(void) |
200 | inline uint32_t gxemul_irqc_get_sources(void) |
200 | { |
201 | { |
201 | return *(uint32_t*) gxemul_hw_map.irqc; |
202 | return *(uint32_t*) gxemul_hw_map.irqc; |
202 | } |
203 | } |
203 | 204 | ||
204 | /** Masks interrupt. |
205 | /** Masks interrupt. |
205 | * |
206 | * |
206 | * @param irq interrupt number |
207 | * @param irq interrupt number |
207 | */ |
208 | */ |
208 | inline void gxemul_irqc_mask(uint32_t irq) |
209 | inline void gxemul_irqc_mask(uint32_t irq) |
209 | { |
210 | { |
210 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
211 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
211 | } |
212 | } |
212 | 213 | ||
213 | /** Unmasks interrupt. |
214 | /** Unmasks interrupt. |
214 | * |
215 | * |
215 | * @param irq interrupt number |
216 | * @param irq interrupt number |
216 | */ |
217 | */ |
217 | inline void gxemul_irqc_unmask(uint32_t irq) |
218 | inline void gxemul_irqc_unmask(uint32_t irq) |
218 | { |
219 | { |
219 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
220 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
220 | } |
221 | } |
221 | 222 | ||
222 | 223 | ||
223 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
224 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
224 | * |
225 | * |
225 | * @param frequency interrupts frequency (0 disables RTC) |
226 | * @param frequency interrupts frequency (0 disables RTC) |
226 | */ |
227 | */ |
227 | void gxemul_timer_start(uint32_t frequency) |
228 | void gxemul_timer_start(uint32_t frequency) |
228 | { |
229 | { |
229 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
230 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
230 | } |
231 | } |
231 | 232 | ||
232 | static irq_ownership_t gxemul_timer_claim(void) |
233 | static irq_ownership_t gxemul_timer_claim(void) |
233 | { |
234 | { |
234 | return IRQ_ACCEPT; |
235 | return IRQ_ACCEPT; |
235 | } |
236 | } |
236 | 237 | ||
237 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
238 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
238 | { |
239 | { |
239 | /* TODO time drifts ?? |
240 | /* TODO time drifts ?? |
240 | unsigned long drift; |
241 | unsigned long drift; |
241 | 242 | ||
242 | drift = cp0_count_read() - nextcount; |
243 | drift = cp0_count_read() - nextcount; |
243 | while (drift > cp0_compare_value) { |
244 | while (drift > cp0_compare_value) { |
244 | drift -= cp0_compare_value; |
245 | drift -= cp0_compare_value; |
245 | CPU->missed_clock_ticks++; |
246 | CPU->missed_clock_ticks++; |
246 | } |
247 | } |
247 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
248 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
248 | cp0_compare_write(nextcount); |
249 | cp0_compare_write(nextcount); |
249 | */ |
250 | */ |
250 | 251 | ||
251 | /* |
252 | /* |
252 | * We are holding a lock which prevents preemption. |
253 | * We are holding a lock which prevents preemption. |
253 | * Release the lock, call clock() and reacquire the lock again. |
254 | * Release the lock, call clock() and reacquire the lock again. |
254 | */ |
255 | */ |
255 | spinlock_unlock(&irq->lock); |
256 | spinlock_unlock(&irq->lock); |
256 | //clock(); |
257 | //clock(); |
257 | puts(" "); |
258 | puts(" "); |
258 | spinlock_lock(&irq->lock); |
259 | spinlock_lock(&irq->lock); |
259 | 260 | ||
260 | /* acknowledge tick */ |
261 | /* acknowledge tick */ |
261 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
262 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
262 | 263 | ||
263 | /* TODO what's that? * |
264 | /* TODO what's that? * |
264 | if (virtual_timer_fnc != NULL) |
265 | if (virtual_timer_fnc != NULL) |
265 | virtual_timer_fnc(); |
266 | virtual_timer_fnc(); |
266 | */ |
267 | */ |
267 | } |
268 | } |
268 | 269 | ||
269 | /** |
270 | /** |
270 | * Initializes and registers timer interrupt handler. |
271 | * Initializes and registers timer interrupt handler. |
271 | */ |
272 | */ |
272 | void gxemul_timer_irq_init() |
273 | void gxemul_timer_irq_init() |
273 | { |
274 | { |
274 | irq_initialize(&gxemul_timer_irq); |
275 | irq_initialize(&gxemul_timer_irq); |
275 | gxemul_timer_irq.devno = device_assign_devno(); |
276 | gxemul_timer_irq.devno = device_assign_devno(); |
276 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
277 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
277 | gxemul_timer_irq.claim = gxemul_timer_claim; |
278 | gxemul_timer_irq.claim = gxemul_timer_claim; |
278 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
279 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
279 | 280 | ||
280 | irq_register(&gxemul_timer_irq); |
281 | irq_register(&gxemul_timer_irq); |
281 | } |
282 | } |
282 | 283 | ||
- | 284 | void machine_timer_irq_start() |
|
- | 285 | { |
|
- | 286 | gxemul_timer_irq_init(); |
|
- | 287 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
|
- | 288 | } |
|
- | 289 | ||
283 | size_t gxemul_get_memory_size(void) |
290 | size_t machine_get_memory_size(void) |
284 | { |
291 | { |
285 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
292 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
286 | } |
293 | } |
287 | 294 | ||
288 | void gxemul_debug_putc(char ch) { |
295 | void gxemul_debug_putc(char ch) { |
289 | *((volatile char *) GXEMUL_KBD) = ch; |
296 | *((volatile char *) GXEMUL_KBD) = ch; |
290 | } |
297 | } |
291 | 298 | ||
292 | /** @} |
299 | /** @} |
293 | */ |
300 | */ |
294 | 301 |