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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2007 Michal Kebrt |
2 | * Copyright (c) 2007 Michal Kebrt |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | * @brief Declarations of functions implemented in assembly. |
33 | * @brief Declarations of functions implemented in assembly. |
| 34 | */ |
34 | */ |
| 35 | 35 | ||
| 36 | #ifndef KERN_arm32_ASM_H_ |
36 | #ifndef KERN_arm32_ASM_H_ |
| 37 | #define KERN_arm32_ASM_H_ |
37 | #define KERN_arm32_ASM_H_ |
| 38 | 38 | ||
| 39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
| 40 | #include <arch/stack.h> |
40 | #include <arch/stack.h> |
| 41 | #include <config.h> |
41 | #include <config.h> |
| 42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
| 43 | 43 | ||
| 44 | /** No such instruction on ARM to sleep CPU. */ |
44 | /** No such instruction on ARM to sleep CPU. */ |
| 45 | static inline void cpu_sleep(void) |
45 | static inline void cpu_sleep(void) |
| 46 | { |
46 | { |
| 47 | } |
47 | } |
| 48 | 48 | ||
| 49 | static inline void pio_write_8(ioport8_t *port, uint8_t v) |
49 | static inline void pio_write_8(ioport8_t *port, uint8_t v) |
| 50 | { |
50 | { |
| 51 | *port = v; |
51 | *port = v; |
| 52 | } |
52 | } |
| 53 | 53 | ||
| 54 | static inline void pio_write_16(ioport16_t *port, uint16_t v) |
54 | static inline void pio_write_16(ioport16_t *port, uint16_t v) |
| 55 | { |
55 | { |
| 56 | *port = v; |
56 | *port = v; |
| 57 | } |
57 | } |
| 58 | 58 | ||
| 59 | static inline void pio_write_32(ioport32_t *port, uint32_t v) |
59 | static inline void pio_write_32(ioport32_t *port, uint32_t v) |
| 60 | { |
60 | { |
| 61 | *port = v; |
61 | *port = v; |
| 62 | } |
62 | } |
| 63 | 63 | ||
| 64 | static inline uint8_t pio_read_8(ioport8_t *port) |
64 | static inline uint8_t pio_read_8(ioport8_t *port) |
| 65 | { |
65 | { |
| 66 | return *port; |
66 | return *port; |
| 67 | } |
67 | } |
| 68 | 68 | ||
| 69 | static inline uint16_t pio_read_16(ioport16_t *port) |
69 | static inline uint16_t pio_read_16(ioport16_t *port) |
| 70 | { |
70 | { |
| 71 | return *port; |
71 | return *port; |
| 72 | } |
72 | } |
| 73 | 73 | ||
| 74 | static inline uint32_t pio_read_32(ioport32_t *port) |
74 | static inline uint32_t pio_read_32(ioport32_t *port) |
| 75 | { |
75 | { |
| 76 | return *port; |
76 | return *port; |
| 77 | } |
77 | } |
| 78 | 78 | ||
| 79 | /** Return base address of current stack. |
79 | /** Return base address of current stack. |
| 80 | * |
80 | * |
| 81 | * Return the base address of the current stack. |
81 | * Return the base address of the current stack. |
| 82 | * The stack is assumed to be STACK_SIZE bytes long. |
82 | * The stack is assumed to be STACK_SIZE bytes long. |
| 83 | * The stack must start on page boundary. |
83 | * The stack must start on page boundary. |
| - | 84 | * |
|
| 84 | */ |
85 | */ |
| 85 | static inline uintptr_t get_stack_base(void) |
86 | static inline uintptr_t get_stack_base(void) |
| 86 | { |
87 | { |
| 87 | uintptr_t v; |
88 | uintptr_t v; |
| 88 | asm volatile ( |
89 | asm volatile ( |
| 89 | "and %0, sp, %1\n" |
90 | "and %[v], sp, %[size]\n" |
| 90 | : "=r" (v) |
91 | : [v] "=r" (v) |
| 91 | : "r" (~(STACK_SIZE - 1)) |
92 | : [size] "r" (~(STACK_SIZE - 1)) |
| 92 | ); |
93 | ); |
| 93 | return v; |
94 | return v; |
| 94 | } |
95 | } |
| 95 | 96 | ||
| 96 | extern void cpu_halt(void); |
97 | extern void cpu_halt(void); |
| 97 | extern void asm_delay_loop(uint32_t t); |
98 | extern void asm_delay_loop(uint32_t t); |
| 98 | extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
99 | extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
| 99 | uintptr_t entry); |
100 | uintptr_t entry); |
| 100 | 101 | ||
| 101 | #endif |
102 | #endif |
| 102 | 103 | ||
| 103 | /** @} |
104 | /** @} |
| 104 | */ |
105 | */ |
| 105 | 106 | ||