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1 | /* |
1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
3 | * Copyright (c) 2005-2006 Ondrej Palkovsky |
3 | * Copyright (c) 2005-2006 Ondrej Palkovsky |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup amd64 |
30 | /** @addtogroup amd64 |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/pm.h> |
36 | #include <arch/pm.h> |
37 | #include <arch/asm.h> |
37 | #include <arch/asm.h> |
38 | #include <mm/as.h> |
38 | #include <mm/as.h> |
39 | #include <mm/frame.h> |
39 | #include <mm/frame.h> |
40 | #include <memstr.h> |
40 | #include <memstr.h> |
41 | #include <mm/slab.h> |
41 | #include <mm/slab.h> |
42 | 42 | ||
43 | /* |
43 | /* |
44 | * There is no segmentation in long mode so we set up flat mode. In this |
44 | * There is no segmentation in long mode so we set up flat mode. In this |
45 | * mode, we use, for each privilege level, two segments spanning the |
45 | * mode, we use, for each privilege level, two segments spanning the |
46 | * whole memory. One is for code and one is for data. |
46 | * whole memory. One is for code and one is for data. |
47 | */ |
47 | */ |
48 | 48 | ||
49 | descriptor_t gdt[GDT_ITEMS] = { |
49 | descriptor_t gdt[GDT_ITEMS] = { |
50 | /* NULL descriptor */ |
50 | /* NULL descriptor */ |
51 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
51 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
52 | /* KTEXT descriptor */ |
52 | /* KTEXT descriptor */ |
53 | { .limit_0_15 = 0xffff, |
53 | { .limit_0_15 = 0xffff, |
54 | .base_0_15 = 0, |
54 | .base_0_15 = 0, |
55 | .base_16_23 = 0, |
55 | .base_16_23 = 0, |
56 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE , |
56 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE , |
57 | .limit_16_19 = 0xf, |
57 | .limit_16_19 = 0xf, |
58 | .available = 0, |
58 | .available = 0, |
59 | .longmode = 1, |
59 | .longmode = 1, |
60 | .special = 0, |
60 | .special = 0, |
61 | .granularity = 1, |
61 | .granularity = 1, |
62 | .base_24_31 = 0 }, |
62 | .base_24_31 = 0 }, |
63 | /* KDATA descriptor */ |
63 | /* KDATA descriptor */ |
64 | { .limit_0_15 = 0xffff, |
64 | { .limit_0_15 = 0xffff, |
65 | .base_0_15 = 0, |
65 | .base_0_15 = 0, |
66 | .base_16_23 = 0, |
66 | .base_16_23 = 0, |
67 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, |
67 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, |
68 | .limit_16_19 = 0xf, |
68 | .limit_16_19 = 0xf, |
69 | .available = 0, |
69 | .available = 0, |
70 | .longmode = 0, |
70 | .longmode = 0, |
71 | .special = 0, |
71 | .special = 0, |
72 | .granularity = 1, |
72 | .granularity = 1, |
73 | .base_24_31 = 0 }, |
73 | .base_24_31 = 0 }, |
74 | /* UDATA descriptor */ |
74 | /* UDATA descriptor */ |
75 | { .limit_0_15 = 0xffff, |
75 | { .limit_0_15 = 0xffff, |
76 | .base_0_15 = 0, |
76 | .base_0_15 = 0, |
77 | .base_16_23 = 0, |
77 | .base_16_23 = 0, |
78 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, |
78 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, |
79 | .limit_16_19 = 0xf, |
79 | .limit_16_19 = 0xf, |
80 | .available = 0, |
80 | .available = 0, |
81 | .longmode = 0, |
81 | .longmode = 0, |
82 | .special = 1, |
82 | .special = 1, |
83 | .granularity = 1, |
83 | .granularity = 1, |
84 | .base_24_31 = 0 }, |
84 | .base_24_31 = 0 }, |
85 | /* UTEXT descriptor */ |
85 | /* UTEXT descriptor */ |
86 | { .limit_0_15 = 0xffff, |
86 | { .limit_0_15 = 0xffff, |
87 | .base_0_15 = 0, |
87 | .base_0_15 = 0, |
88 | .base_16_23 = 0, |
88 | .base_16_23 = 0, |
89 | .access = AR_PRESENT | AR_CODE | DPL_USER, |
89 | .access = AR_PRESENT | AR_CODE | DPL_USER, |
90 | .limit_16_19 = 0xf, |
90 | .limit_16_19 = 0xf, |
91 | .available = 0, |
91 | .available = 0, |
92 | .longmode = 1, |
92 | .longmode = 1, |
93 | .special = 0, |
93 | .special = 0, |
94 | .granularity = 1, |
94 | .granularity = 1, |
95 | .base_24_31 = 0 }, |
95 | .base_24_31 = 0 }, |
96 | /* KTEXT 32-bit protected, for protected mode before long mode */ |
96 | /* KTEXT 32-bit protected, for protected mode before long mode */ |
97 | { .limit_0_15 = 0xffff, |
97 | { .limit_0_15 = 0xffff, |
98 | .base_0_15 = 0, |
98 | .base_0_15 = 0, |
99 | .base_16_23 = 0, |
99 | .base_16_23 = 0, |
100 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, |
100 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, |
101 | .limit_16_19 = 0xf, |
101 | .limit_16_19 = 0xf, |
102 | .available = 0, |
102 | .available = 0, |
103 | .longmode = 0, |
103 | .longmode = 0, |
104 | .special = 1, |
104 | .special = 1, |
105 | .granularity = 1, |
105 | .granularity = 1, |
106 | .base_24_31 = 0 }, |
106 | .base_24_31 = 0 }, |
107 | /* TSS descriptor - set up will be completed later, |
107 | /* TSS descriptor - set up will be completed later, |
108 | * on AMD64 it is 64-bit - 2 items in table */ |
108 | * on AMD64 it is 64-bit - 2 items in table */ |
109 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
109 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
110 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
110 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
111 | /* VESA Init descriptor */ |
111 | /* VESA Init descriptor */ |
112 | #ifdef CONFIG_FB |
112 | #ifdef CONFIG_FB |
113 | { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } |
113 | { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } |
114 | #endif |
114 | #endif |
115 | }; |
115 | }; |
116 | 116 | ||
117 | idescriptor_t idt[IDT_ITEMS]; |
117 | idescriptor_t idt[IDT_ITEMS]; |
118 | 118 | ||
119 | ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt }; |
119 | ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt }; |
120 | ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt }; |
120 | ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt }; |
121 | 121 | ||
122 | static tss_t tss; |
122 | static tss_t tss; |
123 | tss_t *tss_p = NULL; |
123 | tss_t *tss_p = NULL; |
124 | 124 | ||
125 | void gdt_tss_setbase(descriptor_t *d, uintptr_t base) |
125 | void gdt_tss_setbase(descriptor_t *d, uintptr_t base) |
126 | { |
126 | { |
127 | tss_descriptor_t *td = (tss_descriptor_t *) d; |
127 | tss_descriptor_t *td = (tss_descriptor_t *) d; |
128 | 128 | ||
129 | td->base_0_15 = base & 0xffff; |
129 | td->base_0_15 = base & 0xffff; |
130 | td->base_16_23 = ((base) >> 16) & 0xff; |
130 | td->base_16_23 = ((base) >> 16) & 0xff; |
131 | td->base_24_31 = ((base) >> 24) & 0xff; |
131 | td->base_24_31 = ((base) >> 24) & 0xff; |
132 | td->base_32_63 = ((base) >> 32); |
132 | td->base_32_63 = ((base) >> 32); |
133 | } |
133 | } |
134 | 134 | ||
135 | void gdt_tss_setlimit(descriptor_t *d, uint32_t limit) |
135 | void gdt_tss_setlimit(descriptor_t *d, uint32_t limit) |
136 | { |
136 | { |
137 | struct tss_descriptor *td = (tss_descriptor_t *) d; |
137 | struct tss_descriptor *td = (tss_descriptor_t *) d; |
138 | 138 | ||
139 | td->limit_0_15 = limit & 0xffff; |
139 | td->limit_0_15 = limit & 0xffff; |
140 | td->limit_16_19 = (limit >> 16) & 0xf; |
140 | td->limit_16_19 = (limit >> 16) & 0xf; |
141 | } |
141 | } |
142 | 142 | ||
143 | void idt_setoffset(idescriptor_t *d, uintptr_t offset) |
143 | void idt_setoffset(idescriptor_t *d, uintptr_t offset) |
144 | { |
144 | { |
145 | /* |
145 | /* |
146 | * Offset is a linear address. |
146 | * Offset is a linear address. |
147 | */ |
147 | */ |
148 | d->offset_0_15 = offset & 0xffff; |
148 | d->offset_0_15 = offset & 0xffff; |
149 | d->offset_16_31 = offset >> 16 & 0xffff; |
149 | d->offset_16_31 = offset >> 16 & 0xffff; |
150 | d->offset_32_63 = offset >> 32; |
150 | d->offset_32_63 = offset >> 32; |
151 | } |
151 | } |
152 | 152 | ||
153 | void tss_initialize(tss_t *t) |
153 | void tss_initialize(tss_t *t) |
154 | { |
154 | { |
155 | memsetb((uintptr_t) t, sizeof(tss_t), 0); |
155 | memsetb((uintptr_t) t, sizeof(tss_t), 0); |
156 | } |
156 | } |
157 | 157 | ||
158 | /* |
158 | /* |
159 | * This function takes care of proper setup of IDT and IDTR. |
159 | * This function takes care of proper setup of IDT and IDTR. |
160 | */ |
160 | */ |
161 | void idt_init(void) |
161 | void idt_init(void) |
162 | { |
162 | { |
163 | idescriptor_t *d; |
163 | idescriptor_t *d; |
164 | int i; |
164 | int i; |
165 | 165 | ||
166 | for (i = 0; i < IDT_ITEMS; i++) { |
166 | for (i = 0; i < IDT_ITEMS; i++) { |
167 | d = &idt[i]; |
167 | d = &idt[i]; |
168 | 168 | ||
169 | d->unused = 0; |
169 | d->unused = 0; |
170 | d->selector = gdtselector(KTEXT_DES); |
170 | d->selector = gdtselector(KTEXT_DES); |
171 | 171 | ||
172 | d->present = 1; |
172 | d->present = 1; |
173 | d->type = AR_INTERRUPT; /* masking interrupt */ |
173 | d->type = AR_INTERRUPT; /* masking interrupt */ |
174 | 174 | ||
175 | idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size); |
175 | idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size); |
176 | } |
176 | } |
177 | } |
177 | } |
178 | 178 | ||
179 | /** Initialize segmentation - code/data/idt tables |
179 | /** Initialize segmentation - code/data/idt tables |
180 | * |
180 | * |
181 | */ |
181 | */ |
182 | void pm_init(void) |
182 | void pm_init(void) |
183 | { |
183 | { |
184 | descriptor_t *gdt_p = (struct descriptor *) gdtr.base; |
184 | descriptor_t *gdt_p = (struct descriptor *) gdtr.base; |
185 | tss_descriptor_t *tss_desc; |
185 | tss_descriptor_t *tss_desc; |
186 | 186 | ||
187 | /* |
187 | /* |
188 | * Each CPU has its private GDT and TSS. |
188 | * Each CPU has its private GDT and TSS. |
189 | * All CPUs share one IDT. |
189 | * All CPUs share one IDT. |
190 | */ |
190 | */ |
191 | 191 | ||
192 | if (config.cpu_active == 1) { |
192 | if (config.cpu_active == 1) { |
193 | idt_init(); |
193 | idt_init(); |
194 | /* |
194 | /* |
195 | * NOTE: bootstrap CPU has statically allocated TSS, because |
195 | * NOTE: bootstrap CPU has statically allocated TSS, because |
196 | * the heap hasn't been initialized so far. |
196 | * the heap hasn't been initialized so far. |
197 | */ |
197 | */ |
198 | tss_p = &tss; |
198 | tss_p = &tss; |
199 | } |
199 | } |
200 | else { |
200 | else { |
201 | /* We are going to use malloc, which may return |
201 | /* We are going to use malloc, which may return |
202 | * non boot-mapped pointer, initialize the CR3 register |
202 | * non boot-mapped pointer, initialize the CR3 register |
203 | * ahead of page_init */ |
203 | * ahead of page_init */ |
204 | write_cr3((uintptr_t) AS_KERNEL->page_table); |
204 | write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); |
205 | 205 | ||
206 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
206 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
207 | if (!tss_p) |
207 | if (!tss_p) |
208 | panic("could not allocate TSS\n"); |
208 | panic("could not allocate TSS\n"); |
209 | } |
209 | } |
210 | 210 | ||
211 | tss_initialize(tss_p); |
211 | tss_initialize(tss_p); |
212 | 212 | ||
213 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
213 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
214 | tss_desc->present = 1; |
214 | tss_desc->present = 1; |
215 | tss_desc->type = AR_TSS; |
215 | tss_desc->type = AR_TSS; |
216 | tss_desc->dpl = PL_KERNEL; |
216 | tss_desc->dpl = PL_KERNEL; |
217 | 217 | ||
218 | gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
218 | gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
219 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
219 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
220 | 220 | ||
221 | gdtr_load(&gdtr); |
221 | gdtr_load(&gdtr); |
222 | idtr_load(&idtr); |
222 | idtr_load(&idtr); |
223 | /* |
223 | /* |
224 | * As of this moment, the current CPU has its own GDT pointing |
224 | * As of this moment, the current CPU has its own GDT pointing |
225 | * to its own TSS. We just need to load the TR register. |
225 | * to its own TSS. We just need to load the TR register. |
226 | */ |
226 | */ |
227 | tr_load(gdtselector(TSS_DES)); |
227 | tr_load(gdtselector(TSS_DES)); |
228 | } |
228 | } |
229 | 229 | ||
230 | /** @} |
230 | /** @} |
231 | */ |
231 | */ |
232 | 232 |