WebSVN – HelenOS – Diff – /trunk/kernel/arch/amd64/src/pm.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * Copyright (c) 2005-2006 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64  
 * @{
 */
/** @file
 */
 
#include <arch/pm.h>
 
 
 
#include <arch/asm.h>
 
#include <mm/as.h>
 
#include <mm/frame.h>
 
#include <memstr.h>
#include <mm/slab.h>
 
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* VESA Init descriptor */
#ifdef CONFIG_FB    
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
#endif
};
 
idescriptor_t idt[IDT_ITEMS];
 
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
 
static tss_t tss;
tss_t *tss_p = NULL;
 
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
{
    tss_descriptor_t *td = (tss_descriptor_t *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
{
    struct tss_descriptor *td = (tss_descriptor_t *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(tss_t *t)
{
    memsetb((uintptr_t) t, sizeof(tss_t), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    idescriptor_t *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
    }
}
 
/** Initialize segmentation - code/data/idt tables
 *
 */
void pm_init(void)
{
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
    tss_descriptor_t *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        /* We are going to use malloc, which may return
         * non boot-mapped pointer, initialize the CR3 register
         * ahead of page_init */
        write_cr3((uintptr_t) AS_KERNEL->page_table);
 
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
    gdtr_load(&gdtr);
    idtr_load(&idtr);
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    tr_load(gdtselector(TSS_DES));
}
 
/** @}
 */
 

Rev 2071	Rev 2089
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* Copyright (c) 2005-2006 Ondrej Palkovsky	3	* Copyright (c) 2005-2006 Ondrej Palkovsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup amd64	30	/** @addtogroup amd64
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#include <arch/pm.h>	36	#include <arch/pm.h>
37	#include <arch/mm/page.h>	-
38	#include <arch/types.h>	-
39	#include <arch/interrupt.h>	-
40	#include <arch/asm.h>	37	#include <arch/asm.h>
41	#include <interrupt.h>	-
42	#include <mm/as.h>	38	#include <mm/as.h>
43		-
44	#include <config.h>	39	#include <mm/frame.h>
45		-
46	#include <memstr.h>	40	#include <memstr.h>
47	#include <mm/slab.h>	41	#include <mm/slab.h>
48	#include <debug.h>	-
49		42
50	/*	43	/*
51	* There is no segmentation in long mode so we set up flat mode. In this	44	* There is no segmentation in long mode so we set up flat mode. In this
52	* mode, we use, for each privilege level, two segments spanning the	45	* mode, we use, for each privilege level, two segments spanning the
53	* whole memory. One is for code and one is for data.	46	* whole memory. One is for code and one is for data.
54	*/	47	*/
55		48
56	descriptor_t gdt[GDT_ITEMS] = {	49	descriptor_t gdt[GDT_ITEMS] = {
57	/* NULL descriptor */	50	/* NULL descriptor */
58	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
59	/* KTEXT descriptor */	52	/* KTEXT descriptor */
60	{ .limit_0_15 = 0xffff,	53	{ .limit_0_15 = 0xffff,
61	.base_0_15 = 0,	54	.base_0_15 = 0,
62	.base_16_23 = 0,	55	.base_16_23 = 0,
63	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,	56	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,
64	.limit_16_19 = 0xf,	57	.limit_16_19 = 0xf,
65	.available = 0,	58	.available = 0,
66	.longmode = 1,	59	.longmode = 1,
67	.special = 0,	60	.special = 0,
68	.granularity = 1,	61	.granularity = 1,
69	.base_24_31 = 0 },	62	.base_24_31 = 0 },
70	/* KDATA descriptor */	63	/* KDATA descriptor */
71	{ .limit_0_15 = 0xffff,	64	{ .limit_0_15 = 0xffff,
72	.base_0_15 = 0,	65	.base_0_15 = 0,
73	.base_16_23 = 0,	66	.base_16_23 = 0,
74	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	67	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
75	.limit_16_19 = 0xf,	68	.limit_16_19 = 0xf,
76	.available = 0,	69	.available = 0,
77	.longmode = 0,	70	.longmode = 0,
78	.special = 0,	71	.special = 0,
79	.granularity = 1,	72	.granularity = 1,
80	.base_24_31 = 0 },	73	.base_24_31 = 0 },
81	/* UDATA descriptor */	74	/* UDATA descriptor */
82	{ .limit_0_15 = 0xffff,	75	{ .limit_0_15 = 0xffff,
83	.base_0_15 = 0,	76	.base_0_15 = 0,
84	.base_16_23 = 0,	77	.base_16_23 = 0,
85	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	78	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
86	.limit_16_19 = 0xf,	79	.limit_16_19 = 0xf,
87	.available = 0,	80	.available = 0,
88	.longmode = 0,	81	.longmode = 0,
89	.special = 1,	82	.special = 1,
90	.granularity = 1,	83	.granularity = 1,
91	.base_24_31 = 0 },	84	.base_24_31 = 0 },
92	/* UTEXT descriptor */	85	/* UTEXT descriptor */
93	{ .limit_0_15 = 0xffff,	86	{ .limit_0_15 = 0xffff,
94	.base_0_15 = 0,	87	.base_0_15 = 0,
95	.base_16_23 = 0,	88	.base_16_23 = 0,
96	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	89	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
97	.limit_16_19 = 0xf,	90	.limit_16_19 = 0xf,
98	.available = 0,	91	.available = 0,
99	.longmode = 1,	92	.longmode = 1,
100	.special = 0,	93	.special = 0,
101	.granularity = 1,	94	.granularity = 1,
102	.base_24_31 = 0 },	95	.base_24_31 = 0 },
103	/* KTEXT 32-bit protected, for protected mode before long mode */	96	/* KTEXT 32-bit protected, for protected mode before long mode */
104	{ .limit_0_15 = 0xffff,	97	{ .limit_0_15 = 0xffff,
105	.base_0_15 = 0,	98	.base_0_15 = 0,
106	.base_16_23 = 0,	99	.base_16_23 = 0,
107	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	100	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
108	.limit_16_19 = 0xf,	101	.limit_16_19 = 0xf,
109	.available = 0,	102	.available = 0,
110	.longmode = 0,	103	.longmode = 0,
111	.special = 1,	104	.special = 1,
112	.granularity = 1,	105	.granularity = 1,
113	.base_24_31 = 0 },	106	.base_24_31 = 0 },
114	/* TSS descriptor - set up will be completed later,	107	/* TSS descriptor - set up will be completed later,
115	* on AMD64 it is 64-bit - 2 items in table */	108	* on AMD64 it is 64-bit - 2 items in table */
116	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
117	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
118	/* VESA Init descriptor */	111	/* VESA Init descriptor */
119	#ifdef CONFIG_FB	112	#ifdef CONFIG_FB
120	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }	113	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
121	#endif	114	#endif
122	};	115	};
123		116
124	idescriptor_t idt[IDT_ITEMS];	117	idescriptor_t idt[IDT_ITEMS];
125		118
126	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };	119	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
127	ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };	120	ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
128		121
129	static tss_t tss;	122	static tss_t tss;
130	tss_t *tss_p = NULL;	123	tss_t *tss_p = NULL;
131		124
132	void gdt_tss_setbase(descriptor_t *d, uintptr_t base)	125	void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
133	{	126	{
134	tss_descriptor_t td = (tss_descriptor_t ) d;	127	tss_descriptor_t td = (tss_descriptor_t ) d;
135		128
136	td->base_0_15 = base & 0xffff;	129	td->base_0_15 = base & 0xffff;
137	td->base_16_23 = ((base) >> 16) & 0xff;	130	td->base_16_23 = ((base) >> 16) & 0xff;
138	td->base_24_31 = ((base) >> 24) & 0xff;	131	td->base_24_31 = ((base) >> 24) & 0xff;
139	td->base_32_63 = ((base) >> 32);	132	td->base_32_63 = ((base) >> 32);
140	}	133	}
141		134
142	void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)	135	void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
143	{	136	{
144	struct tss_descriptor td = (tss_descriptor_t ) d;	137	struct tss_descriptor td = (tss_descriptor_t ) d;
145		138
146	td->limit_0_15 = limit & 0xffff;	139	td->limit_0_15 = limit & 0xffff;
147	td->limit_16_19 = (limit >> 16) & 0xf;	140	td->limit_16_19 = (limit >> 16) & 0xf;
148	}	141	}
149		142
150	void idt_setoffset(idescriptor_t *d, uintptr_t offset)	143	void idt_setoffset(idescriptor_t *d, uintptr_t offset)
151	{	144	{
152	/*	145	/*
153	* Offset is a linear address.	146	* Offset is a linear address.
154	*/	147	*/
155	d->offset_0_15 = offset & 0xffff;	148	d->offset_0_15 = offset & 0xffff;
156	d->offset_16_31 = offset >> 16 & 0xffff;	149	d->offset_16_31 = offset >> 16 & 0xffff;
157	d->offset_32_63 = offset >> 32;	150	d->offset_32_63 = offset >> 32;
158	}	151	}
159		152
160	void tss_initialize(tss_t *t)	153	void tss_initialize(tss_t *t)
161	{	154	{
162	memsetb((uintptr_t) t, sizeof(tss_t), 0);	155	memsetb((uintptr_t) t, sizeof(tss_t), 0);
163	}	156	}
164		157
165	/*	158	/*
166	* This function takes care of proper setup of IDT and IDTR.	159	* This function takes care of proper setup of IDT and IDTR.
167	*/	160	*/
168	void idt_init(void)	161	void idt_init(void)
169	{	162	{
170	idescriptor_t *d;	163	idescriptor_t *d;
171	int i;	164	int i;
172		165
173	for (i = 0; i < IDT_ITEMS; i++) {	166	for (i = 0; i < IDT_ITEMS; i++) {
174	d = &idt[i];	167	d = &idt[i];
175		168
176	d->unused = 0;	169	d->unused = 0;
177	d->selector = gdtselector(KTEXT_DES);	170	d->selector = gdtselector(KTEXT_DES);
178		171
179	d->present = 1;	172	d->present = 1;
180	d->type = AR_INTERRUPT; /* masking interrupt */	173	d->type = AR_INTERRUPT; /* masking interrupt */
181		174
182	idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);	175	idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
183	}	176	}
184	}	177	}
185		178
186	/** Initialize segmentation - code/data/idt tables	179	/** Initialize segmentation - code/data/idt tables
187	*	180	*
188	*/	181	*/
189	void pm_init(void)	182	void pm_init(void)
190	{	183	{
191	descriptor_t gdt_p = (struct descriptor ) gdtr.base;	184	descriptor_t gdt_p = (struct descriptor ) gdtr.base;
192	tss_descriptor_t *tss_desc;	185	tss_descriptor_t *tss_desc;
193		186
194	/*	187	/*
195	* Each CPU has its private GDT and TSS.	188	* Each CPU has its private GDT and TSS.
196	* All CPUs share one IDT.	189	* All CPUs share one IDT.
197	*/	190	*/
198		191
199	if (config.cpu_active == 1) {	192	if (config.cpu_active == 1) {
200	idt_init();	193	idt_init();
201	/*	194	/*
202	* NOTE: bootstrap CPU has statically allocated TSS, because	195	* NOTE: bootstrap CPU has statically allocated TSS, because
203	* the heap hasn't been initialized so far.	196	* the heap hasn't been initialized so far.
204	*/	197	*/
205	tss_p = &tss;	198	tss_p = &tss;
206	}	199	}
207	else {	200	else {
208	/* We are going to use malloc, which may return	201	/* We are going to use malloc, which may return
209	* non boot-mapped pointer, initialize the CR3 register	202	* non boot-mapped pointer, initialize the CR3 register
210	* ahead of page_init */	203	* ahead of page_init */
211	write_cr3((uintptr_t) AS_KERNEL->page_table);	204	write_cr3((uintptr_t) AS_KERNEL->page_table);
212		205
213	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);	206	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
214	if (!tss_p)	207	if (!tss_p)
215	panic("could not allocate TSS\n");	208	panic("could not allocate TSS\n");
216	}	209	}
217		210
218	tss_initialize(tss_p);	211	tss_initialize(tss_p);
219		212
220	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);	213	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
221	tss_desc->present = 1;	214	tss_desc->present = 1;
222	tss_desc->type = AR_TSS;	215	tss_desc->type = AR_TSS;
223	tss_desc->dpl = PL_KERNEL;	216	tss_desc->dpl = PL_KERNEL;
224		217
225	gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);	218	gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
226	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);	219	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
227		220
228	gdtr_load(&gdtr);	221	gdtr_load(&gdtr);
229	idtr_load(&idtr);	222	idtr_load(&idtr);
230	/*	223	/*
231	* As of this moment, the current CPU has its own GDT pointing	224	* As of this moment, the current CPU has its own GDT pointing
232	* to its own TSS. We just need to load the TR register.	225	* to its own TSS. We just need to load the TR register.
233	*/	226	*/
234	tr_load(gdtselector(TSS_DES));	227	tr_load(gdtselector(TSS_DES));
235	}	228	}
236		229
237	/** @}	230	/** @}
238	*/	231	*/
239		232

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/amd64/src/pm.c @ 2272 – Rev 2071 → 2089