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1 | /* |
1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64 |
29 | /** @addtogroup amd64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <cpu.h> |
35 | #include <cpu.h> |
36 | #include <arch/cpu.h> |
36 | #include <arch/cpu.h> |
37 | #include <arch/cpuid.h> |
37 | #include <arch/cpuid.h> |
38 | #include <arch/pm.h> |
38 | #include <arch/pm.h> |
39 | 39 | ||
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <arch/types.h> |
41 | #include <arch/types.h> |
42 | #include <print.h> |
42 | #include <print.h> |
43 | #include <fpu_context.h> |
43 | #include <fpu_context.h> |
44 | 44 | ||
45 | /* |
45 | /* |
46 | * Identification of CPUs. |
46 | * Identification of CPUs. |
47 | * Contains only non-MP-Specification specific SMP code. |
47 | * Contains only non-MP-Specification specific SMP code. |
48 | */ |
48 | */ |
49 | #define AMD_CPUID_EBX 0x68747541 |
49 | #define AMD_CPUID_EBX 0x68747541 |
50 | #define AMD_CPUID_ECX 0x444d4163 |
50 | #define AMD_CPUID_ECX 0x444d4163 |
51 | #define AMD_CPUID_EDX 0x69746e65 |
51 | #define AMD_CPUID_EDX 0x69746e65 |
52 | 52 | ||
53 | #define INTEL_CPUID_EBX 0x756e6547 |
53 | #define INTEL_CPUID_EBX 0x756e6547 |
54 | #define INTEL_CPUID_ECX 0x6c65746e |
54 | #define INTEL_CPUID_ECX 0x6c65746e |
55 | #define INTEL_CPUID_EDX 0x49656e69 |
55 | #define INTEL_CPUID_EDX 0x49656e69 |
56 | 56 | ||
57 | 57 | ||
58 | enum vendor { |
58 | enum vendor { |
59 | VendorUnknown = 0, |
59 | VendorUnknown = 0, |
60 | VendorAMD, |
60 | VendorAMD, |
61 | VendorIntel |
61 | VendorIntel |
62 | }; |
62 | }; |
63 | 63 | ||
64 | static char *vendor_str[] = { |
64 | static char *vendor_str[] = { |
65 | "Unknown Vendor", |
65 | "Unknown Vendor", |
66 | "AuthenticAMD", |
66 | "AuthenticAMD", |
67 | "GenuineIntel" |
67 | "GenuineIntel" |
68 | }; |
68 | }; |
69 | 69 | ||
70 | 70 | ||
71 | /** Setup flags on processor so that we can use the FPU |
71 | /** Setup flags on processor so that we can use the FPU |
72 | * |
72 | * |
73 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
73 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
74 | * cr0.em = 0 -> we do not emulate coprocessor |
74 | * cr0.em = 0 -> we do not emulate coprocessor |
75 | * cr0.mp = 1 -> we do want lazy context switch |
75 | * cr0.mp = 1 -> we do want lazy context switch |
76 | */ |
76 | */ |
77 | void cpu_setup_fpu(void) |
77 | void cpu_setup_fpu(void) |
78 | { |
78 | { |
79 | asm volatile ( |
79 | asm volatile ( |
80 | "movq %%cr0, %%rax;" |
80 | "movq %%cr0, %%rax\n" |
81 | "btsq $1, %%rax;" /* cr0.mp */ |
81 | "btsq $1, %%rax\n" /* cr0.mp */ |
82 | "btrq $2, %%rax;" /* cr0.em */ |
82 | "btrq $2, %%rax\n" /* cr0.em */ |
83 | "movq %%rax, %%cr0;" |
83 | "movq %%rax, %%cr0\n" |
84 | 84 | ||
85 | "movq %%cr4, %%rax;" |
85 | "movq %%cr4, %%rax\n" |
86 | "bts $9, %%rax;" /* cr4.osfxsr */ |
86 | "bts $9, %%rax\n" /* cr4.osfxsr */ |
87 | "movq %%rax, %%cr4;" |
87 | "movq %%rax, %%cr4\n" |
88 | : |
- | |
89 | : |
- | |
90 | :"%rax" |
88 | ::: "%rax" |
91 | ); |
89 | ); |
92 | } |
90 | } |
93 | 91 | ||
94 | /** Set the TS flag to 1. |
92 | /** Set the TS flag to 1. |
95 | * |
93 | * |
96 | * If a thread accesses coprocessor, exception is run, which |
94 | * If a thread accesses coprocessor, exception is run, which |
97 | * does a lazy fpu context switch. |
95 | * does a lazy fpu context switch. |
98 | * |
96 | * |
99 | */ |
97 | */ |
100 | void fpu_disable(void) |
98 | void fpu_disable(void) |
101 | { |
99 | { |
102 | asm volatile ( |
100 | asm volatile ( |
103 | "mov %%cr0,%%rax;" |
101 | "mov %%cr0, %%rax\n" |
104 | "bts $3,%%rax;" |
102 | "bts $3, %%rax\n" |
105 | "mov %%rax,%%cr0;" |
103 | "mov %%rax, %%cr0\n" |
106 | : |
- | |
107 | : |
- | |
108 | :"%rax" |
104 | ::: "%rax" |
109 | ); |
105 | ); |
110 | } |
106 | } |
111 | 107 | ||
112 | void fpu_enable(void) |
108 | void fpu_enable(void) |
113 | { |
109 | { |
114 | asm volatile ( |
110 | asm volatile ( |
115 | "mov %%cr0,%%rax;" |
111 | "mov %%cr0, %%rax\n" |
116 | "btr $3,%%rax;" |
112 | "btr $3, %%rax\n" |
117 | "mov %%rax,%%cr0;" |
113 | "mov %%rax, %%cr0\n" |
118 | : |
- | |
119 | : |
- | |
120 | :"%rax" |
114 | ::: "%rax" |
121 | ); |
115 | ); |
122 | } |
116 | } |
123 | 117 | ||
124 | void cpu_arch_init(void) |
118 | void cpu_arch_init(void) |
125 | { |
119 | { |
126 | CPU->arch.tss = tss_p; |
120 | CPU->arch.tss = tss_p; |
127 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - |
121 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - |
128 | ((uint8_t *) CPU->arch.tss); |
122 | ((uint8_t *) CPU->arch.tss); |
129 | CPU->fpu_owner = NULL; |
123 | CPU->fpu_owner = NULL; |
130 | } |
124 | } |
131 | 125 | ||
132 | void cpu_identify(void) |
126 | void cpu_identify(void) |
133 | { |
127 | { |
134 | cpu_info_t info; |
128 | cpu_info_t info; |
135 | 129 | ||
136 | CPU->arch.vendor = VendorUnknown; |
130 | CPU->arch.vendor = VendorUnknown; |
137 | if (has_cpuid()) { |
131 | if (has_cpuid()) { |
138 | cpuid(0, &info); |
132 | cpuid(0, &info); |
139 | 133 | ||
140 | /* |
134 | /* |
141 | * Check for AMD processor. |
135 | * Check for AMD processor. |
142 | */ |
136 | */ |
143 | if (info.cpuid_ebx == AMD_CPUID_EBX && |
137 | if (info.cpuid_ebx == AMD_CPUID_EBX && |
144 | info.cpuid_ecx == AMD_CPUID_ECX && |
138 | info.cpuid_ecx == AMD_CPUID_ECX && |
145 | info.cpuid_edx == AMD_CPUID_EDX) { |
139 | info.cpuid_edx == AMD_CPUID_EDX) { |
146 | CPU->arch.vendor = VendorAMD; |
140 | CPU->arch.vendor = VendorAMD; |
147 | } |
141 | } |
148 | 142 | ||
149 | /* |
143 | /* |
150 | * Check for Intel processor. |
144 | * Check for Intel processor. |
151 | */ |
145 | */ |
152 | if (info.cpuid_ebx == INTEL_CPUID_EBX && |
146 | if (info.cpuid_ebx == INTEL_CPUID_EBX && |
153 | info.cpuid_ecx == INTEL_CPUID_ECX && |
147 | info.cpuid_ecx == INTEL_CPUID_ECX && |
154 | info.cpuid_edx == INTEL_CPUID_EDX) { |
148 | info.cpuid_edx == INTEL_CPUID_EDX) { |
155 | CPU->arch.vendor = VendorIntel; |
149 | CPU->arch.vendor = VendorIntel; |
156 | } |
150 | } |
157 | 151 | ||
158 | cpuid(1, &info); |
152 | cpuid(1, &info); |
159 | CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; |
153 | CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; |
160 | CPU->arch.model = (info.cpuid_eax >> 4) & 0xf; |
154 | CPU->arch.model = (info.cpuid_eax >> 4) & 0xf; |
161 | CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf; |
155 | CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf; |
162 | } |
156 | } |
163 | } |
157 | } |
164 | 158 | ||
165 | void cpu_print_report(cpu_t* m) |
159 | void cpu_print_report(cpu_t* m) |
166 | { |
160 | { |
167 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
161 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
168 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, |
162 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, |
169 | m->arch.stepping, m->frequency_mhz); |
163 | m->arch.stepping, m->frequency_mhz); |
170 | } |
164 | } |
171 | 165 | ||
172 | /** @} |
166 | /** @} |
173 | */ |
167 | */ |
174 | 168 |