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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/cpu.h> |
29 | #include <arch/cpu.h> |
30 | #include <arch/cpuid.h> |
30 | #include <arch/cpuid.h> |
31 | #include <arch/pm.h> |
31 | #include <arch/pm.h> |
32 | 32 | ||
33 | #include <arch.h> |
33 | #include <arch.h> |
34 | #include <arch/types.h> |
34 | #include <arch/types.h> |
35 | #include <print.h> |
35 | #include <print.h> |
36 | #include <typedefs.h> |
36 | #include <typedefs.h> |
37 | 37 | ||
38 | /* |
38 | /* |
39 | * Identification of CPUs. |
39 | * Identification of CPUs. |
40 | * Contains only non-MP-Specification specific SMP code. |
40 | * Contains only non-MP-Specification specific SMP code. |
41 | */ |
41 | */ |
42 | #define AMD_CPUID_EBX 0x68747541 |
42 | #define AMD_CPUID_EBX 0x68747541 |
43 | #define AMD_CPUID_ECX 0x444d4163 |
43 | #define AMD_CPUID_ECX 0x444d4163 |
44 | #define AMD_CPUID_EDX 0x69746e65 |
44 | #define AMD_CPUID_EDX 0x69746e65 |
45 | 45 | ||
46 | #define INTEL_CPUID_EBX 0x756e6547 |
46 | #define INTEL_CPUID_EBX 0x756e6547 |
47 | #define INTEL_CPUID_ECX 0x6c65746e |
47 | #define INTEL_CPUID_ECX 0x6c65746e |
48 | #define INTEL_CPUID_EDX 0x49656e69 |
48 | #define INTEL_CPUID_EDX 0x49656e69 |
49 | 49 | ||
50 | 50 | ||
51 | enum vendor { |
51 | enum vendor { |
52 | VendorUnknown=0, |
52 | VendorUnknown=0, |
53 | VendorAMD, |
53 | VendorAMD, |
54 | VendorIntel |
54 | VendorIntel |
55 | }; |
55 | }; |
56 | 56 | ||
57 | static char *vendor_str[] = { |
57 | static char *vendor_str[] = { |
58 | "Unknown Vendor", |
58 | "Unknown Vendor", |
59 | "AuthenticAMD", |
59 | "AuthenticAMD", |
60 | "GenuineIntel" |
60 | "GenuineIntel" |
61 | }; |
61 | }; |
62 | 62 | ||
63 | 63 | ||
64 | /** Setup flags on processor so that we can use the FPU |
64 | /** Setup flags on processor so that we can use the FPU |
65 | * |
65 | * |
66 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
66 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor |
67 | * cr0.em = 0 -> we do not emulate coprocessor |
67 | * cr0.em = 0 -> we do not emulate coprocessor |
68 | * cr0.mp = 1 -> we do want lazy context switch |
68 | * cr0.mp = 1 -> we do want lazy context switch |
69 | */ |
69 | */ |
70 | void cpu_setup_fpu(void) |
70 | void cpu_setup_fpu(void) |
71 | { |
71 | { |
72 | __asm__ volatile ( |
72 | __asm__ volatile ( |
73 | "movq %%cr0, %%rax;" |
73 | "movq %%cr0, %%rax;" |
74 | "btsq $1, %%rax;" /* cr0.mp */ |
74 | "btsq $1, %%rax;" /* cr0.mp */ |
75 | "btrq $2, %%rax;" /* cr0.em */ |
75 | "btrq $2, %%rax;" /* cr0.em */ |
76 | "movq %%rax, %%cr0;" |
76 | "movq %%rax, %%cr0;" |
77 | 77 | ||
78 | "movq %%cr4, %%rax;" |
78 | "movq %%cr4, %%rax;" |
79 | "bts $9, %%rax;" /* cr4.osfxsr */ |
79 | "bts $9, %%rax;" /* cr4.osfxsr */ |
80 | "movq %%rax, %%cr4;" |
80 | "movq %%rax, %%cr4;" |
81 | : |
81 | : |
82 | : |
82 | : |
83 | :"%rax" |
83 | :"%rax" |
84 | ); |
84 | ); |
85 | } |
85 | } |
86 | 86 | ||
87 | /** Set the TS flag to 1. |
87 | /** Set the TS flag to 1. |
88 | * |
88 | * |
89 | * If a thread accesses coprocessor, exception is run, which |
89 | * If a thread accesses coprocessor, exception is run, which |
90 | * does a lazy fpu context switch. |
90 | * does a lazy fpu context switch. |
91 | * |
91 | * |
92 | */ |
92 | */ |
93 | void set_TS_flag(void) |
93 | void fpu_disable(void) |
94 | { |
94 | { |
95 | __asm__ volatile ( |
95 | __asm__ volatile ( |
96 | "mov %%cr0,%%rax;" |
96 | "mov %%cr0,%%rax;" |
97 | "bts $3,%%rax;" |
97 | "bts $3,%%rax;" |
98 | "mov %%rax,%%cr0;" |
98 | "mov %%rax,%%cr0;" |
99 | : |
99 | : |
100 | : |
100 | : |
101 | :"%rax" |
101 | :"%rax" |
102 | ); |
102 | ); |
103 | } |
103 | } |
104 | 104 | ||
105 | void reset_TS_flag(void) |
105 | void fpu_enable(void) |
106 | { |
106 | { |
107 | __asm__ volatile ( |
107 | __asm__ volatile ( |
108 | "mov %%cr0,%%rax;" |
108 | "mov %%cr0,%%rax;" |
109 | "btr $3,%%rax;" |
109 | "btr $3,%%rax;" |
110 | "mov %%rax,%%cr0;" |
110 | "mov %%rax,%%cr0;" |
111 | : |
111 | : |
112 | : |
112 | : |
113 | :"%rax" |
113 | :"%rax" |
114 | ); |
114 | ); |
115 | } |
115 | } |
116 | 116 | ||
117 | void cpu_arch_init(void) |
117 | void cpu_arch_init(void) |
118 | { |
118 | { |
119 | CPU->arch.tss = tss_p; |
119 | CPU->arch.tss = tss_p; |
120 | CPU->fpu_owner=NULL; |
120 | CPU->fpu_owner=NULL; |
121 | } |
121 | } |
122 | 122 | ||
123 | 123 | ||
124 | void cpu_identify(void) |
124 | void cpu_identify(void) |
125 | { |
125 | { |
126 | cpu_info_t info; |
126 | cpu_info_t info; |
127 | int i; |
127 | int i; |
128 | 128 | ||
129 | CPU->arch.vendor = VendorUnknown; |
129 | CPU->arch.vendor = VendorUnknown; |
130 | if (has_cpuid()) { |
130 | if (has_cpuid()) { |
131 | cpuid(0, &info); |
131 | cpuid(0, &info); |
132 | 132 | ||
133 | /* |
133 | /* |
134 | * Check for AMD processor. |
134 | * Check for AMD processor. |
135 | */ |
135 | */ |
136 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
136 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
137 | CPU->arch.vendor = VendorAMD; |
137 | CPU->arch.vendor = VendorAMD; |
138 | } |
138 | } |
139 | 139 | ||
140 | /* |
140 | /* |
141 | * Check for Intel processor. |
141 | * Check for Intel processor. |
142 | */ |
142 | */ |
143 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
143 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
144 | CPU->arch.vendor = VendorIntel; |
144 | CPU->arch.vendor = VendorIntel; |
145 | } |
145 | } |
146 | 146 | ||
147 | cpuid(1, &info); |
147 | cpuid(1, &info); |
148 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
148 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
149 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
149 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
150 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
150 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
151 | } |
151 | } |
152 | } |
152 | } |
153 | 153 | ||
154 | void cpu_print_report(cpu_t* m) |
154 | void cpu_print_report(cpu_t* m) |
155 | { |
155 | { |
156 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
156 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
157 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
157 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
158 | m->frequency_mhz); |
158 | m->frequency_mhz); |
159 | } |
159 | } |
160 | 160 |