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1 | # |
1 | # |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # and 1 means interrupt with error word |
31 | # and 1 means interrupt with error word |
32 | 32 | ||
33 | 33 | ||
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
35 | 35 | ||
36 | #define __ASM__ |
36 | #define __ASM__ |
37 | #include <arch/pm.h> |
37 | #include <arch/pm.h> |
38 | 38 | ||
39 | .text |
39 | .text |
40 | .global interrupt_handlers |
40 | .global interrupt_handlers |
41 | .global panic_printf |
41 | .global panic_printf |
42 | 42 | ||
43 | panic_printf: |
43 | panic_printf: |
44 | movq $halt, (%rsp) |
44 | movq $halt, (%rsp) |
45 | jmp printf |
45 | jmp printf |
46 | 46 | ||
47 | .global memcpy |
47 | .global memcpy |
48 | memcpy: |
48 | memcpy: |
49 | jmp _memcpy |
49 | jmp _memcpy |
50 | 50 | ||
51 | .global cpuid |
51 | .global cpuid |
52 | .global has_cpuid |
52 | .global has_cpuid |
53 | .global rdtsc |
53 | .global rdtsc |
54 | .global read_efer_flag |
54 | .global read_efer_flag |
55 | .global set_efer_flag |
55 | .global set_efer_flag |
56 | 56 | ||
57 | 57 | ||
58 | # THIS IS USERSPACE CODE |
58 | # THIS IS USERSPACE CODE |
59 | .global utext |
59 | .global utext |
60 | utext: |
60 | utext: |
61 | 0: |
61 | 0: |
62 | int $48 |
62 | int $48 |
63 | jmp 0b |
63 | jmp 0b |
64 | # not reached |
64 | # not reached |
65 | utext_end: |
65 | utext_end: |
66 | 66 | ||
67 | .data |
67 | .data |
68 | .global utext_size |
68 | .global utext_size |
69 | utext_size: |
69 | utext_size: |
70 | .long utext_end - utext |
70 | .long utext_end - utext |
71 | 71 | ||
72 | 72 | ||
73 | ## Determine CPUID support |
73 | ## Determine CPUID support |
74 | # |
74 | # |
75 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
75 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
76 | # |
76 | # |
77 | has_cpuid: |
77 | has_cpuid: |
78 | pushq %rbx |
- | |
79 | - | ||
80 | pushfq # store flags |
78 | pushfq # store flags |
81 | popq %rax # read flags |
79 | popq %rax # read flags |
82 | movq %rax,%rbx # copy flags |
80 | movq %rax,%rdx # copy flags |
83 | btcl $21,%ebx # swap the ID bit |
81 | btcl $21,%edx # swap the ID bit |
84 | pushq %rbx |
82 | pushq %rdx |
85 | popfq # propagate the change into flags |
83 | popfq # propagate the change into flags |
86 | pushfq |
84 | pushfq |
87 | popq %rbx # read flags |
85 | popq %rdx # read flags |
88 | andl $(1<<21),%eax # interested only in ID bit |
86 | andl $(1<<21),%eax # interested only in ID bit |
89 | andl $(1<<21),%ebx |
87 | andl $(1<<21),%edx |
90 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
88 | xorl %edx,%eax # 0 if not supported, 1 if supported |
91 | - | ||
92 | popq %rbx |
- | |
93 | ret |
89 | ret |
94 | 90 | ||
95 | cpuid: |
91 | cpuid: |
96 | movq %rbx, %r10 # we have to preserve rbx across function calls |
92 | movq %rbx, %r10 # we have to preserve rbx across function calls |
97 | 93 | ||
98 | movl %edi,%eax # load the command into %eax |
94 | movl %edi,%eax # load the command into %eax |
99 | 95 | ||
100 | cpuid |
96 | cpuid |
101 | movl %eax,0(%rsi) |
97 | movl %eax,0(%rsi) |
102 | movl %ebx,4(%rsi) |
98 | movl %ebx,4(%rsi) |
103 | movl %ecx,8(%rsi) |
99 | movl %ecx,8(%rsi) |
104 | movl %edx,12(%rsi) |
100 | movl %edx,12(%rsi) |
105 | 101 | ||
106 | movq %r10, %rbx |
102 | movq %r10, %rbx |
107 | ret |
103 | ret |
108 | 104 | ||
109 | rdtsc: |
105 | rdtsc: |
110 | xorq %rax,%rax |
106 | xorq %rax,%rax |
111 | rdtsc |
107 | rdtsc |
112 | ret |
108 | ret |
113 | 109 | ||
114 | set_efer_flag: |
110 | set_efer_flag: |
115 | movq $0xc0000080, %rcx |
111 | movq $0xc0000080, %rcx |
116 | rdmsr |
112 | rdmsr |
117 | btsl %edi, %eax |
113 | btsl %edi, %eax |
118 | wrmsr |
114 | wrmsr |
119 | ret |
115 | ret |
120 | 116 | ||
121 | read_efer_flag: |
117 | read_efer_flag: |
122 | movq $0xc0000080, %rcx |
118 | movq $0xc0000080, %rcx |
123 | rdmsr |
119 | rdmsr |
124 | ret |
120 | ret |
125 | 121 | ||
126 | # Push all general purpose registers on stack except %rbp, %rsp |
122 | # Push all general purpose registers on stack except %rbp, %rsp |
127 | .macro push_all_gpr |
123 | .macro push_all_gpr |
128 | pushq %rax |
124 | pushq %rax |
129 | pushq %rbx |
125 | pushq %rbx |
130 | pushq %rcx |
126 | pushq %rcx |
131 | pushq %rdx |
127 | pushq %rdx |
132 | pushq %rsi |
128 | pushq %rsi |
133 | pushq %rdi |
129 | pushq %rdi |
134 | pushq %r8 |
130 | pushq %r8 |
135 | pushq %r9 |
131 | pushq %r9 |
136 | pushq %r10 |
132 | pushq %r10 |
137 | pushq %r11 |
133 | pushq %r11 |
138 | pushq %r12 |
134 | pushq %r12 |
139 | pushq %r13 |
135 | pushq %r13 |
140 | pushq %r14 |
136 | pushq %r14 |
141 | pushq %r15 |
137 | pushq %r15 |
142 | .endm |
138 | .endm |
143 | 139 | ||
144 | .macro pop_all_gpr |
140 | .macro pop_all_gpr |
145 | popq %r15 |
141 | popq %r15 |
146 | popq %r14 |
142 | popq %r14 |
147 | popq %r13 |
143 | popq %r13 |
148 | popq %r12 |
144 | popq %r12 |
149 | popq %r11 |
145 | popq %r11 |
150 | popq %r10 |
146 | popq %r10 |
151 | popq %r9 |
147 | popq %r9 |
152 | popq %r8 |
148 | popq %r8 |
153 | popq %rdi |
149 | popq %rdi |
154 | popq %rsi |
150 | popq %rsi |
155 | popq %rdx |
151 | popq %rdx |
156 | popq %rcx |
152 | popq %rcx |
157 | popq %rbx |
153 | popq %rbx |
158 | popq %rax |
154 | popq %rax |
159 | .endm |
155 | .endm |
160 | 156 | ||
161 | ## Declare interrupt handlers |
157 | ## Declare interrupt handlers |
162 | # |
158 | # |
163 | # Declare interrupt handlers for n interrupt |
159 | # Declare interrupt handlers for n interrupt |
164 | # vectors starting at vector i. |
160 | # vectors starting at vector i. |
165 | # |
161 | # |
166 | # The handlers setup data segment registers |
162 | # The handlers setup data segment registers |
167 | # and call trap_dispatcher(). |
163 | # and call trap_dispatcher(). |
168 | # |
164 | # |
169 | .macro handler i n |
165 | .macro handler i n |
170 | pushq %rbp |
166 | pushq %rbp |
171 | movq %rsp,%rbp |
167 | movq %rsp,%rbp |
172 | 168 | ||
173 | push_all_gpr |
169 | push_all_gpr |
174 | 170 | ||
175 | movq $(\i),%rdi # %rdi - first parameter |
171 | movq $(\i),%rdi # %rdi - first parameter |
176 | movq %rbp, %rsi |
172 | movq %rbp, %rsi |
177 | addq $8, %rsi # %rsi - second parameter - original stack |
173 | addq $8, %rsi # %rsi - second parameter - original stack |
178 | call trap_dispatcher # trap_dispatcher(i, stack) |
174 | call trap_dispatcher # trap_dispatcher(i, stack) |
179 | 175 | ||
180 | # Test if this is interrupt with error word or not |
176 | # Test if this is interrupt with error word or not |
181 | mov $\i,%cl; |
177 | mov $\i,%cl; |
182 | movl $1,%eax; |
178 | movl $1,%eax; |
183 | test $0xe0,%cl; |
179 | test $0xe0,%cl; |
184 | jnz 0f; |
180 | jnz 0f; |
185 | and $0x1f,%cl; |
181 | and $0x1f,%cl; |
186 | shl %cl,%eax; |
182 | shl %cl,%eax; |
187 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
183 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
188 | jz 0f; |
184 | jz 0f; |
189 | 185 | ||
190 | 186 | ||
191 | # Return with error word |
187 | # Return with error word |
192 | pop_all_gpr |
188 | pop_all_gpr |
193 | 189 | ||
194 | popq %rbp; |
190 | popq %rbp; |
195 | add $8,%esp; # Skip error word |
191 | add $8,%esp; # Skip error word |
196 | iretq |
192 | iretq |
197 | 193 | ||
198 | 0: |
194 | 0: |
199 | # Return with no error word |
195 | # Return with no error word |
200 | pop_all_gpr |
196 | pop_all_gpr |
201 | 197 | ||
202 | popq %rbp |
198 | popq %rbp |
203 | iretq |
199 | iretq |
204 | 200 | ||
205 | .if (\n-\i)-1 |
201 | .if (\n-\i)-1 |
206 | handler "(\i+1)",\n |
202 | handler "(\i+1)",\n |
207 | .endif |
203 | .endif |
208 | .endm |
204 | .endm |
209 | 205 | ||
210 | interrupt_handlers: |
206 | interrupt_handlers: |
211 | h_start: |
207 | h_start: |
212 | handler 0 IDT_ITEMS |
208 | handler 0 IDT_ITEMS |
213 | h_end: |
209 | h_end: |
214 | 210 | ||
215 | 211 | ||
216 | .data |
212 | .data |
217 | .global interrupt_handler_size |
213 | .global interrupt_handler_size |
218 | 214 | ||
219 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
215 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
220 | 216 |