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1 | # |
1 | # |
2 | # Copyright (c) 2005 Ondrej Palkovsky |
2 | # Copyright (c) 2005 Ondrej Palkovsky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #define IREGISTER_SPACE 120 |
29 | #define IREGISTER_SPACE 120 |
30 | 30 | ||
31 | #define IOFFSET_RAX 0x0 |
31 | #define IOFFSET_RAX 0x0 |
32 | #define IOFFSET_RBX 0x8 |
32 | #define IOFFSET_RBX 0x8 |
33 | #define IOFFSET_RCX 0x10 |
33 | #define IOFFSET_RCX 0x10 |
34 | #define IOFFSET_RDX 0x18 |
34 | #define IOFFSET_RDX 0x18 |
35 | #define IOFFSET_RSI 0x20 |
35 | #define IOFFSET_RSI 0x20 |
36 | #define IOFFSET_RDI 0x28 |
36 | #define IOFFSET_RDI 0x28 |
37 | #define IOFFSET_R8 0x30 |
37 | #define IOFFSET_R8 0x30 |
38 | #define IOFFSET_R9 0x38 |
38 | #define IOFFSET_R9 0x38 |
39 | #define IOFFSET_R10 0x40 |
39 | #define IOFFSET_R10 0x40 |
40 | #define IOFFSET_R11 0x48 |
40 | #define IOFFSET_R11 0x48 |
41 | #define IOFFSET_R12 0x50 |
41 | #define IOFFSET_R12 0x50 |
42 | #define IOFFSET_R13 0x58 |
42 | #define IOFFSET_R13 0x58 |
43 | #define IOFFSET_R14 0x60 |
43 | #define IOFFSET_R14 0x60 |
44 | #define IOFFSET_R15 0x68 |
44 | #define IOFFSET_R15 0x68 |
45 | #define IOFFSET_RBP 0x70 |
45 | #define IOFFSET_RBP 0x70 |
46 | 46 | ||
47 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
47 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
48 | # and 1 means interrupt with error word |
48 | # and 1 means interrupt with error word |
49 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
49 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
50 | 50 | ||
51 | #include <arch/pm.h> |
51 | #include <arch/pm.h> |
52 | #include <arch/mm/page.h> |
52 | #include <arch/mm/page.h> |
53 | 53 | ||
54 | .text |
54 | .text |
55 | .global interrupt_handlers |
55 | .global interrupt_handlers |
56 | .global syscall_entry |
56 | .global syscall_entry |
57 | .global panic_printf |
57 | .global panic_printf |
58 | 58 | ||
59 | panic_printf: |
59 | panic_printf: |
60 | movq $halt, (%rsp) |
60 | movq $halt, (%rsp) |
61 | jmp printf |
61 | jmp printf |
62 | 62 | ||
63 | .global cpuid |
63 | .global cpuid |
64 | .global has_cpuid |
64 | .global has_cpuid |
65 | .global get_cycle |
65 | .global get_cycle |
66 | .global read_efer_flag |
66 | .global read_efer_flag |
67 | .global set_efer_flag |
67 | .global set_efer_flag |
- | 68 | .global memsetb |
|
- | 69 | .global memsetw |
|
68 | .global memcpy |
70 | .global memcpy |
69 | .global memcpy_from_uspace |
71 | .global memcpy_from_uspace |
70 | .global memcpy_to_uspace |
72 | .global memcpy_to_uspace |
71 | .global memcpy_from_uspace_failover_address |
73 | .global memcpy_from_uspace_failover_address |
72 | .global memcpy_to_uspace_failover_address |
74 | .global memcpy_to_uspace_failover_address |
73 | 75 | ||
- | 76 | # Wrapper for generic memsetb |
|
- | 77 | memsetb: |
|
- | 78 | jmp _memsetb |
|
- | 79 | ||
- | 80 | # Wrapper for generic memsetw |
|
- | 81 | memsetw: |
|
- | 82 | jmp _memsetw |
|
- | 83 | ||
74 | #define MEMCPY_DST %rdi |
84 | #define MEMCPY_DST %rdi |
75 | #define MEMCPY_SRC %rsi |
85 | #define MEMCPY_SRC %rsi |
76 | #define MEMCPY_SIZE %rdx |
86 | #define MEMCPY_SIZE %rdx |
77 | 87 | ||
78 | /** |
88 | /** |
79 | * Copy memory from/to userspace. |
89 | * Copy memory from/to userspace. |
80 | * |
90 | * |
81 | * This is almost conventional memcpy(). |
91 | * This is almost conventional memcpy(). |
82 | * The difference is that there is a failover part |
92 | * The difference is that there is a failover part |
83 | * to where control is returned from a page fault if |
93 | * to where control is returned from a page fault if |
84 | * the page fault occurs during copy_from_uspace() |
94 | * the page fault occurs during copy_from_uspace() |
85 | * or copy_to_uspace(). |
95 | * or copy_to_uspace(). |
86 | * |
96 | * |
87 | * @param MEMCPY_DST Destination address. |
97 | * @param MEMCPY_DST Destination address. |
88 | * @param MEMCPY_SRC Source address. |
98 | * @param MEMCPY_SRC Source address. |
89 | * @param MEMCPY_SIZE Number of bytes to copy. |
99 | * @param MEMCPY_SIZE Number of bytes to copy. |
90 | * |
100 | * |
91 | * @retrun MEMCPY_SRC on success, 0 on failure. |
101 | * @retrun MEMCPY_SRC on success, 0 on failure. |
92 | */ |
102 | */ |
93 | memcpy: |
103 | memcpy: |
94 | memcpy_from_uspace: |
104 | memcpy_from_uspace: |
95 | memcpy_to_uspace: |
105 | memcpy_to_uspace: |
96 | movq MEMCPY_SRC, %rax |
106 | movq MEMCPY_SRC, %rax |
97 | 107 | ||
98 | movq MEMCPY_SIZE, %rcx |
108 | movq MEMCPY_SIZE, %rcx |
99 | shrq $3, %rcx /* size / 8 */ |
109 | shrq $3, %rcx /* size / 8 */ |
100 | 110 | ||
101 | rep movsq /* copy as much as possible word by word */ |
111 | rep movsq /* copy as much as possible word by word */ |
102 | 112 | ||
103 | movq MEMCPY_SIZE, %rcx |
113 | movq MEMCPY_SIZE, %rcx |
104 | andq $7, %rcx /* size % 8 */ |
114 | andq $7, %rcx /* size % 8 */ |
105 | jz 0f |
115 | jz 0f |
106 | 116 | ||
107 | rep movsb /* copy the rest byte by byte */ |
117 | rep movsb /* copy the rest byte by byte */ |
108 | 118 | ||
109 | 0: |
119 | 0: |
110 | ret /* return MEMCPY_SRC, success */ |
120 | ret /* return MEMCPY_SRC, success */ |
111 | 121 | ||
112 | memcpy_from_uspace_failover_address: |
122 | memcpy_from_uspace_failover_address: |
113 | memcpy_to_uspace_failover_address: |
123 | memcpy_to_uspace_failover_address: |
114 | xorq %rax, %rax /* return 0, failure */ |
124 | xorq %rax, %rax /* return 0, failure */ |
115 | ret |
125 | ret |
116 | 126 | ||
117 | ## Determine CPUID support |
127 | ## Determine CPUID support |
118 | # |
128 | # |
119 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
129 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
120 | # |
130 | # |
121 | has_cpuid: |
131 | has_cpuid: |
122 | pushfq # store flags |
132 | pushfq # store flags |
123 | popq %rax # read flags |
133 | popq %rax # read flags |
124 | movq %rax,%rdx # copy flags |
134 | movq %rax,%rdx # copy flags |
125 | btcl $21,%edx # swap the ID bit |
135 | btcl $21,%edx # swap the ID bit |
126 | pushq %rdx |
136 | pushq %rdx |
127 | popfq # propagate the change into flags |
137 | popfq # propagate the change into flags |
128 | pushfq |
138 | pushfq |
129 | popq %rdx # read flags |
139 | popq %rdx # read flags |
130 | andl $(1<<21),%eax # interested only in ID bit |
140 | andl $(1<<21),%eax # interested only in ID bit |
131 | andl $(1<<21),%edx |
141 | andl $(1<<21),%edx |
132 | xorl %edx,%eax # 0 if not supported, 1 if supported |
142 | xorl %edx,%eax # 0 if not supported, 1 if supported |
133 | ret |
143 | ret |
134 | 144 | ||
135 | cpuid: |
145 | cpuid: |
136 | movq %rbx, %r10 # we have to preserve rbx across function calls |
146 | movq %rbx, %r10 # we have to preserve rbx across function calls |
137 | 147 | ||
138 | movl %edi,%eax # load the command into %eax |
148 | movl %edi,%eax # load the command into %eax |
139 | 149 | ||
140 | cpuid |
150 | cpuid |
141 | movl %eax,0(%rsi) |
151 | movl %eax,0(%rsi) |
142 | movl %ebx,4(%rsi) |
152 | movl %ebx,4(%rsi) |
143 | movl %ecx,8(%rsi) |
153 | movl %ecx,8(%rsi) |
144 | movl %edx,12(%rsi) |
154 | movl %edx,12(%rsi) |
145 | 155 | ||
146 | movq %r10, %rbx |
156 | movq %r10, %rbx |
147 | ret |
157 | ret |
148 | 158 | ||
149 | get_cycle: |
159 | get_cycle: |
150 | xorq %rax,%rax |
160 | xorq %rax,%rax |
151 | rdtsc |
161 | rdtsc |
152 | ret |
162 | ret |
153 | 163 | ||
154 | set_efer_flag: |
164 | set_efer_flag: |
155 | movq $0xc0000080, %rcx |
165 | movq $0xc0000080, %rcx |
156 | rdmsr |
166 | rdmsr |
157 | btsl %edi, %eax |
167 | btsl %edi, %eax |
158 | wrmsr |
168 | wrmsr |
159 | ret |
169 | ret |
160 | 170 | ||
161 | read_efer_flag: |
171 | read_efer_flag: |
162 | movq $0xc0000080, %rcx |
172 | movq $0xc0000080, %rcx |
163 | rdmsr |
173 | rdmsr |
164 | ret |
174 | ret |
165 | 175 | ||
166 | # Push all general purpose registers on stack except %rbp, %rsp |
176 | # Push all general purpose registers on stack except %rbp, %rsp |
167 | .macro save_all_gpr |
177 | .macro save_all_gpr |
168 | movq %rax, IOFFSET_RAX(%rsp) |
178 | movq %rax, IOFFSET_RAX(%rsp) |
169 | movq %rcx, IOFFSET_RCX(%rsp) |
179 | movq %rcx, IOFFSET_RCX(%rsp) |
170 | movq %rdx, IOFFSET_RDX(%rsp) |
180 | movq %rdx, IOFFSET_RDX(%rsp) |
171 | movq %rsi, IOFFSET_RSI(%rsp) |
181 | movq %rsi, IOFFSET_RSI(%rsp) |
172 | movq %rdi, IOFFSET_RDI(%rsp) |
182 | movq %rdi, IOFFSET_RDI(%rsp) |
173 | movq %r8, IOFFSET_R8(%rsp) |
183 | movq %r8, IOFFSET_R8(%rsp) |
174 | movq %r9, IOFFSET_R9(%rsp) |
184 | movq %r9, IOFFSET_R9(%rsp) |
175 | movq %r10, IOFFSET_R10(%rsp) |
185 | movq %r10, IOFFSET_R10(%rsp) |
176 | movq %r11, IOFFSET_R11(%rsp) |
186 | movq %r11, IOFFSET_R11(%rsp) |
177 | #ifdef CONFIG_DEBUG_ALLREGS |
187 | #ifdef CONFIG_DEBUG_ALLREGS |
178 | movq %rbx, IOFFSET_RBX(%rsp) |
188 | movq %rbx, IOFFSET_RBX(%rsp) |
179 | movq %rbp, IOFFSET_RBP(%rsp) |
189 | movq %rbp, IOFFSET_RBP(%rsp) |
180 | movq %r12, IOFFSET_R12(%rsp) |
190 | movq %r12, IOFFSET_R12(%rsp) |
181 | movq %r13, IOFFSET_R13(%rsp) |
191 | movq %r13, IOFFSET_R13(%rsp) |
182 | movq %r14, IOFFSET_R14(%rsp) |
192 | movq %r14, IOFFSET_R14(%rsp) |
183 | movq %r15, IOFFSET_R15(%rsp) |
193 | movq %r15, IOFFSET_R15(%rsp) |
184 | #endif |
194 | #endif |
185 | .endm |
195 | .endm |
186 | 196 | ||
187 | .macro restore_all_gpr |
197 | .macro restore_all_gpr |
188 | movq IOFFSET_RAX(%rsp), %rax |
198 | movq IOFFSET_RAX(%rsp), %rax |
189 | movq IOFFSET_RCX(%rsp), %rcx |
199 | movq IOFFSET_RCX(%rsp), %rcx |
190 | movq IOFFSET_RDX(%rsp), %rdx |
200 | movq IOFFSET_RDX(%rsp), %rdx |
191 | movq IOFFSET_RSI(%rsp), %rsi |
201 | movq IOFFSET_RSI(%rsp), %rsi |
192 | movq IOFFSET_RDI(%rsp), %rdi |
202 | movq IOFFSET_RDI(%rsp), %rdi |
193 | movq IOFFSET_R8(%rsp), %r8 |
203 | movq IOFFSET_R8(%rsp), %r8 |
194 | movq IOFFSET_R9(%rsp), %r9 |
204 | movq IOFFSET_R9(%rsp), %r9 |
195 | movq IOFFSET_R10(%rsp), %r10 |
205 | movq IOFFSET_R10(%rsp), %r10 |
196 | movq IOFFSET_R11(%rsp), %r11 |
206 | movq IOFFSET_R11(%rsp), %r11 |
197 | #ifdef CONFIG_DEBUG_ALLREGS |
207 | #ifdef CONFIG_DEBUG_ALLREGS |
198 | movq IOFFSET_RBX(%rsp), %rbx |
208 | movq IOFFSET_RBX(%rsp), %rbx |
199 | movq IOFFSET_RBP(%rsp), %rbp |
209 | movq IOFFSET_RBP(%rsp), %rbp |
200 | movq IOFFSET_R12(%rsp), %r12 |
210 | movq IOFFSET_R12(%rsp), %r12 |
201 | movq IOFFSET_R13(%rsp), %r13 |
211 | movq IOFFSET_R13(%rsp), %r13 |
202 | movq IOFFSET_R14(%rsp), %r14 |
212 | movq IOFFSET_R14(%rsp), %r14 |
203 | movq IOFFSET_R15(%rsp), %r15 |
213 | movq IOFFSET_R15(%rsp), %r15 |
204 | #endif |
214 | #endif |
205 | .endm |
215 | .endm |
206 | 216 | ||
207 | #ifdef CONFIG_DEBUG_ALLREGS |
217 | #ifdef CONFIG_DEBUG_ALLREGS |
208 | # define INTERRUPT_ALIGN 256 |
218 | # define INTERRUPT_ALIGN 256 |
209 | #else |
219 | #else |
210 | # define INTERRUPT_ALIGN 128 |
220 | # define INTERRUPT_ALIGN 128 |
211 | #endif |
221 | #endif |
212 | 222 | ||
213 | ## Declare interrupt handlers |
223 | ## Declare interrupt handlers |
214 | # |
224 | # |
215 | # Declare interrupt handlers for n interrupt |
225 | # Declare interrupt handlers for n interrupt |
216 | # vectors starting at vector i. |
226 | # vectors starting at vector i. |
217 | # |
227 | # |
218 | # The handlers call exc_dispatch(). |
228 | # The handlers call exc_dispatch(). |
219 | # |
229 | # |
220 | .macro handler i n |
230 | .macro handler i n |
221 | 231 | ||
222 | /* |
232 | /* |
223 | * Choose between version with error code and version without error |
233 | * Choose between version with error code and version without error |
224 | * code. Both versions have to be of the same size. amd64 assembly is, |
234 | * code. Both versions have to be of the same size. amd64 assembly is, |
225 | * however, a little bit tricky. For instance, subq $0x80, %rsp and |
235 | * however, a little bit tricky. For instance, subq $0x80, %rsp and |
226 | * subq $0x78, %rsp can result in two instructions with different |
236 | * subq $0x78, %rsp can result in two instructions with different |
227 | * op-code lengths. |
237 | * op-code lengths. |
228 | * Therefore we align the interrupt handlers. |
238 | * Therefore we align the interrupt handlers. |
229 | */ |
239 | */ |
230 | 240 | ||
231 | .iflt \i-32 |
241 | .iflt \i-32 |
232 | .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST |
242 | .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST |
233 | /* |
243 | /* |
234 | * Version with error word. |
244 | * Version with error word. |
235 | */ |
245 | */ |
236 | subq $IREGISTER_SPACE, %rsp |
246 | subq $IREGISTER_SPACE, %rsp |
237 | .else |
247 | .else |
238 | /* |
248 | /* |
239 | * Version without error word, |
249 | * Version without error word, |
240 | */ |
250 | */ |
241 | subq $(IREGISTER_SPACE+8), %rsp |
251 | subq $(IREGISTER_SPACE+8), %rsp |
242 | .endif |
252 | .endif |
243 | .else |
253 | .else |
244 | /* |
254 | /* |
245 | * Version without error word, |
255 | * Version without error word, |
246 | */ |
256 | */ |
247 | subq $(IREGISTER_SPACE+8), %rsp |
257 | subq $(IREGISTER_SPACE+8), %rsp |
248 | .endif |
258 | .endif |
249 | 259 | ||
250 | save_all_gpr |
260 | save_all_gpr |
251 | cld |
261 | cld |
252 | 262 | ||
253 | movq $(\i), %rdi # %rdi - first parameter |
263 | movq $(\i), %rdi # %rdi - first parameter |
254 | movq %rsp, %rsi # %rsi - pointer to istate |
264 | movq %rsp, %rsi # %rsi - pointer to istate |
255 | call exc_dispatch # exc_dispatch(i, istate) |
265 | call exc_dispatch # exc_dispatch(i, istate) |
256 | 266 | ||
257 | restore_all_gpr |
267 | restore_all_gpr |
258 | # $8 = Skip error word |
268 | # $8 = Skip error word |
259 | addq $(IREGISTER_SPACE+8), %rsp |
269 | addq $(IREGISTER_SPACE+8), %rsp |
260 | iretq |
270 | iretq |
261 | 271 | ||
262 | .align INTERRUPT_ALIGN |
272 | .align INTERRUPT_ALIGN |
263 | .if (\n-\i)-1 |
273 | .if (\n-\i)-1 |
264 | handler "(\i+1)",\n |
274 | handler "(\i+1)",\n |
265 | .endif |
275 | .endif |
266 | .endm |
276 | .endm |
267 | 277 | ||
268 | .align INTERRUPT_ALIGN |
278 | .align INTERRUPT_ALIGN |
269 | interrupt_handlers: |
279 | interrupt_handlers: |
270 | h_start: |
280 | h_start: |
271 | handler 0 IDT_ITEMS |
281 | handler 0 IDT_ITEMS |
272 | h_end: |
282 | h_end: |
273 | 283 | ||
274 | ## Low-level syscall handler |
284 | ## Low-level syscall handler |
275 | # |
285 | # |
276 | # Registers on entry: |
286 | # Registers on entry: |
277 | # |
287 | # |
278 | # @param rcx Userspace return address. |
288 | # @param rcx Userspace return address. |
279 | # @param r11 Userspace RLFAGS. |
289 | # @param r11 Userspace RLFAGS. |
280 | # |
290 | # |
281 | # @param rax Syscall number. |
291 | # @param rax Syscall number. |
282 | # @param rdi 1st syscall argument. |
292 | # @param rdi 1st syscall argument. |
283 | # @param rsi 2nd syscall argument. |
293 | # @param rsi 2nd syscall argument. |
284 | # @param rdx 3rd syscall argument. |
294 | # @param rdx 3rd syscall argument. |
285 | # @param r10 4th syscall argument. Used instead of RCX because the |
295 | # @param r10 4th syscall argument. Used instead of RCX because the |
286 | # SYSCALL instruction clobbers it. |
296 | # SYSCALL instruction clobbers it. |
287 | # @param r8 5th syscall argument. |
297 | # @param r8 5th syscall argument. |
288 | # @param r9 6th syscall argument. |
298 | # @param r9 6th syscall argument. |
289 | # |
299 | # |
290 | # @return Return value is in rax. |
300 | # @return Return value is in rax. |
291 | # |
301 | # |
292 | syscall_entry: |
302 | syscall_entry: |
293 | swapgs # Switch to hidden gs |
303 | swapgs # Switch to hidden gs |
294 | # |
304 | # |
295 | # %gs:0 Scratch space for this thread's user RSP |
305 | # %gs:0 Scratch space for this thread's user RSP |
296 | # %gs:8 Address to be used as this thread's kernel RSP |
306 | # %gs:8 Address to be used as this thread's kernel RSP |
297 | # |
307 | # |
298 | movq %rsp, %gs:0 # Save this thread's user RSP |
308 | movq %rsp, %gs:0 # Save this thread's user RSP |
299 | movq %gs:8, %rsp # Set this thread's kernel RSP |
309 | movq %gs:8, %rsp # Set this thread's kernel RSP |
300 | swapgs # Switch back to remain consistent |
310 | swapgs # Switch back to remain consistent |
301 | sti |
311 | sti |
302 | 312 | ||
303 | pushq %rcx |
313 | pushq %rcx |
304 | pushq %r11 |
314 | pushq %r11 |
305 | 315 | ||
306 | movq %r10, %rcx # Copy the 4th argument where it is expected |
316 | movq %r10, %rcx # Copy the 4th argument where it is expected |
307 | pushq %rax |
317 | pushq %rax |
308 | call syscall_handler |
318 | call syscall_handler |
309 | addq $8, %rsp |
319 | addq $8, %rsp |
310 | 320 | ||
311 | popq %r11 |
321 | popq %r11 |
312 | popq %rcx |
322 | popq %rcx |
313 | 323 | ||
314 | cli |
324 | cli |
315 | swapgs |
325 | swapgs |
316 | movq %gs:0, %rsp # Restore the user RSP |
326 | movq %gs:0, %rsp # Restore the user RSP |
317 | swapgs |
327 | swapgs |
318 | 328 | ||
319 | sysretq |
329 | sysretq |
320 | 330 | ||
321 | .data |
331 | .data |
322 | .global interrupt_handler_size |
332 | .global interrupt_handler_size |
323 | 333 | ||
324 | interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS |
334 | interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS |
325 | 335 |