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/*
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/*
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 * Copyright (c) 2005 Ondrej Palkovsky
2
 * Copyright (c) 2005 Ondrej Palkovsky
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 * All rights reserved.
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 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup amd64
29
/** @addtogroup amd64
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 */
33
 */
34
 
34
 
35
#include <arch.h>
35
#include <arch.h>
36
 
36
 
37
#include <arch/types.h>
37
#include <arch/types.h>
38
 
38
 
39
#include <config.h>
39
#include <config.h>
40
 
40
 
41
#include <proc/thread.h>
41
#include <proc/thread.h>
-
 
42
#include <genarch/multiboot/multiboot.h>
42
#include <genarch/drivers/legacy/ia32/io.h>
43
#include <genarch/drivers/legacy/ia32/io.h>
43
#include <genarch/drivers/ega/ega.h>
44
#include <genarch/drivers/ega/ega.h>
44
#include <arch/drivers/vesa.h>
45
#include <arch/drivers/vesa.h>
45
#include <genarch/kbd/i8042.h>
46
#include <genarch/kbd/i8042.h>
46
#include <arch/drivers/i8254.h>
47
#include <arch/drivers/i8254.h>
47
#include <arch/drivers/i8259.h>
48
#include <arch/drivers/i8259.h>
-
 
49
#include <arch/boot/boot.h>
48
 
50
 
49
#ifdef CONFIG_SMP
51
#ifdef CONFIG_SMP
50
#include <arch/smp/apic.h>
52
#include <arch/smp/apic.h>
51
#endif
53
#endif
52
 
54
 
53
#include <arch/bios/bios.h>
55
#include <arch/bios/bios.h>
54
#include <arch/cpu.h>
56
#include <arch/cpu.h>
55
#include <print.h>
57
#include <print.h>
56
#include <arch/cpuid.h>
58
#include <arch/cpuid.h>
57
#include <genarch/acpi/acpi.h>
59
#include <genarch/acpi/acpi.h>
58
#include <panic.h>
60
#include <panic.h>
59
#include <interrupt.h>
61
#include <interrupt.h>
60
#include <arch/syscall.h>
62
#include <arch/syscall.h>
61
#include <arch/debugger.h>
63
#include <arch/debugger.h>
62
#include <syscall/syscall.h>
64
#include <syscall/syscall.h>
63
#include <console/console.h>
65
#include <console/console.h>
64
#include <ddi/irq.h>
66
#include <ddi/irq.h>
65
#include <ddi/device.h>
67
#include <ddi/device.h>
66
#include <sysinfo/sysinfo.h>
68
#include <sysinfo/sysinfo.h>
67
 
69
 
68
 
-
 
69
/** Disable I/O on non-privileged levels
70
/** Disable I/O on non-privileged levels
70
 *
71
 *
71
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
72
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
72
 */
73
 */
73
static void clean_IOPL_NT_flags(void)
74
static void clean_IOPL_NT_flags(void)
74
{
75
{
75
    asm volatile (
76
    asm volatile (
76
        "pushfq\n"
77
        "pushfq\n"
77
        "pop %%rax\n"
78
        "pop %%rax\n"
78
        "and $~(0x7000), %%rax\n"
79
        "and $~(0x7000), %%rax\n"
79
        "pushq %%rax\n"
80
        "pushq %%rax\n"
80
        "popfq\n"
81
        "popfq\n"
81
        ::: "%rax"
82
        ::: "%rax"
82
    );
83
    );
83
}
84
}
84
 
85
 
85
/** Disable alignment check
86
/** Disable alignment check
86
 *
87
 *
87
 * Clean AM(18) flag in CR0 register
88
 * Clean AM(18) flag in CR0 register
88
 */
89
 */
89
static void clean_AM_flag(void)
90
static void clean_AM_flag(void)
90
{
91
{
91
    asm volatile (
92
    asm volatile (
92
        "mov %%cr0, %%rax\n"
93
        "mov %%cr0, %%rax\n"
93
        "and $~(0x40000), %%rax\n"
94
        "and $~(0x40000), %%rax\n"
94
        "mov %%rax, %%cr0\n"
95
        "mov %%rax, %%cr0\n"
95
        ::: "%rax"
96
        ::: "%rax"
96
    );
97
    );
97
}
98
}
-
 
99
 
-
 
100
/** Perform amd64-specific initialization before main_bsp() is called.
-
 
101
 *
-
 
102
 * @param signature Should contain the multiboot signature.
-
 
103
 * @param mi        Pointer to the multiboot information structure.
-
 
104
 */
-
 
105
void arch_pre_main(uint32_t signature, const multiboot_info_t *mi)
-
 
106
{
-
 
107
    /* Parse multiboot information obtained from the bootloader. */
-
 
108
    multiboot_info_parse(signature, mi);
-
 
109
   
-
 
110
#ifdef CONFIG_SMP
-
 
111
    /* Copy AP bootstrap routines below 1 MB. */
-
 
112
    memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
-
 
113
        (size_t) &_hardcoded_unmapped_size);
-
 
114
#endif
-
 
115
}
98
 
116
 
99
void arch_pre_mm_init(void)
117
void arch_pre_mm_init(void)
100
{
118
{
101
    /* Enable no-execute pages */
119
    /* Enable no-execute pages */
102
    set_efer_flag(AMD_NXE_FLAG);
120
    set_efer_flag(AMD_NXE_FLAG);
103
    /* Enable FPU */
121
    /* Enable FPU */
104
    cpu_setup_fpu();
122
    cpu_setup_fpu();
105
 
123
 
106
    /* Initialize segmentation */
124
    /* Initialize segmentation */
107
    pm_init();
125
    pm_init();
108
   
126
   
109
    /* Disable I/O on nonprivileged levels
127
    /* Disable I/O on nonprivileged levels
110
     * clear the NT (nested-thread) flag
128
     * clear the NT (nested-thread) flag
111
     */
129
     */
112
    clean_IOPL_NT_flags();
130
    clean_IOPL_NT_flags();
113
    /* Disable alignment check */
131
    /* Disable alignment check */
114
    clean_AM_flag();
132
    clean_AM_flag();
115
 
133
 
116
    if (config.cpu_active == 1) {
134
    if (config.cpu_active == 1) {
117
        interrupt_init();
135
        interrupt_init();
118
        bios_init();
136
        bios_init();
119
       
137
       
120
        /* PIC */
138
        /* PIC */
121
        i8259_init();
139
        i8259_init();
122
    }
140
    }
123
}
141
}
124
 
142
 
125
 
143
 
126
void arch_post_mm_init(void)
144
void arch_post_mm_init(void)
127
{
145
{
128
    if (config.cpu_active == 1) {
146
    if (config.cpu_active == 1) {
129
        /* Initialize IRQ routing */
147
        /* Initialize IRQ routing */
130
        irq_init(IRQ_COUNT, IRQ_COUNT);
148
        irq_init(IRQ_COUNT, IRQ_COUNT);
131
       
149
       
132
        /* hard clock */
150
        /* hard clock */
133
        i8254_init();
151
        i8254_init();
134
               
152
               
135
#ifdef CONFIG_FB
153
#ifdef CONFIG_FB
136
        if (vesa_present())
154
        if (vesa_present())
137
            vesa_init();
155
            vesa_init();
138
        else
156
        else
139
#endif
157
#endif
140
            ega_init(EGA_BASE, EGA_VIDEORAM);   /* video */
158
            ega_init(EGA_BASE, EGA_VIDEORAM);   /* video */
141
       
159
       
142
        /* Enable debugger */
160
        /* Enable debugger */
143
        debugger_init();
161
        debugger_init();
144
        /* Merge all memory zones to 1 big zone */
162
        /* Merge all memory zones to 1 big zone */
145
        zone_merge_all();
163
        zone_merge_all();
146
    }
164
    }
147
   
165
   
148
    /* Setup fast SYSCALL/SYSRET */
166
    /* Setup fast SYSCALL/SYSRET */
149
    syscall_setup_cpu();
167
    syscall_setup_cpu();
150
}
168
}
151
 
169
 
152
void arch_post_cpu_init()
170
void arch_post_cpu_init()
153
{
171
{
154
#ifdef CONFIG_SMP
172
#ifdef CONFIG_SMP
155
    if (config.cpu_active > 1) {
173
    if (config.cpu_active > 1) {
156
        l_apic_init();
174
        l_apic_init();
157
        l_apic_debug();
175
        l_apic_debug();
158
    }
176
    }
159
#endif
177
#endif
160
}
178
}
161
 
179
 
162
void arch_pre_smp_init(void)
180
void arch_pre_smp_init(void)
163
{
181
{
164
    if (config.cpu_active == 1) {
182
    if (config.cpu_active == 1) {
165
#ifdef CONFIG_SMP
183
#ifdef CONFIG_SMP
166
        acpi_init();
184
        acpi_init();
167
#endif /* CONFIG_SMP */
185
#endif /* CONFIG_SMP */
168
    }
186
    }
169
}
187
}
170
 
188
 
171
void arch_post_smp_init(void)
189
void arch_post_smp_init(void)
172
{
190
{
173
    devno_t devno = device_assign_devno();
191
    devno_t devno = device_assign_devno();
174
    /* keyboard controller */
192
    /* keyboard controller */
175
    (void) i8042_init((i8042_t *) I8042_BASE, devno, IRQ_KBD);
193
    (void) i8042_init((i8042_t *) I8042_BASE, devno, IRQ_KBD);
176
 
194
 
177
    /*
195
    /*
178
     * This is the necessary evil until the userspace driver is entirely
196
     * This is the necessary evil until the userspace driver is entirely
179
     * self-sufficient.
197
     * self-sufficient.
180
     */
198
     */
181
    sysinfo_set_item_val("kbd", NULL, true);
199
    sysinfo_set_item_val("kbd", NULL, true);
182
    sysinfo_set_item_val("kbd.devno", NULL, devno);
200
    sysinfo_set_item_val("kbd.devno", NULL, devno);
183
    sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
201
    sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
184
}
202
}
185
 
203
 
186
void calibrate_delay_loop(void)
204
void calibrate_delay_loop(void)
187
{
205
{
188
    i8254_calibrate_delay_loop();
206
    i8254_calibrate_delay_loop();
189
    if (config.cpu_active == 1) {
207
    if (config.cpu_active == 1) {
190
        /*
208
        /*
191
         * This has to be done only on UP.
209
         * This has to be done only on UP.
192
         * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
210
         * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
193
         */
211
         */
194
        i8254_normal_operation();
212
        i8254_normal_operation();
195
    }
213
    }
196
}
214
}
197
 
215
 
198
/** Set thread-local-storage pointer
216
/** Set thread-local-storage pointer
199
 *
217
 *
200
 * TLS pointer is set in FS register. Unfortunately the 64-bit
218
 * TLS pointer is set in FS register. Unfortunately the 64-bit
201
 * part can be set only in CPL0 mode.
219
 * part can be set only in CPL0 mode.
202
 *
220
 *
203
 * The specs say, that on %fs:0 there is stored contents of %fs register,
221
 * The specs say, that on %fs:0 there is stored contents of %fs register,
204
 * we need not to go to CPL0 to read it.
222
 * we need not to go to CPL0 to read it.
205
 */
223
 */
206
unative_t sys_tls_set(unative_t addr)
224
unative_t sys_tls_set(unative_t addr)
207
{
225
{
208
    THREAD->arch.tls = addr;
226
    THREAD->arch.tls = addr;
209
    write_msr(AMD_MSR_FS, addr);
227
    write_msr(AMD_MSR_FS, addr);
210
    return 0;
228
    return 0;
211
}
229
}
212
 
230
 
213
/** Acquire console back for kernel
231
/** Acquire console back for kernel
214
 *
232
 *
215
 */
233
 */
216
void arch_grab_console(void)
234
void arch_grab_console(void)
217
{
235
{
218
#ifdef CONFIG_FB
236
#ifdef CONFIG_FB
219
    vesa_redraw();
237
    vesa_redraw();
220
#else
238
#else
221
    ega_redraw();
239
    ega_redraw();
222
#endif
240
#endif
223
}
241
}
224
 
242
 
225
/** Return console to userspace
243
/** Return console to userspace
226
 *
244
 *
227
 */
245
 */
228
void arch_release_console(void)
246
void arch_release_console(void)
229
{
247
{
230
}
248
}
231
 
249
 
232
/** Construct function pointer
250
/** Construct function pointer
233
 *
251
 *
234
 * @param fptr   function pointer structure
252
 * @param fptr   function pointer structure
235
 * @param addr   function address
253
 * @param addr   function address
236
 * @param caller calling function address
254
 * @param caller calling function address
237
 *
255
 *
238
 * @return address of the function pointer
256
 * @return address of the function pointer
239
 *
257
 *
240
 */
258
 */
241
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
259
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
242
{
260
{
243
    return addr;
261
    return addr;
244
}
262
}
245
 
263
 
246
/** @}
264
/** @}
247
 */
265
 */
248
 
266