WebSVN – HelenOS – Diff – /trunk/kernel/arch/amd64/src/amd64.c


/*
 * Copyright (c) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64
 * @{
 */
/** @file
 */
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <proc/thread.h>
#include <arch/drivers/ega.h>
#include <arch/drivers/vesa.h>
#include <genarch/kbd/i8042.h>
#include <arch/drivers/i8254.h>
#include <arch/drivers/i8259.h>
 
#ifdef CONFIG_SMP
#include <arch/smp/apic.h>
#endif
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
#include <console/console.h>
#include <ddi/irq.h>
#include <ddi/device.h>
 
 
/** Disable I/O on non-privileged levels
 *
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 */
static void clean_IOPL_NT_flags(void)
{
    asm (
 
        "pushfq\n"
        "pop %%rax\n"
        "and $~(0x7000), %%rax\n"
        "pushq %%rax\n"
        "popfq\n"
        :
        :
        : "%rax"
    );
}
 
/** Disable alignment check
 *
 * Clean AM(18) flag in CR0 register
 */
static void clean_AM_flag(void)
{
    asm (
 
        "mov %%cr0, %%rax\n"
        "and $~(0x40000), %%rax\n"
        "mov %%rax, %%cr0\n"
        :
        :
        : "%rax"
    );
}
 
void arch_pre_mm_init(void)
{
    /* Enable no-execute pages */
    set_efer_flag(AMD_NXE_FLAG);
    /* Enable FPU */
    cpu_setup_fpu();
 
    /* Initialize segmentation */
    pm_init();
   
    /* Disable I/O on nonprivileged levels
     * clear the NT (nested-thread) flag
     */
    clean_IOPL_NT_flags();
    /* Disable alignment check */
    clean_AM_flag();
 
    if (config.cpu_active == 1) {
        interrupt_init();
        bios_init();
       
        /* PIC */
        i8259_init();
    }
}
 
 
void arch_post_mm_init(void)
{
    if (config.cpu_active == 1) {
        /* Initialize IRQ routing */
        irq_init(IRQ_COUNT, IRQ_COUNT);
       
        /* hard clock */
        i8254_init();
               
#ifdef CONFIG_FB
        if (vesa_present())
            vesa_init();
        else
#endif
            ega_init(); /* video */
       
        /* Enable debugger */
        debugger_init();
        /* Merge all memory zones to 1 big zone */
        zone_merge_all();
    }
   
    /* Setup fast SYSCALL/SYSRET */
    syscall_setup_cpu();
 
}
 
void arch_post_cpu_init()
{
#ifdef CONFIG_SMP
    if (config.cpu_active > 1) {
        l_apic_init();
        l_apic_debug();
    }
#endif
}
 
void arch_pre_smp_init(void)
{
    if (config.cpu_active == 1) {
        memory_print_map();
       
        #ifdef CONFIG_SMP
        acpi_init();
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_smp_init(void)
{
    /* keyboard controller */
    i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);
}
 
void calibrate_delay_loop(void)
{
    i8254_calibrate_delay_loop();
    if (config.cpu_active == 1) {
        /*
         * This has to be done only on UP.
         * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
         */
        i8254_normal_operation();
    }
}
 
/** Set thread-local-storage pointer
 *
 * TLS pointer is set in FS register. Unfortunately the 64-bit
 * part can be set only in CPL0 mode.
 *
 * The specs say, that on %fs:0 there is stored contents of %fs register,
 * we need not to go to CPL0 to read it.
 */
unative_t sys_tls_set(unative_t addr)
{
    THREAD->arch.tls = addr;
    write_msr(AMD_MSR_FS, addr);
    return 0;
}
 
/** Acquire console back for kernel
 *
 */
void arch_grab_console(void)
{
    i8042_grab();
}
/** Return console to userspace
 *
 */
void arch_release_console(void)
{
    i8042_release();
}
 
/** @}
 */
 

Rev 2692	Rev 2697
1	/*	1	/*
2	* Copyright (c) 2005 Ondrej Palkovsky	2	* Copyright (c) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup amd64	29	/** @addtogroup amd64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch.h>	35	#include <arch.h>
36		36
37	#include <arch/types.h>	37	#include <arch/types.h>
38		38
39	#include <config.h>	39	#include <config.h>
40		40
41	#include <proc/thread.h>	41	#include <proc/thread.h>
42	#include <arch/drivers/ega.h>	42	#include <arch/drivers/ega.h>
43	#include <arch/drivers/vesa.h>	43	#include <arch/drivers/vesa.h>
44	#include <genarch/kbd/i8042.h>	44	#include <genarch/kbd/i8042.h>
45	#include <arch/drivers/i8254.h>	45	#include <arch/drivers/i8254.h>
46	#include <arch/drivers/i8259.h>	46	#include <arch/drivers/i8259.h>
47		47
48	#ifdef CONFIG_SMP	48	#ifdef CONFIG_SMP
49	#include <arch/smp/apic.h>	49	#include <arch/smp/apic.h>
50	#endif	50	#endif
51		51
52	#include <arch/bios/bios.h>	52	#include <arch/bios/bios.h>
53	#include <arch/mm/memory_init.h>	53	#include <arch/mm/memory_init.h>
54	#include <arch/cpu.h>	54	#include <arch/cpu.h>
55	#include <print.h>	55	#include <print.h>
56	#include <arch/cpuid.h>	56	#include <arch/cpuid.h>
57	#include <genarch/acpi/acpi.h>	57	#include <genarch/acpi/acpi.h>
58	#include <panic.h>	58	#include <panic.h>
59	#include <interrupt.h>	59	#include <interrupt.h>
60	#include <arch/syscall.h>	60	#include <arch/syscall.h>
61	#include <arch/debugger.h>	61	#include <arch/debugger.h>
62	#include <syscall/syscall.h>	62	#include <syscall/syscall.h>
63	#include <console/console.h>	63	#include <console/console.h>
64	#include <ddi/irq.h>	64	#include <ddi/irq.h>
65	#include <ddi/device.h>	65	#include <ddi/device.h>
66		66
67		67
68	/** Disable I/O on non-privileged levels	68	/** Disable I/O on non-privileged levels
69	*	69	*
70	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register	70	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
71	*/	71	*/
72	static void clean_IOPL_NT_flags(void)	72	static void clean_IOPL_NT_flags(void)
73	{	73	{
74	asm	74	asm (
75	(	-
76	"pushfq;"	75	"pushfq\n"
77	"pop %%rax;"	76	"pop %%rax\n"
78	"and $~(0x7000),%%rax;"	77	"and $~(0x7000), %%rax\n"
79	"pushq %%rax;"	78	"pushq %%rax\n"
80	"popfq;"	79	"popfq\n"
81	:	80	:
82	:	81	:
83	:"%rax"	82	: "%rax"
84	);	83	);
85	}	84	}
86		85
87	/** Disable alignment check	86	/** Disable alignment check
88	*	87	*
89	* Clean AM(18) flag in CR0 register	88	* Clean AM(18) flag in CR0 register
90	*/	89	*/
91	static void clean_AM_flag(void)	90	static void clean_AM_flag(void)
92	{	91	{
93	asm	92	asm (
94	(	-
95	"mov %%cr0,%%rax;"	93	"mov %%cr0, %%rax\n"
96	"and $~(0x40000),%%rax;"	94	"and $~(0x40000), %%rax\n"
97	"mov %%rax,%%cr0;"	95	"mov %%rax, %%cr0\n"
98	:	96	:
99	:	97	:
100	:"%rax"	98	: "%rax"
101	);	99	);
102	}	100	}
103		101
104	void arch_pre_mm_init(void)	102	void arch_pre_mm_init(void)
105	{	103	{
106	/* Enable no-execute pages */	104	/* Enable no-execute pages */
107	set_efer_flag(AMD_NXE_FLAG);	105	set_efer_flag(AMD_NXE_FLAG);
108	/* Enable FPU */	106	/* Enable FPU */
109	cpu_setup_fpu();	107	cpu_setup_fpu();
110		108
111	/* Initialize segmentation */	109	/* Initialize segmentation */
112	pm_init();	110	pm_init();
113		111
114	/* Disable I/O on nonprivileged levels	112	/* Disable I/O on nonprivileged levels
115	* clear the NT (nested-thread) flag	113	* clear the NT (nested-thread) flag
116	*/	114	*/
117	clean_IOPL_NT_flags();	115	clean_IOPL_NT_flags();
118	/* Disable alignment check */	116	/* Disable alignment check */
119	clean_AM_flag();	117	clean_AM_flag();
120		118
121	if (config.cpu_active == 1) {	119	if (config.cpu_active == 1) {
122	interrupt_init();	120	interrupt_init();
123	bios_init();	121	bios_init();
124		122
125	/* PIC */	123	/* PIC */
126	i8259_init();	124	i8259_init();
127	}	125	}
128	}	126	}
129		127
-		128
130	void arch_post_mm_init(void)	129	void arch_post_mm_init(void)
131	{	130	{
132	if (config.cpu_active == 1) {	131	if (config.cpu_active == 1) {
133	/* Initialize IRQ routing */	132	/* Initialize IRQ routing */
134	irq_init(IRQ_COUNT, IRQ_COUNT);	133	irq_init(IRQ_COUNT, IRQ_COUNT);
135		134
136	/* hard clock */	135	/* hard clock */
137	i8254_init();	136	i8254_init();
138		137
139	#ifdef CONFIG_FB	138	#ifdef CONFIG_FB
140	if (vesa_present())	139	if (vesa_present())
141	vesa_init();	140	vesa_init();
142	else	141	else
143	#endif	142	#endif
144	ega_init(); /* video */	143	ega_init(); /* video */
145		144
146	/* Enable debugger */	145	/* Enable debugger */
147	debugger_init();	146	debugger_init();
148	/* Merge all memory zones to 1 big zone */	147	/* Merge all memory zones to 1 big zone */
149	zone_merge_all();	148	zone_merge_all();
150	}	149	}
-		150
151	/* Setup fast SYSCALL/SYSRET */	151	/* Setup fast SYSCALL/SYSRET */
152	syscall_setup_cpu();	152	syscall_setup_cpu();
153		-
154	}	153	}
155		154
156	void arch_post_cpu_init()	155	void arch_post_cpu_init()
157	{	156	{
158	#ifdef CONFIG_SMP	157	#ifdef CONFIG_SMP
159	if (config.cpu_active > 1) {	158	if (config.cpu_active > 1) {
160	l_apic_init();	159	l_apic_init();
161	l_apic_debug();	160	l_apic_debug();
162	}	161	}
163	#endif	162	#endif
164	}	163	}
165		164
166	void arch_pre_smp_init(void)	165	void arch_pre_smp_init(void)
167	{	166	{
168	if (config.cpu_active == 1) {	167	if (config.cpu_active == 1) {
169	memory_print_map();	168	memory_print_map();
170		169
171	#ifdef CONFIG_SMP	170	#ifdef CONFIG_SMP
172	acpi_init();	171	acpi_init();
173	#endif /* CONFIG_SMP */	172	#endif /* CONFIG_SMP */
174	}	173	}
175	}	174	}
176		175
177	void arch_post_smp_init(void)	176	void arch_post_smp_init(void)
178	{	177	{
179	/* keyboard controller */	178	/* keyboard controller */
180	i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);	179	i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);
181	}	180	}
182		181
183	void calibrate_delay_loop(void)	182	void calibrate_delay_loop(void)
184	{	183	{
185	i8254_calibrate_delay_loop();	184	i8254_calibrate_delay_loop();
186	if (config.cpu_active == 1) {	185	if (config.cpu_active == 1) {
187	/*	186	/*
188	* This has to be done only on UP.	187	* This has to be done only on UP.
189	* On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.	188	* On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
190	*/	189	*/
191	i8254_normal_operation();	190	i8254_normal_operation();
192	}	191	}
193	}	192	}
194		193
195	/** Set thread-local-storage pointer	194	/** Set thread-local-storage pointer
196	*	195	*
197	* TLS pointer is set in FS register. Unfortunately the 64-bit	196	* TLS pointer is set in FS register. Unfortunately the 64-bit
198	* part can be set only in CPL0 mode.	197	* part can be set only in CPL0 mode.
199	*	198	*
200	* The specs say, that on %fs:0 there is stored contents of %fs register,	199	* The specs say, that on %fs:0 there is stored contents of %fs register,
201	* we need not to go to CPL0 to read it.	200	* we need not to go to CPL0 to read it.
202	*/	201	*/
203	unative_t sys_tls_set(unative_t addr)	202	unative_t sys_tls_set(unative_t addr)
204	{	203	{
205	THREAD->arch.tls = addr;	204	THREAD->arch.tls = addr;
206	write_msr(AMD_MSR_FS, addr);	205	write_msr(AMD_MSR_FS, addr);
207	return 0;	206	return 0;
208	}	207	}
209		208
210	/** Acquire console back for kernel	209	/** Acquire console back for kernel
211	*	210	*
212	*/	211	*/
213	void arch_grab_console(void)	212	void arch_grab_console(void)
214	{	213	{
215	i8042_grab();	214	i8042_grab();
216	}	215	}
217	/** Return console to userspace	216	/** Return console to userspace
218	*	217	*
219	*/	218	*/
220	void arch_release_console(void)	219	void arch_release_console(void)
221	{	220	{
222	i8042_release();	221	i8042_release();
223	}	222	}
224		223
225	/** @}	224	/** @}
226	*/	225	*/
227		226

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/amd64/src/amd64.c – Rev 2692 → 2697