WebSVN – HelenOS – Diff – /trunk/kernel/arch/amd64/src/amd64.c


/*
 * Copyright (C) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64
 * @{
 */
/** @file
 */
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <proc/thread.h>
#include <arch/drivers/ega.h>
#include <arch/drivers/vesa.h>
#include <genarch/kbd/i8042.h>
#include <arch/drivers/i8254.h>
#include <arch/drivers/i8259.h>
 
#ifdef CONFIG_SMP
#include <arch/smp/apic.h>
#endif
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
#include <console/console.h>
 
 
/** Disable I/O on non-privileged levels
 *
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/** Disable alignment check
 *
 * Clean AM(18) flag in CR0 register
 */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void arch_pre_mm_init(void)
{
    struct cpu_info cpuid_s;
 
    cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
        panic("Processor does not support No-execute pages.\n");
 
    cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
        panic("Processor does not support FXSAVE/FXRESTORE.\n");
   
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
        panic("Processor does not support SSE2 instructions.\n");
 
    /* Enable No-execute pages */
    set_efer_flag(AMD_NXE_FLAG);
    /* Enable FPU */
    cpu_setup_fpu();
 
    /* Initialize segmentation */
    pm_init();
 
        /* Disable I/O on nonprivileged levels
     * clear the NT(nested-thread) flag
     */
    clean_IOPL_NT_flags();
    /* Disable alignment check */
    clean_AM_flag();
 
    if (config.cpu_active == 1) {
        bios_init();
        i8259_init();   /* PIC */
        i8254_init();   /* hard clock */
 
        #ifdef CONFIG_SMP
        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
                 tlb_shootdown_ipi);
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_mm_init(void)
{
    if (config.cpu_active == 1) {
#ifdef CONFIG_FB
        if (vesa_present())
            vesa_init();
        else
#endif
            ega_init(); /* video */
        /* Enable debugger */
        debugger_init();
        /* Merge all memory zones to 1 big zone */
        zone_merge_all();
    }
    /* Setup fast SYSCALL/SYSRET */
    syscall_setup_cpu();
   
}
 
void arch_post_cpu_init()
{
#ifdef CONFIG_SMP
    if (config.cpu_active > 1) {
        l_apic_init();
        l_apic_debug();
    }
#endif
}
 
void arch_pre_smp_init(void)
{
    if (config.cpu_active == 1) {
        memory_print_map();
       
        #ifdef CONFIG_SMP
        acpi_init();
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_smp_init(void)
{
    i8042_init();   /* keyboard controller */
}
 
void calibrate_delay_loop(void)
{
    i8254_calibrate_delay_loop();
    i8254_normal_operation();
}
 
/** Set thread-local-storage pointer
 *
 * TLS pointer is set in FS register. Unfortunately the 64-bit
 * part can be set only in CPL0 mode.
 *
 * The specs say, that on %fs:0 there is stored contents of %fs register,
 * we need not to go to CPL0 to read it.
 */
unative_t sys_tls_set(unative_t addr)
{
    THREAD->arch.tls = addr;
    write_msr(AMD_MSR_FS, addr);
    return 0;
}
 
/** Acquire console back for kernel
 *
 */
void arch_grab_console(void)
{
    i8042_grab();
}
/** Return console to userspace
 *
 */
void arch_release_console(void)
{
    i8042_release();
}
 
/** @}
 */
 

Rev 1842	Rev 1901
1	/*	1	/*
2	* Copyright (C) 2005 Ondrej Palkovsky	2	* Copyright (C) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup amd64	29	/** @addtogroup amd64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch.h>	35	#include <arch.h>
36		36
37	#include <arch/types.h>	37	#include <arch/types.h>
38		38
39	#include <config.h>	39	#include <config.h>
40		40
41	#include <proc/thread.h>	41	#include <proc/thread.h>
42	#include <arch/drivers/ega.h>	42	#include <arch/drivers/ega.h>
43	#include <arch/drivers/vesa.h>	43	#include <arch/drivers/vesa.h>
44	#include <genarch/kbd/i8042.h>	44	#include <genarch/kbd/i8042.h>
45	#include <arch/drivers/i8254.h>	45	#include <arch/drivers/i8254.h>
46	#include <arch/drivers/i8259.h>	46	#include <arch/drivers/i8259.h>
47		47
-		48	#ifdef CONFIG_SMP
-		49	#include <arch/smp/apic.h>
-		50	#endif
-		51
48	#include <arch/bios/bios.h>	52	#include <arch/bios/bios.h>
49	#include <arch/mm/memory_init.h>	53	#include <arch/mm/memory_init.h>
50	#include <arch/cpu.h>	54	#include <arch/cpu.h>
51	#include <print.h>	55	#include <print.h>
52	#include <arch/cpuid.h>	56	#include <arch/cpuid.h>
53	#include <genarch/acpi/acpi.h>	57	#include <genarch/acpi/acpi.h>
54	#include <panic.h>	58	#include <panic.h>
55	#include <interrupt.h>	59	#include <interrupt.h>
56	#include <arch/syscall.h>	60	#include <arch/syscall.h>
57	#include <arch/debugger.h>	61	#include <arch/debugger.h>
58	#include <syscall/syscall.h>	62	#include <syscall/syscall.h>
59	#include <console/console.h>	63	#include <console/console.h>
60		64
61		65
62	/** Disable I/O on non-privileged levels	66	/** Disable I/O on non-privileged levels
63	*	67	*
64	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register	68	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
65	*/	69	*/
66	static void clean_IOPL_NT_flags(void)	70	static void clean_IOPL_NT_flags(void)
67	{	71	{
68	asm	72	asm
69	(	73	(
70	"pushfq;"	74	"pushfq;"
71	"pop %%rax;"	75	"pop %%rax;"
72	"and $~(0x7000),%%rax;"	76	"and $~(0x7000),%%rax;"
73	"pushq %%rax;"	77	"pushq %%rax;"
74	"popfq;"	78	"popfq;"
75	:	79	:
76	:	80	:
77	:"%rax"	81	:"%rax"
78	);	82	);
79	}	83	}
80		84
81	/** Disable alignment check	85	/** Disable alignment check
82	*	86	*
83	* Clean AM(18) flag in CR0 register	87	* Clean AM(18) flag in CR0 register
84	*/	88	*/
85	static void clean_AM_flag(void)	89	static void clean_AM_flag(void)
86	{	90	{
87	asm	91	asm
88	(	92	(
89	"mov %%cr0,%%rax;"	93	"mov %%cr0,%%rax;"
90	"and $~(0x40000),%%rax;"	94	"and $~(0x40000),%%rax;"
91	"mov %%rax,%%cr0;"	95	"mov %%rax,%%cr0;"
92	:	96	:
93	:	97	:
94	:"%rax"	98	:"%rax"
95	);	99	);
96	}	100	}
97		101
98	void arch_pre_mm_init(void)	102	void arch_pre_mm_init(void)
99	{	103	{
100	struct cpu_info cpuid_s;	104	struct cpu_info cpuid_s;
101		105
102	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);	106	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
103	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))	107	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
104	panic("Processor does not support No-execute pages.\n");	108	panic("Processor does not support No-execute pages.\n");
105		109
106	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);	110	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
107	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))	111	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
108	panic("Processor does not support FXSAVE/FXRESTORE.\n");	112	panic("Processor does not support FXSAVE/FXRESTORE.\n");
109		113
110	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))	114	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
111	panic("Processor does not support SSE2 instructions.\n");	115	panic("Processor does not support SSE2 instructions.\n");
112		116
113	/* Enable No-execute pages */	117	/* Enable No-execute pages */
114	set_efer_flag(AMD_NXE_FLAG);	118	set_efer_flag(AMD_NXE_FLAG);
115	/* Enable FPU */	119	/* Enable FPU */
116	cpu_setup_fpu();	120	cpu_setup_fpu();
117		121
118	/* Initialize segmentation */	122	/* Initialize segmentation */
119	pm_init();	123	pm_init();
120		124
121	/* Disable I/O on nonprivileged levels	125	/* Disable I/O on nonprivileged levels
122	* clear the NT(nested-thread) flag	126	* clear the NT(nested-thread) flag
123	*/	127	*/
124	clean_IOPL_NT_flags();	128	clean_IOPL_NT_flags();
125	/* Disable alignment check */	129	/* Disable alignment check */
126	clean_AM_flag();	130	clean_AM_flag();
127		131
128	if (config.cpu_active == 1) {	132	if (config.cpu_active == 1) {
129	bios_init();	133	bios_init();
130	i8259_init(); /* PIC */	134	i8259_init(); /* PIC */
131	i8254_init(); /* hard clock */	135	i8254_init(); /* hard clock */
132		136
133	#ifdef CONFIG_SMP	137	#ifdef CONFIG_SMP
134	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",	138	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
135	tlb_shootdown_ipi);	139	tlb_shootdown_ipi);
136	#endif /* CONFIG_SMP */	140	#endif /* CONFIG_SMP */
137	}	141	}
138	}	142	}
139		143
140	void arch_post_mm_init(void)	144	void arch_post_mm_init(void)
141	{	145	{
142	if (config.cpu_active == 1) {	146	if (config.cpu_active == 1) {
143	#ifdef CONFIG_FB	147	#ifdef CONFIG_FB
144	if (vesa_present())	148	if (vesa_present())
145	vesa_init();	149	vesa_init();
146	else	150	else
147	#endif	151	#endif
148	ega_init(); /* video */	152	ega_init(); /* video */
149	/* Enable debugger */	153	/* Enable debugger */
150	debugger_init();	154	debugger_init();
151	/* Merge all memory zones to 1 big zone */	155	/* Merge all memory zones to 1 big zone */
152	zone_merge_all();	156	zone_merge_all();
153	}	157	}
154	/* Setup fast SYSCALL/SYSRET */	158	/* Setup fast SYSCALL/SYSRET */
155	syscall_setup_cpu();	159	syscall_setup_cpu();
156		160
157	}	161	}
-		162
-		163	void arch_post_cpu_init()
-		164	{
-		165	#ifdef CONFIG_SMP
-		166	if (config.cpu_active > 1) {
-		167	l_apic_init();
-		168	l_apic_debug();
-		169	}
-		170	#endif
-		171	}
158		172
159	void arch_pre_smp_init(void)	173	void arch_pre_smp_init(void)
160	{	174	{
161	if (config.cpu_active == 1) {	175	if (config.cpu_active == 1) {
162	memory_print_map();	176	memory_print_map();
163		177
164	#ifdef CONFIG_SMP	178	#ifdef CONFIG_SMP
165	acpi_init();	179	acpi_init();
166	#endif /* CONFIG_SMP */	180	#endif /* CONFIG_SMP */
167	}	181	}
168	}	182	}
169		183
170	void arch_post_smp_init(void)	184	void arch_post_smp_init(void)
171	{	185	{
172	i8042_init(); /* keyboard controller */	186	i8042_init(); /* keyboard controller */
173	}	187	}
174		188
175	void calibrate_delay_loop(void)	189	void calibrate_delay_loop(void)
176	{	190	{
177	i8254_calibrate_delay_loop();	191	i8254_calibrate_delay_loop();
178	i8254_normal_operation();	192	i8254_normal_operation();
179	}	193	}
180		194
181	/** Set thread-local-storage pointer	195	/** Set thread-local-storage pointer
182	*	196	*
183	* TLS pointer is set in FS register. Unfortunately the 64-bit	197	* TLS pointer is set in FS register. Unfortunately the 64-bit
184	* part can be set only in CPL0 mode.	198	* part can be set only in CPL0 mode.
185	*	199	*
186	* The specs say, that on %fs:0 there is stored contents of %fs register,	200	* The specs say, that on %fs:0 there is stored contents of %fs register,
187	* we need not to go to CPL0 to read it.	201	* we need not to go to CPL0 to read it.
188	*/	202	*/
189	unative_t sys_tls_set(unative_t addr)	203	unative_t sys_tls_set(unative_t addr)
190	{	204	{
191	THREAD->arch.tls = addr;	205	THREAD->arch.tls = addr;
192	write_msr(AMD_MSR_FS, addr);	206	write_msr(AMD_MSR_FS, addr);
193	return 0;	207	return 0;
194	}	208	}
195		209
196	/** Acquire console back for kernel	210	/** Acquire console back for kernel
197	*	211	*
198	*/	212	*/
199	void arch_grab_console(void)	213	void arch_grab_console(void)
200	{	214	{
201	i8042_grab();	215	i8042_grab();
202	}	216	}
203	/** Return console to userspace	217	/** Return console to userspace
204	*	218	*
205	*/	219	*/
206	void arch_release_console(void)	220	void arch_release_console(void)
207	{	221	{
208	i8042_release();	222	i8042_release();
209	}	223	}
210		224
211	/** @}	225	/** @}
212	*/	226	*/
213		227

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/amd64/src/amd64.c – Rev 1842 → 1901