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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __amd64_ASM_H__ |
29 | #ifndef __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | 34 | ||
35 | 35 | ||
36 | void asm_delay_loop(__u32 t); |
36 | void asm_delay_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
38 | 38 | ||
39 | /* TODO: implement the real stuff */ |
- | |
40 | static inline __address get_stack_base(void) |
39 | static inline __address get_stack_base(void) |
41 | { |
40 | { |
- | 41 | __address v; |
|
- | 42 | ||
- | 43 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
|
- | 44 | ||
42 | return NULL; |
45 | return v; |
43 | } |
46 | } |
44 | 47 | ||
45 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
48 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
46 | static inline void cpu_halt(void) { __asm__("hlt"); }; |
49 | static inline void cpu_halt(void) { __asm__("hlt"); }; |
47 | 50 | ||
48 | 51 | ||
49 | static inline __u8 inb(__u16 port) |
52 | static inline __u8 inb(__u16 port) |
50 | { |
53 | { |
51 | __u8 out; |
54 | __u8 out; |
52 | 55 | ||
53 | asm ( |
56 | asm ( |
54 | "mov %0, %%dx;" |
57 | "mov %1, %%dx;" |
55 | "inb %%dx,%%al;" |
58 | "inb %%dx,%%al;" |
56 | "mov %%al, %1;" |
59 | "mov %%al, %0;" |
57 | :"=m"(out) |
60 | :"=m"(out) |
58 | :"m"(port) |
61 | :"m"(port) |
59 | :"%dx","%al" |
62 | :"%dx","%al" |
60 | ); |
63 | ); |
61 | return out; |
64 | return out; |
62 | } |
65 | } |
63 | 66 | ||
64 | static inline __u8 outb(__u16 port,__u8 b) |
67 | static inline __u8 outb(__u16 port,__u8 b) |
65 | { |
68 | { |
66 | asm ( |
69 | asm ( |
67 | "mov %0,%%dx;" |
70 | "mov %0,%%dx;" |
68 | "mov %1,%%al;" |
71 | "mov %1,%%al;" |
69 | "outb %%al,%%dx;" |
72 | "outb %%al,%%dx;" |
70 | : |
73 | : |
71 | :"m"( port), "m" (b) |
74 | :"m"( port), "m" (b) |
72 | :"%dx","%al" |
75 | :"%dx","%al" |
73 | ); |
76 | ); |
74 | } |
77 | } |
75 | 78 | ||
76 | /** Set priority level low |
79 | /** Set priority level low |
77 | * |
80 | * |
78 | * Enable interrupts and return previous |
81 | * Enable interrupts and return previous |
79 | * value of EFLAGS. |
82 | * value of EFLAGS. |
80 | */ |
83 | */ |
81 | static inline pri_t cpu_priority_low(void) { |
84 | static inline pri_t cpu_priority_low(void) { |
82 | pri_t v; |
85 | pri_t v; |
83 | __asm__ volatile ( |
86 | __asm__ volatile ( |
84 | "pushfq\n" |
87 | "pushfq\n" |
85 | "popq %0\n" |
88 | "popq %0\n" |
86 | "sti\n" |
89 | "sti\n" |
87 | : "=r" (v) |
90 | : "=r" (v) |
88 | ); |
91 | ); |
89 | return v; |
92 | return v; |
90 | } |
93 | } |
91 | 94 | ||
92 | /** Set priority level high |
95 | /** Set priority level high |
93 | * |
96 | * |
94 | * Disable interrupts and return previous |
97 | * Disable interrupts and return previous |
95 | * value of EFLAGS. |
98 | * value of EFLAGS. |
96 | */ |
99 | */ |
97 | static inline pri_t cpu_priority_high(void) { |
100 | static inline pri_t cpu_priority_high(void) { |
98 | pri_t v; |
101 | pri_t v; |
99 | __asm__ volatile ( |
102 | __asm__ volatile ( |
100 | "pushfq\n" |
103 | "pushfq\n" |
101 | "popq %0\n" |
104 | "popq %0\n" |
102 | "cli\n" |
105 | "cli\n" |
103 | : "=r" (v) |
106 | : "=r" (v) |
104 | ); |
107 | ); |
105 | return v; |
108 | return v; |
106 | } |
109 | } |
107 | 110 | ||
108 | /** Restore priority level |
111 | /** Restore priority level |
109 | * |
112 | * |
110 | * Restore EFLAGS. |
113 | * Restore EFLAGS. |
111 | */ |
114 | */ |
112 | static inline void cpu_priority_restore(pri_t pri) { |
115 | static inline void cpu_priority_restore(pri_t pri) { |
113 | __asm__ volatile ( |
116 | __asm__ volatile ( |
114 | "pushq %0\n" |
117 | "pushq %0\n" |
115 | "popfq\n" |
118 | "popfq\n" |
116 | : : "r" (pri) |
119 | : : "r" (pri) |
117 | ); |
120 | ); |
118 | } |
121 | } |
119 | 122 | ||
120 | /** Return raw priority level |
123 | /** Return raw priority level |
121 | * |
124 | * |
122 | * Return EFLAFS. |
125 | * Return EFLAFS. |
123 | */ |
126 | */ |
124 | static inline pri_t cpu_priority_read(void) { |
127 | static inline pri_t cpu_priority_read(void) { |
125 | pri_t v; |
128 | pri_t v; |
126 | __asm__ volatile ( |
129 | __asm__ volatile ( |
127 | "pushfq\n" |
130 | "pushfq\n" |
128 | "popq %0\n" |
131 | "popq %0\n" |
129 | : "=r" (v) |
132 | : "=r" (v) |
130 | ); |
133 | ); |
131 | return v; |
134 | return v; |
132 | } |
135 | } |
133 | 136 | ||
134 | /** Read CR2 |
137 | /** Read CR2 |
135 | * |
138 | * |
136 | * Return value in CR2 |
139 | * Return value in CR2 |
137 | * |
140 | * |
138 | * @return Value read. |
141 | * @return Value read. |
139 | */ |
142 | */ |
140 | static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
143 | static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
141 | 144 | ||
142 | /** Write CR3 |
145 | /** Write CR3 |
143 | * |
146 | * |
144 | * Write value to CR3. |
147 | * Write value to CR3. |
145 | * |
148 | * |
146 | * @param v Value to be written. |
149 | * @param v Value to be written. |
147 | */ |
150 | */ |
148 | static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); } |
151 | static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); } |
149 | 152 | ||
150 | /** Read CR3 |
153 | /** Read CR3 |
151 | * |
154 | * |
152 | * Return value in CR3 |
155 | * Return value in CR3 |
153 | * |
156 | * |
154 | * @return Value read. |
157 | * @return Value read. |
155 | */ |
158 | */ |
156 | static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } |
159 | static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } |
157 | 160 | ||
158 | 161 | ||
159 | extern size_t interrupt_handler_size; |
162 | extern size_t interrupt_handler_size; |
160 | extern void interrupt_handlers(void); |
163 | extern void interrupt_handlers(void); |
161 | 164 | ||
162 | #endif |
165 | #endif |
163 | 166 |