Rev 2082 | Rev 2233 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2082 | Rev 2089 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64 |
29 | /** @addtogroup amd64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_amd64_ASM_H_ |
35 | #ifndef KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
37 | 37 | ||
38 | #include <arch/pm.h> |
- | |
39 | #include <arch/types.h> |
- | |
40 | #include <config.h> |
38 | #include <config.h> |
41 | 39 | ||
42 | extern void asm_delay_loop(uint32_t t); |
40 | extern void asm_delay_loop(uint32_t t); |
43 | extern void asm_fake_loop(uint32_t t); |
41 | extern void asm_fake_loop(uint32_t t); |
44 | 42 | ||
45 | /** Return base address of current stack. |
43 | /** Return base address of current stack. |
46 | * |
44 | * |
47 | * Return the base address of the current stack. |
45 | * Return the base address of the current stack. |
48 | * The stack is assumed to be STACK_SIZE bytes long. |
46 | * The stack is assumed to be STACK_SIZE bytes long. |
49 | * The stack must start on page boundary. |
47 | * The stack must start on page boundary. |
50 | */ |
48 | */ |
51 | static inline uintptr_t get_stack_base(void) |
49 | static inline uintptr_t get_stack_base(void) |
52 | { |
50 | { |
53 | uintptr_t v; |
51 | uintptr_t v; |
54 | 52 | ||
55 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
53 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
56 | 54 | ||
57 | return v; |
55 | return v; |
58 | } |
56 | } |
59 | 57 | ||
60 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
58 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
61 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
59 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
62 | 60 | ||
63 | 61 | ||
64 | /** Byte from port |
62 | /** Byte from port |
65 | * |
63 | * |
66 | * Get byte from port |
64 | * Get byte from port |
67 | * |
65 | * |
68 | * @param port Port to read from |
66 | * @param port Port to read from |
69 | * @return Value read |
67 | * @return Value read |
70 | */ |
68 | */ |
71 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
69 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
72 | 70 | ||
73 | /** Byte to port |
71 | /** Byte to port |
74 | * |
72 | * |
75 | * Output byte to port |
73 | * Output byte to port |
76 | * |
74 | * |
77 | * @param port Port to write to |
75 | * @param port Port to write to |
78 | * @param val Value to write |
76 | * @param val Value to write |
79 | */ |
77 | */ |
80 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
78 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
81 | 79 | ||
82 | /** Swap Hidden part of GS register with visible one */ |
80 | /** Swap Hidden part of GS register with visible one */ |
83 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
81 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
84 | 82 | ||
85 | /** Enable interrupts. |
83 | /** Enable interrupts. |
86 | * |
84 | * |
87 | * Enable interrupts and return previous |
85 | * Enable interrupts and return previous |
88 | * value of EFLAGS. |
86 | * value of EFLAGS. |
89 | * |
87 | * |
90 | * @return Old interrupt priority level. |
88 | * @return Old interrupt priority level. |
91 | */ |
89 | */ |
92 | static inline ipl_t interrupts_enable(void) { |
90 | static inline ipl_t interrupts_enable(void) { |
93 | ipl_t v; |
91 | ipl_t v; |
94 | __asm__ volatile ( |
92 | __asm__ volatile ( |
95 | "pushfq\n" |
93 | "pushfq\n" |
96 | "popq %0\n" |
94 | "popq %0\n" |
97 | "sti\n" |
95 | "sti\n" |
98 | : "=r" (v) |
96 | : "=r" (v) |
99 | ); |
97 | ); |
100 | return v; |
98 | return v; |
101 | } |
99 | } |
102 | 100 | ||
103 | /** Disable interrupts. |
101 | /** Disable interrupts. |
104 | * |
102 | * |
105 | * Disable interrupts and return previous |
103 | * Disable interrupts and return previous |
106 | * value of EFLAGS. |
104 | * value of EFLAGS. |
107 | * |
105 | * |
108 | * @return Old interrupt priority level. |
106 | * @return Old interrupt priority level. |
109 | */ |
107 | */ |
110 | static inline ipl_t interrupts_disable(void) { |
108 | static inline ipl_t interrupts_disable(void) { |
111 | ipl_t v; |
109 | ipl_t v; |
112 | __asm__ volatile ( |
110 | __asm__ volatile ( |
113 | "pushfq\n" |
111 | "pushfq\n" |
114 | "popq %0\n" |
112 | "popq %0\n" |
115 | "cli\n" |
113 | "cli\n" |
116 | : "=r" (v) |
114 | : "=r" (v) |
117 | ); |
115 | ); |
118 | return v; |
116 | return v; |
119 | } |
117 | } |
120 | 118 | ||
121 | /** Restore interrupt priority level. |
119 | /** Restore interrupt priority level. |
122 | * |
120 | * |
123 | * Restore EFLAGS. |
121 | * Restore EFLAGS. |
124 | * |
122 | * |
125 | * @param ipl Saved interrupt priority level. |
123 | * @param ipl Saved interrupt priority level. |
126 | */ |
124 | */ |
127 | static inline void interrupts_restore(ipl_t ipl) { |
125 | static inline void interrupts_restore(ipl_t ipl) { |
128 | __asm__ volatile ( |
126 | __asm__ volatile ( |
129 | "pushq %0\n" |
127 | "pushq %0\n" |
130 | "popfq\n" |
128 | "popfq\n" |
131 | : : "r" (ipl) |
129 | : : "r" (ipl) |
132 | ); |
130 | ); |
133 | } |
131 | } |
134 | 132 | ||
135 | /** Return interrupt priority level. |
133 | /** Return interrupt priority level. |
136 | * |
134 | * |
137 | * Return EFLAFS. |
135 | * Return EFLAFS. |
138 | * |
136 | * |
139 | * @return Current interrupt priority level. |
137 | * @return Current interrupt priority level. |
140 | */ |
138 | */ |
141 | static inline ipl_t interrupts_read(void) { |
139 | static inline ipl_t interrupts_read(void) { |
142 | ipl_t v; |
140 | ipl_t v; |
143 | __asm__ volatile ( |
141 | __asm__ volatile ( |
144 | "pushfq\n" |
142 | "pushfq\n" |
145 | "popq %0\n" |
143 | "popq %0\n" |
146 | : "=r" (v) |
144 | : "=r" (v) |
147 | ); |
145 | ); |
148 | return v; |
146 | return v; |
149 | } |
147 | } |
150 | 148 | ||
151 | /** Write to MSR */ |
149 | /** Write to MSR */ |
152 | static inline void write_msr(uint32_t msr, uint64_t value) |
150 | static inline void write_msr(uint32_t msr, uint64_t value) |
153 | { |
151 | { |
154 | __asm__ volatile ( |
152 | __asm__ volatile ( |
155 | "wrmsr;" : : "c" (msr), |
153 | "wrmsr;" : : "c" (msr), |
156 | "a" ((uint32_t)(value)), |
154 | "a" ((uint32_t)(value)), |
157 | "d" ((uint32_t)(value >> 32)) |
155 | "d" ((uint32_t)(value >> 32)) |
158 | ); |
156 | ); |
159 | } |
157 | } |
160 | 158 | ||
161 | static inline unative_t read_msr(uint32_t msr) |
159 | static inline unative_t read_msr(uint32_t msr) |
162 | { |
160 | { |
163 | uint32_t ax, dx; |
161 | uint32_t ax, dx; |
164 | 162 | ||
165 | __asm__ volatile ( |
163 | __asm__ volatile ( |
166 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
164 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
167 | ); |
165 | ); |
168 | return ((uint64_t)dx << 32) | ax; |
166 | return ((uint64_t)dx << 32) | ax; |
169 | } |
167 | } |
170 | 168 | ||
171 | 169 | ||
172 | /** Enable local APIC |
170 | /** Enable local APIC |
173 | * |
171 | * |
174 | * Enable local APIC in MSR. |
172 | * Enable local APIC in MSR. |
175 | */ |
173 | */ |
176 | static inline void enable_l_apic_in_msr() |
174 | static inline void enable_l_apic_in_msr() |
177 | { |
175 | { |
178 | __asm__ volatile ( |
176 | __asm__ volatile ( |
179 | "movl $0x1b, %%ecx\n" |
177 | "movl $0x1b, %%ecx\n" |
180 | "rdmsr\n" |
178 | "rdmsr\n" |
181 | "orl $(1<<11),%%eax\n" |
179 | "orl $(1<<11),%%eax\n" |
182 | "orl $(0xfee00000),%%eax\n" |
180 | "orl $(0xfee00000),%%eax\n" |
183 | "wrmsr\n" |
181 | "wrmsr\n" |
184 | : |
182 | : |
185 | : |
183 | : |
186 | :"%eax","%ecx","%edx" |
184 | :"%eax","%ecx","%edx" |
187 | ); |
185 | ); |
188 | } |
186 | } |
189 | 187 | ||
190 | static inline uintptr_t * get_ip() |
188 | static inline uintptr_t * get_ip() |
191 | { |
189 | { |
192 | uintptr_t *ip; |
190 | uintptr_t *ip; |
193 | 191 | ||
194 | __asm__ volatile ( |
192 | __asm__ volatile ( |
195 | "mov %%rip, %0" |
193 | "mov %%rip, %0" |
196 | : "=r" (ip) |
194 | : "=r" (ip) |
197 | ); |
195 | ); |
198 | return ip; |
196 | return ip; |
199 | } |
197 | } |
200 | 198 | ||
201 | /** Invalidate TLB Entry. |
199 | /** Invalidate TLB Entry. |
202 | * |
200 | * |
203 | * @param addr Address on a page whose TLB entry is to be invalidated. |
201 | * @param addr Address on a page whose TLB entry is to be invalidated. |
204 | */ |
202 | */ |
205 | static inline void invlpg(uintptr_t addr) |
203 | static inline void invlpg(uintptr_t addr) |
206 | { |
204 | { |
207 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
205 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
208 | } |
206 | } |
209 | 207 | ||
210 | /** Load GDTR register from memory. |
208 | /** Load GDTR register from memory. |
211 | * |
209 | * |
212 | * @param gdtr_reg Address of memory from where to load GDTR. |
210 | * @param gdtr_reg Address of memory from where to load GDTR. |
213 | */ |
211 | */ |
214 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
212 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
215 | { |
213 | { |
216 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
214 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
217 | } |
215 | } |
218 | 216 | ||
219 | /** Store GDTR register to memory. |
217 | /** Store GDTR register to memory. |
220 | * |
218 | * |
221 | * @param gdtr_reg Address of memory to where to load GDTR. |
219 | * @param gdtr_reg Address of memory to where to load GDTR. |
222 | */ |
220 | */ |
223 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
221 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
224 | { |
222 | { |
225 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
223 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
226 | } |
224 | } |
227 | 225 | ||
228 | /** Load IDTR register from memory. |
226 | /** Load IDTR register from memory. |
229 | * |
227 | * |
230 | * @param idtr_reg Address of memory from where to load IDTR. |
228 | * @param idtr_reg Address of memory from where to load IDTR. |
231 | */ |
229 | */ |
232 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
230 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
233 | { |
231 | { |
234 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
232 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
235 | } |
233 | } |
236 | 234 | ||
237 | /** Load TR from descriptor table. |
235 | /** Load TR from descriptor table. |
238 | * |
236 | * |
239 | * @param sel Selector specifying descriptor of TSS segment. |
237 | * @param sel Selector specifying descriptor of TSS segment. |
240 | */ |
238 | */ |
241 | static inline void tr_load(uint16_t sel) |
239 | static inline void tr_load(uint16_t sel) |
242 | { |
240 | { |
243 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
241 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
244 | } |
242 | } |
245 | 243 | ||
246 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
244 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
247 | { \ |
245 | { \ |
248 | unative_t res; \ |
246 | unative_t res; \ |
249 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
247 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
250 | return res; \ |
248 | return res; \ |
251 | } |
249 | } |
252 | 250 | ||
253 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
251 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
254 | { \ |
252 | { \ |
255 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
253 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
256 | } |
254 | } |
257 | 255 | ||
258 | GEN_READ_REG(cr0); |
256 | GEN_READ_REG(cr0); |
259 | GEN_READ_REG(cr2); |
257 | GEN_READ_REG(cr2); |
260 | GEN_READ_REG(cr3); |
258 | GEN_READ_REG(cr3); |
261 | GEN_WRITE_REG(cr3); |
259 | GEN_WRITE_REG(cr3); |
262 | 260 | ||
263 | GEN_READ_REG(dr0); |
261 | GEN_READ_REG(dr0); |
264 | GEN_READ_REG(dr1); |
262 | GEN_READ_REG(dr1); |
265 | GEN_READ_REG(dr2); |
263 | GEN_READ_REG(dr2); |
266 | GEN_READ_REG(dr3); |
264 | GEN_READ_REG(dr3); |
267 | GEN_READ_REG(dr6); |
265 | GEN_READ_REG(dr6); |
268 | GEN_READ_REG(dr7); |
266 | GEN_READ_REG(dr7); |
269 | 267 | ||
270 | GEN_WRITE_REG(dr0); |
268 | GEN_WRITE_REG(dr0); |
271 | GEN_WRITE_REG(dr1); |
269 | GEN_WRITE_REG(dr1); |
272 | GEN_WRITE_REG(dr2); |
270 | GEN_WRITE_REG(dr2); |
273 | GEN_WRITE_REG(dr3); |
271 | GEN_WRITE_REG(dr3); |
274 | GEN_WRITE_REG(dr6); |
272 | GEN_WRITE_REG(dr6); |
275 | GEN_WRITE_REG(dr7); |
273 | GEN_WRITE_REG(dr7); |
276 | 274 | ||
277 | extern size_t interrupt_handler_size; |
275 | extern size_t interrupt_handler_size; |
278 | extern void interrupt_handlers(void); |
276 | extern void interrupt_handlers(void); |
279 | 277 | ||
280 | #endif |
278 | #endif |
281 | 279 | ||
282 | /** @} |
280 | /** @} |
283 | */ |
281 | */ |
284 | 282 |