Rev 2452 | Rev 3902 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2452 | Rev 2453 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64 |
29 | /** @addtogroup amd64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_amd64_ASM_H_ |
35 | #ifndef KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
37 | 37 | ||
38 | #include <config.h> |
38 | #include <config.h> |
39 | 39 | ||
40 | extern void asm_delay_loop(uint32_t t); |
40 | extern void asm_delay_loop(uint32_t t); |
41 | extern void asm_fake_loop(uint32_t t); |
41 | extern void asm_fake_loop(uint32_t t); |
42 | 42 | ||
43 | /** Return base address of current stack. |
43 | /** Return base address of current stack. |
44 | * |
44 | * |
45 | * Return the base address of the current stack. |
45 | * Return the base address of the current stack. |
46 | * The stack is assumed to be STACK_SIZE bytes long. |
46 | * The stack is assumed to be STACK_SIZE bytes long. |
47 | * The stack must start on page boundary. |
47 | * The stack must start on page boundary. |
48 | */ |
48 | */ |
49 | static inline uintptr_t get_stack_base(void) |
49 | static inline uintptr_t get_stack_base(void) |
50 | { |
50 | { |
51 | uintptr_t v; |
51 | uintptr_t v; |
52 | 52 | ||
53 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
53 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
54 | 54 | ||
55 | return v; |
55 | return v; |
56 | } |
56 | } |
57 | 57 | ||
58 | static inline void cpu_sleep(void) |
58 | static inline void cpu_sleep(void) |
59 | { |
59 | { |
60 | asm volatile ("hlt\n"); |
60 | asm volatile ("hlt\n"); |
61 | }; |
61 | } |
62 | 62 | ||
63 | static inline void cpu_halt(void) |
63 | static inline void cpu_halt(void) |
64 | { |
64 | { |
65 | asm volatile ("hlt\n"); |
65 | asm volatile ("hlt\n"); |
66 | }; |
66 | } |
67 | 67 | ||
68 | 68 | ||
69 | /** Byte from port |
69 | /** Byte from port |
70 | * |
70 | * |
71 | * Get byte from port |
71 | * Get byte from port |
72 | * |
72 | * |
73 | * @param port Port to read from |
73 | * @param port Port to read from |
74 | * @return Value read |
74 | * @return Value read |
75 | */ |
75 | */ |
- | 76 | static inline uint8_t inb(uint16_t port) |
|
- | 77 | { |
|
- | 78 | uint8_t val; |
|
- | 79 | ||
76 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
80 | asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port)); |
- | 81 | return val; |
|
- | 82 | } |
|
77 | 83 | ||
78 | /** Byte to port |
84 | /** Byte to port |
79 | * |
85 | * |
80 | * Output byte to port |
86 | * Output byte to port |
81 | * |
87 | * |
82 | * @param port Port to write to |
88 | * @param port Port to write to |
83 | * @param val Value to write |
89 | * @param val Value to write |
84 | */ |
90 | */ |
- | 91 | static inline void outb(uint16_t port, uint8_t val) |
|
- | 92 | { |
|
85 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
93 | asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); |
- | 94 | } |
|
86 | 95 | ||
87 | /** Swap Hidden part of GS register with visible one */ |
96 | /** Swap Hidden part of GS register with visible one */ |
88 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
97 | static inline void swapgs(void) |
- | 98 | { |
|
- | 99 | asm volatile("swapgs"); |
|
- | 100 | } |
|
89 | 101 | ||
90 | /** Enable interrupts. |
102 | /** Enable interrupts. |
91 | * |
103 | * |
92 | * Enable interrupts and return previous |
104 | * Enable interrupts and return previous |
93 | * value of EFLAGS. |
105 | * value of EFLAGS. |
94 | * |
106 | * |
95 | * @return Old interrupt priority level. |
107 | * @return Old interrupt priority level. |
96 | */ |
108 | */ |
97 | static inline ipl_t interrupts_enable(void) { |
109 | static inline ipl_t interrupts_enable(void) { |
98 | ipl_t v; |
110 | ipl_t v; |
99 | __asm__ volatile ( |
111 | __asm__ volatile ( |
100 | "pushfq\n" |
112 | "pushfq\n" |
101 | "popq %0\n" |
113 | "popq %0\n" |
102 | "sti\n" |
114 | "sti\n" |
103 | : "=r" (v) |
115 | : "=r" (v) |
104 | ); |
116 | ); |
105 | return v; |
117 | return v; |
106 | } |
118 | } |
107 | 119 | ||
108 | /** Disable interrupts. |
120 | /** Disable interrupts. |
109 | * |
121 | * |
110 | * Disable interrupts and return previous |
122 | * Disable interrupts and return previous |
111 | * value of EFLAGS. |
123 | * value of EFLAGS. |
112 | * |
124 | * |
113 | * @return Old interrupt priority level. |
125 | * @return Old interrupt priority level. |
114 | */ |
126 | */ |
115 | static inline ipl_t interrupts_disable(void) { |
127 | static inline ipl_t interrupts_disable(void) { |
116 | ipl_t v; |
128 | ipl_t v; |
117 | __asm__ volatile ( |
129 | __asm__ volatile ( |
118 | "pushfq\n" |
130 | "pushfq\n" |
119 | "popq %0\n" |
131 | "popq %0\n" |
120 | "cli\n" |
132 | "cli\n" |
121 | : "=r" (v) |
133 | : "=r" (v) |
122 | ); |
134 | ); |
123 | return v; |
135 | return v; |
124 | } |
136 | } |
125 | 137 | ||
126 | /** Restore interrupt priority level. |
138 | /** Restore interrupt priority level. |
127 | * |
139 | * |
128 | * Restore EFLAGS. |
140 | * Restore EFLAGS. |
129 | * |
141 | * |
130 | * @param ipl Saved interrupt priority level. |
142 | * @param ipl Saved interrupt priority level. |
131 | */ |
143 | */ |
132 | static inline void interrupts_restore(ipl_t ipl) { |
144 | static inline void interrupts_restore(ipl_t ipl) { |
133 | __asm__ volatile ( |
145 | __asm__ volatile ( |
134 | "pushq %0\n" |
146 | "pushq %0\n" |
135 | "popfq\n" |
147 | "popfq\n" |
136 | : : "r" (ipl) |
148 | : : "r" (ipl) |
137 | ); |
149 | ); |
138 | } |
150 | } |
139 | 151 | ||
140 | /** Return interrupt priority level. |
152 | /** Return interrupt priority level. |
141 | * |
153 | * |
142 | * Return EFLAFS. |
154 | * Return EFLAFS. |
143 | * |
155 | * |
144 | * @return Current interrupt priority level. |
156 | * @return Current interrupt priority level. |
145 | */ |
157 | */ |
146 | static inline ipl_t interrupts_read(void) { |
158 | static inline ipl_t interrupts_read(void) { |
147 | ipl_t v; |
159 | ipl_t v; |
148 | __asm__ volatile ( |
160 | __asm__ volatile ( |
149 | "pushfq\n" |
161 | "pushfq\n" |
150 | "popq %0\n" |
162 | "popq %0\n" |
151 | : "=r" (v) |
163 | : "=r" (v) |
152 | ); |
164 | ); |
153 | return v; |
165 | return v; |
154 | } |
166 | } |
155 | 167 | ||
156 | /** Write to MSR */ |
168 | /** Write to MSR */ |
157 | static inline void write_msr(uint32_t msr, uint64_t value) |
169 | static inline void write_msr(uint32_t msr, uint64_t value) |
158 | { |
170 | { |
159 | __asm__ volatile ( |
171 | __asm__ volatile ( |
160 | "wrmsr;" : : "c" (msr), |
172 | "wrmsr;" : : "c" (msr), |
161 | "a" ((uint32_t)(value)), |
173 | "a" ((uint32_t)(value)), |
162 | "d" ((uint32_t)(value >> 32)) |
174 | "d" ((uint32_t)(value >> 32)) |
163 | ); |
175 | ); |
164 | } |
176 | } |
165 | 177 | ||
166 | static inline unative_t read_msr(uint32_t msr) |
178 | static inline unative_t read_msr(uint32_t msr) |
167 | { |
179 | { |
168 | uint32_t ax, dx; |
180 | uint32_t ax, dx; |
169 | 181 | ||
170 | __asm__ volatile ( |
182 | __asm__ volatile ( |
171 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
183 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
172 | ); |
184 | ); |
173 | return ((uint64_t)dx << 32) | ax; |
185 | return ((uint64_t)dx << 32) | ax; |
174 | } |
186 | } |
175 | 187 | ||
176 | 188 | ||
177 | /** Enable local APIC |
189 | /** Enable local APIC |
178 | * |
190 | * |
179 | * Enable local APIC in MSR. |
191 | * Enable local APIC in MSR. |
180 | */ |
192 | */ |
181 | static inline void enable_l_apic_in_msr() |
193 | static inline void enable_l_apic_in_msr() |
182 | { |
194 | { |
183 | __asm__ volatile ( |
195 | __asm__ volatile ( |
184 | "movl $0x1b, %%ecx\n" |
196 | "movl $0x1b, %%ecx\n" |
185 | "rdmsr\n" |
197 | "rdmsr\n" |
186 | "orl $(1<<11),%%eax\n" |
198 | "orl $(1<<11),%%eax\n" |
187 | "orl $(0xfee00000),%%eax\n" |
199 | "orl $(0xfee00000),%%eax\n" |
188 | "wrmsr\n" |
200 | "wrmsr\n" |
189 | : |
201 | : |
190 | : |
202 | : |
191 | :"%eax","%ecx","%edx" |
203 | :"%eax","%ecx","%edx" |
192 | ); |
204 | ); |
193 | } |
205 | } |
194 | 206 | ||
195 | static inline uintptr_t * get_ip() |
207 | static inline uintptr_t * get_ip() |
196 | { |
208 | { |
197 | uintptr_t *ip; |
209 | uintptr_t *ip; |
198 | 210 | ||
199 | __asm__ volatile ( |
211 | __asm__ volatile ( |
200 | "mov %%rip, %0" |
212 | "mov %%rip, %0" |
201 | : "=r" (ip) |
213 | : "=r" (ip) |
202 | ); |
214 | ); |
203 | return ip; |
215 | return ip; |
204 | } |
216 | } |
205 | 217 | ||
206 | /** Invalidate TLB Entry. |
218 | /** Invalidate TLB Entry. |
207 | * |
219 | * |
208 | * @param addr Address on a page whose TLB entry is to be invalidated. |
220 | * @param addr Address on a page whose TLB entry is to be invalidated. |
209 | */ |
221 | */ |
210 | static inline void invlpg(uintptr_t addr) |
222 | static inline void invlpg(uintptr_t addr) |
211 | { |
223 | { |
212 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
224 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
213 | } |
225 | } |
214 | 226 | ||
215 | /** Load GDTR register from memory. |
227 | /** Load GDTR register from memory. |
216 | * |
228 | * |
217 | * @param gdtr_reg Address of memory from where to load GDTR. |
229 | * @param gdtr_reg Address of memory from where to load GDTR. |
218 | */ |
230 | */ |
219 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
231 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
220 | { |
232 | { |
221 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
233 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
222 | } |
234 | } |
223 | 235 | ||
224 | /** Store GDTR register to memory. |
236 | /** Store GDTR register to memory. |
225 | * |
237 | * |
226 | * @param gdtr_reg Address of memory to where to load GDTR. |
238 | * @param gdtr_reg Address of memory to where to load GDTR. |
227 | */ |
239 | */ |
228 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
240 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
229 | { |
241 | { |
230 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
242 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
231 | } |
243 | } |
232 | 244 | ||
233 | /** Load IDTR register from memory. |
245 | /** Load IDTR register from memory. |
234 | * |
246 | * |
235 | * @param idtr_reg Address of memory from where to load IDTR. |
247 | * @param idtr_reg Address of memory from where to load IDTR. |
236 | */ |
248 | */ |
237 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
249 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
238 | { |
250 | { |
239 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
251 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
240 | } |
252 | } |
241 | 253 | ||
242 | /** Load TR from descriptor table. |
254 | /** Load TR from descriptor table. |
243 | * |
255 | * |
244 | * @param sel Selector specifying descriptor of TSS segment. |
256 | * @param sel Selector specifying descriptor of TSS segment. |
245 | */ |
257 | */ |
246 | static inline void tr_load(uint16_t sel) |
258 | static inline void tr_load(uint16_t sel) |
247 | { |
259 | { |
248 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
260 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
249 | } |
261 | } |
250 | 262 | ||
251 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
263 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
252 | { \ |
264 | { \ |
253 | unative_t res; \ |
265 | unative_t res; \ |
254 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
266 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
255 | return res; \ |
267 | return res; \ |
256 | } |
268 | } |
257 | 269 | ||
258 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
270 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
259 | { \ |
271 | { \ |
260 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
272 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
261 | } |
273 | } |
262 | 274 | ||
263 | GEN_READ_REG(cr0) |
275 | GEN_READ_REG(cr0) |
264 | GEN_READ_REG(cr2) |
276 | GEN_READ_REG(cr2) |
265 | GEN_READ_REG(cr3) |
277 | GEN_READ_REG(cr3) |
266 | GEN_WRITE_REG(cr3) |
278 | GEN_WRITE_REG(cr3) |
267 | 279 | ||
268 | GEN_READ_REG(dr0) |
280 | GEN_READ_REG(dr0) |
269 | GEN_READ_REG(dr1) |
281 | GEN_READ_REG(dr1) |
270 | GEN_READ_REG(dr2) |
282 | GEN_READ_REG(dr2) |
271 | GEN_READ_REG(dr3) |
283 | GEN_READ_REG(dr3) |
272 | GEN_READ_REG(dr6) |
284 | GEN_READ_REG(dr6) |
273 | GEN_READ_REG(dr7) |
285 | GEN_READ_REG(dr7) |
274 | 286 | ||
275 | GEN_WRITE_REG(dr0) |
287 | GEN_WRITE_REG(dr0) |
276 | GEN_WRITE_REG(dr1) |
288 | GEN_WRITE_REG(dr1) |
277 | GEN_WRITE_REG(dr2) |
289 | GEN_WRITE_REG(dr2) |
278 | GEN_WRITE_REG(dr3) |
290 | GEN_WRITE_REG(dr3) |
279 | GEN_WRITE_REG(dr6) |
291 | GEN_WRITE_REG(dr6) |
280 | GEN_WRITE_REG(dr7) |
292 | GEN_WRITE_REG(dr7) |
281 | 293 | ||
282 | extern size_t interrupt_handler_size; |
294 | extern size_t interrupt_handler_size; |
283 | extern void interrupt_handlers(void); |
295 | extern void interrupt_handlers(void); |
284 | 296 | ||
285 | #endif |
297 | #endif |
286 | 298 | ||
287 | /** @} |
299 | /** @} |
288 | */ |
300 | */ |
289 | 301 |