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1 | # |
1 | # |
2 | # Copyright (C) 2006 Martin Decky |
2 | # Copyright (C) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include "regname.h" |
29 | #include "regname.h" |
30 | 30 | ||
31 | .data |
31 | .data |
32 | 32 | ||
33 | flush_buffer: |
33 | flush_buffer: |
34 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
34 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
35 | 35 | ||
36 | .text |
36 | .text |
37 | 37 | ||
38 | .global memsetb |
38 | .global memsetb |
39 | .global memcpy |
39 | .global memcpy |
40 | .global flush_instruction_cache |
40 | .global flush_instruction_cache |
41 | .global jump_to_kernel |
41 | .global jump_to_kernel |
42 | 42 | ||
43 | memsetb: |
43 | memsetb: |
44 | rlwimi r5, r5, 8, 16, 23 |
44 | rlwimi r5, r5, 8, 16, 23 |
45 | rlwimi r5, r5, 16, 0, 15 |
45 | rlwimi r5, r5, 16, 0, 15 |
46 | 46 | ||
47 | addi r14, r3, -4 |
47 | addi r14, r3, -4 |
48 | 48 | ||
49 | cmplwi 0, r4, 4 |
49 | cmplwi 0, r4, 4 |
50 | blt 7f |
50 | blt 7f |
51 | 51 | ||
52 | stwu r5, 4(r14) |
52 | stwu r5, 4(r14) |
53 | beqlr |
53 | beqlr |
54 | 54 | ||
55 | andi. r15, r14, 3 |
55 | andi. r15, r14, 3 |
56 | add r4, r15, r4 |
56 | add r4, r15, r4 |
57 | subf r14, r15, r14 |
57 | subf r14, r15, r14 |
58 | srwi r15, r4, 2 |
58 | srwi r15, r4, 2 |
59 | mtctr r15 |
59 | mtctr r15 |
60 | 60 | ||
61 | bdz 6f |
61 | bdz 6f |
62 | 62 | ||
63 | 1: |
63 | 1: |
64 | stwu r5, 4(r14) |
64 | stwu r5, 4(r14) |
65 | bdnz 1b |
65 | bdnz 1b |
66 | 66 | ||
67 | 6: |
67 | 6: |
68 | 68 | ||
69 | andi. r4, r4, 3 |
69 | andi. r4, r4, 3 |
70 | 70 | ||
71 | 7: |
71 | 7: |
72 | 72 | ||
73 | cmpwi 0, r4, 0 |
73 | cmpwi 0, r4, 0 |
74 | beqlr |
74 | beqlr |
75 | 75 | ||
76 | mtctr r4 |
76 | mtctr r4 |
77 | addi r6, r6, 3 |
77 | addi r6, r6, 3 |
78 | 78 | ||
79 | 8: |
79 | 8: |
80 | 80 | ||
81 | stbu r5, 1(r14) |
81 | stbu r5, 1(r14) |
82 | bdnz 8b |
82 | bdnz 8b |
83 | 83 | ||
84 | blr |
84 | blr |
85 | 85 | ||
86 | memcpy: |
86 | memcpy: |
87 | srwi. r7, r5, 3 |
87 | srwi. r7, r5, 3 |
88 | addi r6, r3, -4 |
88 | addi r6, r3, -4 |
89 | addi r4, r4, -4 |
89 | addi r4, r4, -4 |
90 | beq 2f |
90 | beq 2f |
91 | 91 | ||
92 | andi. r0, r6, 3 |
92 | andi. r0, r6, 3 |
93 | mtctr r7 |
93 | mtctr r7 |
94 | bne 5f |
94 | bne 5f |
95 | 95 | ||
96 | 1: |
96 | 1: |
97 | 97 | ||
98 | lwz r7, 4(r4) |
98 | lwz r7, 4(r4) |
99 | lwzu r8, 8(r4) |
99 | lwzu r8, 8(r4) |
100 | stw r7, 4(r6) |
100 | stw r7, 4(r6) |
101 | stwu r8, 8(r6) |
101 | stwu r8, 8(r6) |
102 | bdnz 1b |
102 | bdnz 1b |
103 | 103 | ||
104 | andi. r5, r5, 7 |
104 | andi. r5, r5, 7 |
105 | 105 | ||
106 | 2: |
106 | 2: |
107 | 107 | ||
108 | cmplwi 0, r5, 4 |
108 | cmplwi 0, r5, 4 |
109 | blt 3f |
109 | blt 3f |
110 | 110 | ||
111 | lwzu r0, 4(r4) |
111 | lwzu r0, 4(r4) |
112 | addi r5, r5, -4 |
112 | addi r5, r5, -4 |
113 | stwu r0, 4(r6) |
113 | stwu r0, 4(r6) |
114 | 114 | ||
115 | 3: |
115 | 3: |
116 | 116 | ||
117 | cmpwi 0, r5, 0 |
117 | cmpwi 0, r5, 0 |
118 | beqlr |
118 | beqlr |
119 | mtctr r5 |
119 | mtctr r5 |
120 | addi r4, r4, 3 |
120 | addi r4, r4, 3 |
121 | addi r6, r6, 3 |
121 | addi r6, r6, 3 |
122 | 122 | ||
123 | 4: |
123 | 4: |
124 | 124 | ||
125 | lbzu r0, 1(r4) |
125 | lbzu r0, 1(r4) |
126 | stbu r0, 1(r6) |
126 | stbu r0, 1(r6) |
127 | bdnz 4b |
127 | bdnz 4b |
128 | blr |
128 | blr |
129 | 129 | ||
130 | 5: |
130 | 5: |
131 | 131 | ||
132 | subfic r0, r0, 4 |
132 | subfic r0, r0, 4 |
133 | mtctr r0 |
133 | mtctr r0 |
134 | 134 | ||
135 | 6: |
135 | 6: |
136 | 136 | ||
137 | lbz r7, 4(r4) |
137 | lbz r7, 4(r4) |
138 | addi r4, r4, 1 |
138 | addi r4, r4, 1 |
139 | stb r7, 4(r6) |
139 | stb r7, 4(r6) |
140 | addi r6, r6, 1 |
140 | addi r6, r6, 1 |
141 | bdnz 6b |
141 | bdnz 6b |
142 | subf r5, r0, r5 |
142 | subf r5, r0, r5 |
143 | rlwinm. r7, r5, 32-3, 3, 31 |
143 | rlwinm. r7, r5, 32-3, 3, 31 |
144 | beq 2b |
144 | beq 2b |
145 | mtctr r7 |
145 | mtctr r7 |
146 | b 1b |
146 | b 1b |
147 | 147 | ||
148 | flush_instruction_cache: |
148 | flush_instruction_cache: |
149 | 149 | ||
150 | # Flush data cache |
150 | # Flush data cache |
151 | 151 | ||
152 | lis r3, flush_buffer@h |
152 | lis r3, flush_buffer@h |
153 | ori r3, r3, flush_buffer@l |
153 | ori r3, r3, flush_buffer@l |
154 | li r4, L1_CACHE_LINES |
154 | li r4, L1_CACHE_LINES |
155 | mtctr r4 |
155 | mtctr r4 |
156 | 156 | ||
157 | 0: |
157 | 0: |
158 | 158 | ||
159 | lwz r4, 0(r3) |
159 | lwz r4, 0(r3) |
160 | addi r3, r3, L1_CACHE_BYTES |
160 | addi r3, r3, L1_CACHE_BYTES |
161 | bdnz 0b |
161 | bdnz 0b |
162 | 162 | ||
163 | # Invalidate instruction cache |
163 | # Invalidate instruction cache |
164 | 164 | ||
165 | li r3, 0 |
165 | li r3, 0 |
166 | ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci) |
166 | ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci) |
167 | mfspr r4, hid0 |
167 | mfspr r4, hid0 |
168 | or r5, r4, r3 |
168 | or r5, r4, r3 |
169 | isync |
169 | isync |
170 | mtspr hid0, r5 |
170 | mtspr hid0, r5 |
171 | sync |
171 | sync |
172 | isync |
172 | isync |
173 | 173 | ||
174 | # Enable instruction cache |
174 | # Enable instruction cache |
175 | 175 | ||
176 | ori r5, r4, hid0_ice |
176 | ori r5, r4, hid0_ice |
177 | mtspr hid0, r5 |
177 | mtspr hid0, r5 |
178 | sync |
178 | sync |
179 | isync |
179 | isync |
180 | blr |
180 | blr |
181 | 181 | ||
182 | jump_to_kernel: |
182 | jump_to_kernel: |
- | 183 | ||
- | 184 | # r3 = kernel_start (va) |
|
- | 185 | # r4 = memmap (pa) |
|
- | 186 | # r5 = real_mode (pa) |
|
- | 187 | ||
- | 188 | mtspr srr0, r5 |
|
- | 189 | ||
- | 190 | # jumps to real_mode |
|
- | 191 | ||
- | 192 | mfmsr r5 |
|
- | 193 | lis r6, ~0@h |
|
- | 194 | ori r6, r6, ~(msr_ir | msr_dr)@l |
|
- | 195 | and r5, r5, r6 |
|
- | 196 | mtspr srr1, r5 |
|
- | 197 | rfi |
|
- | 198 | ||
- | 199 | .section REALMODE |
|
- | 200 | .align 12 |
|
- | 201 | .global real_mode |
|
- | 202 | ||
- | 203 | real_mode: |
|
- | 204 | ||
- | 205 | # fill segment registers |
|
- | 206 | ||
- | 207 | li r5, 16 |
|
- | 208 | mtctr r5 |
|
- | 209 | li r5, 0 |
|
- | 210 | li r6, 0 |
|
- | 211 | ||
- | 212 | seg_fill: |
|
- | 213 | ||
- | 214 | mtsrin r6, r5 |
|
- | 215 | addis r5, r5, 0x1000 # move to next SR |
|
- | 216 | addis r6, r6, 0x10 # add 256 MB, move to next SR |
|
- | 217 | ||
- | 218 | bdnz seg_fill |
|
- | 219 | ||
- | 220 | # bootstrap kernel |
|
- | 221 | # |
|
- | 222 | # r3 = kernel_start (va) |
|
- | 223 | # r4 = memmap (pa) -> r10 |
|
- | 224 | ||
- | 225 | mtspr srr0, r3 |
|
- | 226 | ||
- | 227 | mfmsr r5 |
|
- | 228 | ori r5, r5, (msr_ir | msr_dr)@l |
|
- | 229 | mtspr srr1, r5 |
|
- | 230 | ||
183 | mr r10, r4 |
231 | mr r10, r4 |
184 | mtlr r3 |
- | |
185 | blr |
232 | rfi |
186 | 233 | ||
187 | 234 | ||
188 |
|
235 |
|
189 | 236 | ||
190 | 237 | ||
191 | 238 |