WebSVN – HelenOS – Diff – /trunk/boot/arch/arm32/loader/mm.h


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 
/** @addtogroup arm32boot
 * @{
 */
/** @file
 *  @brief Memory management used while booting the kernel.
 *
 *  So called "section" paging is used while booting the kernel. The term "section"
 *  comes from the ARM architecture specification and stands for the following:
 *  one-level paging, 1MB sized pages, 4096 entries in the page table.
 */
 
 
#ifndef BOOT_arm32__MM_H
#define BOOT_arm32__MM_H
 
 
#ifndef __ASM__
#include "types.h"
#endif
 
 
/** Frame width. */
#define FRAME_WIDTH                 20
 
/** Frame size. */
#define FRAME_SIZE                  (1 << FRAME_WIDTH)
 
/** Page size in 2-level paging which is switched on later after the kernel initialization. */
#define KERNEL_PAGE_SIZE            (1 << 12)
 
 
#ifndef __ASM__
/** Converts kernel address to physical address. */
#   define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)
/** Converts physical address to kernel address. */
#   define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x)                 ((x) - 0x80000000)
#   define PA2KA(x)                 ((x) + 0x80000000)
#endif
 
 
/** Number of entries in PTL0. */
#define PTL0_ENTRIES                (1<<12)             /* 4096 */
 
/** Size of an entry in PTL0. */
#define PTL0_ENTRY_SIZE             4
 
/** Returns number of frame the address belongs to. */
#define ADDR2PFN( addr )            ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
 
/** Describes "section" page table entry (one-level paging with 1MB sized pages). */  
#define PTE_DESCRIPTOR_SECTION      0x2
 
/** Page table access rights: user - no access, kernel - read/write. */
#define PTE_AP_USER_NO_KERNEL_RW    0x1
 
 
#ifndef __ASM__
 
 
/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
 * pages). Used only while booting the kernel.
 */
typedef struct {
    unsigned descriptor_type     : 2;
    unsigned bufferable          : 1;
    unsigned cacheable           : 1;
    unsigned impl_specific       : 1;
    unsigned domain              : 4;
    unsigned should_be_zero_1    : 1;
    unsigned access_permission   : 2;  
    unsigned should_be_zero_2    : 8;
    unsigned section_base_addr   : 12;
} __attribute__ ((packed)) pte_level0_section_t;
 
 
/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
extern pte_level0_section_t page_table[PTL0_ENTRIES];
 
extern void mmu_start(void);
 
 
/** Enables paging. */
static inline void enable_paging()
{
    /* c3 - each two bits controls access to the one of domains (16)
     *      0b01 - behave as a client (user) of a domain
     */
    asm volatile (
        // behave as a client of domains
        "ldr r0, =0x55555555       \n"
        "mcr p15, 0, r0, c3, c0, 0 \n"
 
        // current settings
        "mrc p15, 0, r0, c1, c0, 0 \n"
 
        // mask to enable paging
        "ldr r1, =0x00000001       \n"
        "orr r0, r0, r1            \n"
 
        // store settings
        "mcr p15, 0, r0, c1, c0, 0 \n"
        :
        :
        : "r0", "r1"
    );
}
 
 
/** Sets the address of level 0 page table to CP15 register 2.
 *
 * @param pt Address of a page table to set.
 */  
static inline void set_ptl0_address(pte_level0_section_t* pt)
{
    asm volatile (
        "mcr p15, 0, %0, c2, c0, 0 \n"
        :
        : "r"(pt)
    );
}
 
 
#endif
 
#endif
 
/** @}
 */
 
 

Rev 2339	Rev 2349
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29		29
30	/** @addtogroup arm32boot	30	/** @addtogroup arm32boot
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
-		34	* @brief Memory management used while booting the kernel.
-		35	*
-		36	* So called "section" paging is used while booting the kernel. The term "section"
-		37	* comes from the ARM architecture specification and stands for the following:
-		38	* one-level paging, 1MB sized pages, 4096 entries in the page table.
34	*/	39	*/
35		40
36		41
37	#ifndef BOOT_arm32__MM_H	42	#ifndef BOOT_arm32__MM_H
38	#define BOOT_arm32__MM_H	43	#define BOOT_arm32__MM_H
39		44
40		45
41	#ifndef __ASM__	46	#ifndef __ASM__
42	#include "types.h"	47	#include "types.h"
43	#endif	48	#endif
44		49
45		50
46	/** Frame width. */	51	/** Frame width. */
47	#define FRAME_WIDTH 20 /* 4KB frames */	52	#define FRAME_WIDTH 20
48		53
49	/** Frame size. */	54	/** Frame size. */
50	#define FRAME_SIZE (1 << FRAME_WIDTH)	55	#define FRAME_SIZE (1 << FRAME_WIDTH)
51		56
52	/** Page size in 2-level paging which is switched on later in the kernel initialization. */	57	/** Page size in 2-level paging which is switched on later after the kernel initialization. */
53	#define PAGE_SIZE (1 << 12)	58	#define KERNEL_PAGE_SIZE (1 << 12)
54		59
55		60
56	#ifndef __ASM__	61	#ifndef __ASM__
-		62	/** Converts kernel address to physical address. */
57	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	63	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
-		64	/** Converts physical address to kernel address. */
58	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	65	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
59	#else	66	#else
60	# define KA2PA(x) ((x) - 0x80000000)	67	# define KA2PA(x) ((x) - 0x80000000)
61	# define PA2KA(x) ((x) + 0x80000000)	68	# define PA2KA(x) ((x) + 0x80000000)
62	#endif	69	#endif
63		70
64		71
65	/** Number of entries in PTL0. */	72	/** Number of entries in PTL0. */
66	#define PTL0_ENTRIES (1<<12) /* 4096 */	73	#define PTL0_ENTRIES (1<<12) /* 4096 */
67		74
68	/** Size of an entry in PTL0. */	75	/** Size of an entry in PTL0. */
69	#define PTL0_ENTRY_SIZE 4	76	#define PTL0_ENTRY_SIZE 4
70		77
71	/** Returns number of frame the address belongs to. */	78	/** Returns number of frame the address belongs to. */
72	#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH )	79	#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
73		80
74	/** Describes "section" page table entry (one-level paging with 1MB sized pages). */	81	/** Describes "section" page table entry (one-level paging with 1MB sized pages). */
75	#define PTE_DESCRIPTOR_SECTION 0x2	82	#define PTE_DESCRIPTOR_SECTION 0x2
76		83
77	/** Page table access rights: user - no access, kernel - read/write. */	84	/** Page table access rights: user - no access, kernel - read/write. */
78	#define PTE_AP_USER_NO_KERNEL_RW 0x1	85	#define PTE_AP_USER_NO_KERNEL_RW 0x1
79		86
80		87
81	#ifndef __ASM__	88	#ifndef __ASM__
82		89
83		90
84	/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized	91	/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
85	* pages). Used only while booting the kernel. */	92	* pages). Used only while booting the kernel.
-		93	*/
86	typedef struct {	94	typedef struct {
87	unsigned descriptor_type : 2;	95	unsigned descriptor_type : 2;
88	unsigned bufferable : 1;	96	unsigned bufferable : 1;
89	unsigned cacheable : 1;	97	unsigned cacheable : 1;
90	unsigned impl_specific : 1;	98	unsigned impl_specific : 1;
91	unsigned domain : 4;	99	unsigned domain : 4;
92	unsigned should_be_zero_1 : 1;	100	unsigned should_be_zero_1 : 1;
93	unsigned access_permission : 2;	101	unsigned access_permission : 2;
94	unsigned should_be_zero_2 : 8;	102	unsigned should_be_zero_2 : 8;
95	unsigned section_base_addr : 12;	103	unsigned section_base_addr : 12;
96	} __attribute__ ((packed)) pte_level0_section_t;	104	} __attribute__ ((packed)) pte_level0_section_t;
97		105
98		106
99	/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */	107	/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
100	extern pte_level0_section_t page_table[PTL0_ENTRIES];	108	extern pte_level0_section_t page_table[PTL0_ENTRIES];
101		109
102	extern void mmu_start(void);	110	extern void mmu_start(void);
103		111
104		112
105	/** Enables paging. */	113	/** Enables paging. */
106	static inline void enable_paging()	114	static inline void enable_paging()
107	{	115	{
108	/* c3 - each two bits controls access to the one of domains (16)	116	/* c3 - each two bits controls access to the one of domains (16)
109	* 0b01 - behave as a client (user) of a domain	117	* 0b01 - behave as a client (user) of a domain
110	*/	118	*/
111	asm volatile (	119	asm volatile (
112	// behave as a client of domains	120	// behave as a client of domains
113	"ldr r0, =0x55555555 \n"	121	"ldr r0, =0x55555555 \n"
114	"mcr p15, 0, r0, c3, c0, 0 \n"	122	"mcr p15, 0, r0, c3, c0, 0 \n"
115		123
116	// current settings	124	// current settings
117	"mrc p15, 0, r0, c1, c0, 0 \n"	125	"mrc p15, 0, r0, c1, c0, 0 \n"
118		126
119	// mask to enable paging	127	// mask to enable paging
120	"ldr r1, =0x00000001 \n"	128	"ldr r1, =0x00000001 \n"
121	"orr r0, r0, r1 \n"	129	"orr r0, r0, r1 \n"
122		130
123	// store settings	131	// store settings
124	"mcr p15, 0, r0, c1, c0, 0 \n"	132	"mcr p15, 0, r0, c1, c0, 0 \n"
125	:	133	:
126	:	134	:
127	: "r0", "r1"	135	: "r0", "r1"
128	);	136	);
129	}	137	}
130		138
131		139
132	/** Sets the address of level 0 page table to CP15 register 2.	140	/** Sets the address of level 0 page table to CP15 register 2.
133	*	141	*
134	* @param pt Address of a page table to set.	142	* @param pt Address of a page table to set.
135	*/	143	*/
136	static inline void set_ptl0_address(pte_level0_section_t* pt)	144	static inline void set_ptl0_address(pte_level0_section_t* pt)
137	{	145	{
138	asm volatile (	146	asm volatile (
139	"mcr p15, 0, %0, c2, c0, 0 \n"	147	"mcr p15, 0, %0, c2, c0, 0 \n"
140	:	148	:
141	: "r"(pt)	149	: "r"(pt)
142	);	150	);
143	}	151	}
144		152
145		153
146	#endif	154	#endif
147		155
148	#endif	156	#endif
149		157
150	/** @}	158	/** @}
151	*/	159	*/
152		160
153		161

Subversion Repositories HelenOS

(root)/trunk/boot/arch/arm32/loader/mm.h @ 4681 – Rev 2339 → 2349