WebSVN – HelenOS – Diff – /tags/0.4.1/kernel/arch/ppc32/src/asm.S


#
# Copyright (c) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
 
.text
 
.global userspace_asm
.global iret
.global iret_syscall
.global memsetb
.global memsetw
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
 
userspace_asm:
 
	# r3 = uspace_uarg
	# r4 = stack
	# r5 = entry
	
	# disable interrupts
 
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	# set entry point
	
	mtsrr0 r5
	
	# set problem state, enable interrupts
	
	ori r31, r31, msr_pr
	ori r31, r31, msr_ee
	mtsrr1 r31
	
	# set stack
	
	mr sp, r4
 
	# %r6 is defined to hold pcb_ptr - set it to 0
 
	xor r6, r6, r6
	
	# jump to userspace
	
	rfi
 
iret:
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r3, 16(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 156(sp)
	lwz sp, 160(sp)
	
	rfi
 
iret_syscall:
	
	# reset decrementer
 
	li r31, 1000
	mtdec r31
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 156(sp)
	lwz sp, 160(sp)
 
	rfi
 
memsetb:
	b _memsetb
 
memsetw:
	b _memsetw
 
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
 
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	# return zero, failure
	xor r3, r3, r3
	blr
 

Rev 4220	Rev 4687
1	#	1	#
2	# Copyright (c) 2005 Martin Decky	2	# Copyright (c) 2005 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.global userspace_asm	33	.global userspace_asm
34	.global iret	34	.global iret
35	.global iret_syscall	35	.global iret_syscall
36	.global memsetb	36	.global memsetb
37	.global memsetw	37	.global memsetw
38	.global memcpy	38	.global memcpy
39	.global memcpy_from_uspace	39	.global memcpy_from_uspace
40	.global memcpy_to_uspace	40	.global memcpy_to_uspace
41	.global memcpy_from_uspace_failover_address	41	.global memcpy_from_uspace_failover_address
42	.global memcpy_to_uspace_failover_address	42	.global memcpy_to_uspace_failover_address
43		43
44	userspace_asm:	44	userspace_asm:
45		45
46	# r3 = uspace_uarg	46	# r3 = uspace_uarg
47	# r4 = stack	47	# r4 = stack
48	# r5 = entry	48	# r5 = entry
49		49
50	# disable interrupts	50	# disable interrupts
51		51
52	mfmsr r31	52	mfmsr r31
53	rlwinm r31, r31, 0, 17, 15	53	rlwinm r31, r31, 0, 17, 15
54	mtmsr r31	54	mtmsr r31
55		55
56	# set entry point	56	# set entry point
57		57
58	mtsrr0 r5	58	mtsrr0 r5
59		59
60	# set problem state, enable interrupts	60	# set problem state, enable interrupts
61		61
62	ori r31, r31, msr_pr	62	ori r31, r31, msr_pr
63	ori r31, r31, msr_ee	63	ori r31, r31, msr_ee
64	mtsrr1 r31	64	mtsrr1 r31
65		65
66	# set stack	66	# set stack
67		67
68	mr sp, r4	68	mr sp, r4
69		69
70	# %r6 is defined to hold pcb_ptr - set it to 0	70	# %r6 is defined to hold pcb_ptr - set it to 0
71		71
72	xor r6, r6, r6	72	xor r6, r6, r6
73		73
74	# jump to userspace	74	# jump to userspace
75		75
76	rfi	76	rfi
77		77
78	iret:	78	iret:
79		79
80	# disable interrupts	80	# disable interrupts
81		81
82	mfmsr r31	82	mfmsr r31
83	rlwinm r31, r31, 0, 17, 15	83	rlwinm r31, r31, 0, 17, 15
84	mtmsr r31	84	mtmsr r31
85		85
86	lwz r0, 8(sp)	86	lwz r0, 8(sp)
87	lwz r2, 12(sp)	87	lwz r2, 12(sp)
88	lwz r3, 16(sp)	88	lwz r3, 16(sp)
89	lwz r4, 20(sp)	89	lwz r4, 20(sp)
90	lwz r5, 24(sp)	90	lwz r5, 24(sp)
91	lwz r6, 28(sp)	91	lwz r6, 28(sp)
92	lwz r7, 32(sp)	92	lwz r7, 32(sp)
93	lwz r8, 36(sp)	93	lwz r8, 36(sp)
94	lwz r9, 40(sp)	94	lwz r9, 40(sp)
95	lwz r10, 44(sp)	95	lwz r10, 44(sp)
96	lwz r11, 48(sp)	96	lwz r11, 48(sp)
97	lwz r13, 52(sp)	97	lwz r13, 52(sp)
98	lwz r14, 56(sp)	98	lwz r14, 56(sp)
99	lwz r15, 60(sp)	99	lwz r15, 60(sp)
100	lwz r16, 64(sp)	100	lwz r16, 64(sp)
101	lwz r17, 68(sp)	101	lwz r17, 68(sp)
102	lwz r18, 72(sp)	102	lwz r18, 72(sp)
103	lwz r19, 76(sp)	103	lwz r19, 76(sp)
104	lwz r20, 80(sp)	104	lwz r20, 80(sp)
105	lwz r21, 84(sp)	105	lwz r21, 84(sp)
106	lwz r22, 88(sp)	106	lwz r22, 88(sp)
107	lwz r23, 92(sp)	107	lwz r23, 92(sp)
108	lwz r24, 96(sp)	108	lwz r24, 96(sp)
109	lwz r25, 100(sp)	109	lwz r25, 100(sp)
110	lwz r26, 104(sp)	110	lwz r26, 104(sp)
111	lwz r27, 108(sp)	111	lwz r27, 108(sp)
112	lwz r28, 112(sp)	112	lwz r28, 112(sp)
113	lwz r29, 116(sp)	113	lwz r29, 116(sp)
114	lwz r30, 120(sp)	114	lwz r30, 120(sp)
115	lwz r31, 124(sp)	115	lwz r31, 124(sp)
116		116
117	lwz r12, 128(sp)	117	lwz r12, 128(sp)
118	mtcr r12	118	mtcr r12
119		119
120	lwz r12, 132(sp)	120	lwz r12, 132(sp)
121	mtsrr0 r12	121	mtsrr0 r12
122		122
123	lwz r12, 136(sp)	123	lwz r12, 136(sp)
124	mtsrr1 r12	124	mtsrr1 r12
125		125
126	lwz r12, 140(sp)	126	lwz r12, 140(sp)
127	mtlr r12	127	mtlr r12
128		128
129	lwz r12, 144(sp)	129	lwz r12, 144(sp)
130	mtctr r12	130	mtctr r12
131		131
132	lwz r12, 148(sp)	132	lwz r12, 148(sp)
133	mtxer r12	133	mtxer r12
134		134
135	lwz r12, 156(sp)	135	lwz r12, 156(sp)
136	lwz sp, 160(sp)	136	lwz sp, 160(sp)
137		137
138	rfi	138	rfi
139		139
140	iret_syscall:	140	iret_syscall:
141		141
142	# reset decrementer	142	# reset decrementer
143		143
144	li r31, 1000	144	li r31, 1000
145	mtdec r31	145	mtdec r31
146		146
147	# disable interrupts	147	# disable interrupts
148		148
149	mfmsr r31	149	mfmsr r31
150	rlwinm r31, r31, 0, 17, 15	150	rlwinm r31, r31, 0, 17, 15
151	mtmsr r31	151	mtmsr r31
152		152
153	lwz r0, 8(sp)	153	lwz r0, 8(sp)
154	lwz r2, 12(sp)	154	lwz r2, 12(sp)
155	lwz r4, 20(sp)	155	lwz r4, 20(sp)
156	lwz r5, 24(sp)	156	lwz r5, 24(sp)
157	lwz r6, 28(sp)	157	lwz r6, 28(sp)
158	lwz r7, 32(sp)	158	lwz r7, 32(sp)
159	lwz r8, 36(sp)	159	lwz r8, 36(sp)
160	lwz r9, 40(sp)	160	lwz r9, 40(sp)
161	lwz r10, 44(sp)	161	lwz r10, 44(sp)
162	lwz r11, 48(sp)	162	lwz r11, 48(sp)
163	lwz r13, 52(sp)	163	lwz r13, 52(sp)
164	lwz r14, 56(sp)	164	lwz r14, 56(sp)
165	lwz r15, 60(sp)	165	lwz r15, 60(sp)
166	lwz r16, 64(sp)	166	lwz r16, 64(sp)
167	lwz r17, 68(sp)	167	lwz r17, 68(sp)
168	lwz r18, 72(sp)	168	lwz r18, 72(sp)
169	lwz r19, 76(sp)	169	lwz r19, 76(sp)
170	lwz r20, 80(sp)	170	lwz r20, 80(sp)
171	lwz r21, 84(sp)	171	lwz r21, 84(sp)
172	lwz r22, 88(sp)	172	lwz r22, 88(sp)
173	lwz r23, 92(sp)	173	lwz r23, 92(sp)
174	lwz r24, 96(sp)	174	lwz r24, 96(sp)
175	lwz r25, 100(sp)	175	lwz r25, 100(sp)
176	lwz r26, 104(sp)	176	lwz r26, 104(sp)
177	lwz r27, 108(sp)	177	lwz r27, 108(sp)
178	lwz r28, 112(sp)	178	lwz r28, 112(sp)
179	lwz r29, 116(sp)	179	lwz r29, 116(sp)
180	lwz r30, 120(sp)	180	lwz r30, 120(sp)
181	lwz r31, 124(sp)	181	lwz r31, 124(sp)
182		182
183	lwz r12, 128(sp)	183	lwz r12, 128(sp)
184	mtcr r12	184	mtcr r12
185		185
186	lwz r12, 132(sp)	186	lwz r12, 132(sp)
187	mtsrr0 r12	187	mtsrr0 r12
188		188
189	lwz r12, 136(sp)	189	lwz r12, 136(sp)
190	mtsrr1 r12	190	mtsrr1 r12
191		191
192	lwz r12, 140(sp)	192	lwz r12, 140(sp)
193	mtlr r12	193	mtlr r12
194		194
195	lwz r12, 144(sp)	195	lwz r12, 144(sp)
196	mtctr r12	196	mtctr r12
197		197
198	lwz r12, 148(sp)	198	lwz r12, 148(sp)
199	mtxer r12	199	mtxer r12
200		200
201	lwz r12, 156(sp)	201	lwz r12, 156(sp)
202	lwz sp, 160(sp)	202	lwz sp, 160(sp)
203		203
204	rfi	204	rfi
205		205
206	memsetb:	206	memsetb:
207	b _memsetb	207	b _memsetb
208		208
209	memsetw:	209	memsetw:
210	b _memsetw	210	b _memsetw
211		211
212	memcpy:	212	memcpy:
213	memcpy_from_uspace:	213	memcpy_from_uspace:
214	memcpy_to_uspace:	214	memcpy_to_uspace:
215		215
216	srwi. r7, r5, 3	216	srwi. r7, r5, 3
217	addi r6, r3, -4	217	addi r6, r3, -4
218	addi r4, r4, -4	218	addi r4, r4, -4
219	beq 2f	219	beq 2f
220		220
221	andi. r0, r6, 3	221	andi. r0, r6, 3
222	mtctr r7	222	mtctr r7
223	bne 5f	223	bne 5f
224		224
225	1:	225	1:
226		226
227	lwz r7, 4(r4)	227	lwz r7, 4(r4)
228	lwzu r8, 8(r4)	228	lwzu r8, 8(r4)
229	stw r7, 4(r6)	229	stw r7, 4(r6)
230	stwu r8, 8(r6)	230	stwu r8, 8(r6)
231	bdnz 1b	231	bdnz 1b
232		232
233	andi. r5, r5, 7	233	andi. r5, r5, 7
234		234
235	2:	235	2:
236		236
237	cmplwi 0, r5, 4	237	cmplwi 0, r5, 4
238	blt 3f	238	blt 3f
239		239
240	lwzu r0, 4(r4)	240	lwzu r0, 4(r4)
241	addi r5, r5, -4	241	addi r5, r5, -4
242	stwu r0, 4(r6)	242	stwu r0, 4(r6)
243		243
244	3:	244	3:
245		245
246	cmpwi 0, r5, 0	246	cmpwi 0, r5, 0
247	beqlr	247	beqlr
248	mtctr r5	248	mtctr r5
249	addi r4, r4, 3	249	addi r4, r4, 3
250	addi r6, r6, 3	250	addi r6, r6, 3
251		251
252	4:	252	4:
253		253
254	lbzu r0, 1(r4)	254	lbzu r0, 1(r4)
255	stbu r0, 1(r6)	255	stbu r0, 1(r6)
256	bdnz 4b	256	bdnz 4b
257	blr	257	blr
258		258
259	5:	259	5:
260		260
261	subfic r0, r0, 4	261	subfic r0, r0, 4
262	mtctr r0	262	mtctr r0
263		263
264	6:	264	6:
265		265
266	lbz r7, 4(r4)	266	lbz r7, 4(r4)
267	addi r4, r4, 1	267	addi r4, r4, 1
268	stb r7, 4(r6)	268	stb r7, 4(r6)
269	addi r6, r6, 1	269	addi r6, r6, 1
270	bdnz 6b	270	bdnz 6b
271	subf r5, r0, r5	271	subf r5, r0, r5
272	rlwinm. r7, r5, 32-3, 3, 31	272	rlwinm. r7, r5, 32-3, 3, 31
273	beq 2b	273	beq 2b
274	mtctr r7	274	mtctr r7
275	b 1b	275	b 1b
276		276
277	memcpy_from_uspace_failover_address:	277	memcpy_from_uspace_failover_address:
278	memcpy_to_uspace_failover_address:	278	memcpy_to_uspace_failover_address:
279	# return zero, failure	279	# return zero, failure
280	xor r3, r3, r3	280	xor r3, r3, r3
281	blr	281	blr
282		282

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(root)/tags/0.4.1/kernel/arch/ppc32/src/asm.S – Rev 4220 → 4687