WebSVN – HelenOS – Diff – /tags/0.4.1/kernel/arch/arm32/src/interrupt.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Interrupts controlling routines.
 */
 
#include <arch/asm.h>
#include <arch/regutils.h>
#include <ddi/irq.h>
#include <ddi/device.h>
#include <interrupt.h>
 
#ifdef MACHINE_testarm
    #include <arch/mach/testarm/testarm.h>
#endif
 
#ifdef MACHINE_integratorcp
    #include <arch/mach/integratorcp/integratorcp.h>
#endif
 
/** Initial size of a table holding interrupt handlers. */
#define IRQ_COUNT 8
 
/** Disable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_disable(void)
{
    ipl_t ipl = current_status_reg_read();
 
    current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
   
    return ipl;
}
 
/** Enable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_enable(void)
{
    ipl_t ipl = current_status_reg_read();
 
    current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
   
    return ipl;
}
 
/** Restore interrupt priority level.
 *
 * @param ipl Saved interrupt priority level.
 */
void interrupts_restore(ipl_t ipl)
{
    current_status_reg_control_write(
        (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
        (ipl & STATUS_REG_IRQ_DISABLED_BIT));
}
 
/** Read interrupt priority level.
 *
 * @return Current interrupt priority level.
 */
ipl_t interrupts_read(void)
{
    return current_status_reg_read();
}
 
/** Initialize basic tables for exception dispatching
 * and starts the timer.
 */
void interrupt_init(void)
{
    irq_init(IRQ_COUNT, IRQ_COUNT);
    machine_timer_irq_start();
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/tags/0.4.1/kernel/arch/arm32/src/interrupt.c – Rev 4675 → 4687

Rev 4675		Rev 4687
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Interrupts controlling routines.	33	* @brief Interrupts controlling routines.
34	*/	34	*/
35		35
36	#include <arch/asm.h>	36	#include <arch/asm.h>
37	#include <arch/regutils.h>	37	#include <arch/regutils.h>
38	#include <ddi/irq.h>	38	#include <ddi/irq.h>
39	#include <ddi/device.h>	39	#include <ddi/device.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41		41
42	#ifdef MACHINE_testarm	42	#ifdef MACHINE_testarm
43	#include <arch/mach/testarm/testarm.h>	43	#include <arch/mach/testarm/testarm.h>
44	#endif	44	#endif
45		45
46	#ifdef MACHINE_integratorcp	46	#ifdef MACHINE_integratorcp
47	#include <arch/mach/integratorcp/integratorcp.h>	47	#include <arch/mach/integratorcp/integratorcp.h>
48	#endif	48	#endif
49		49
50	/** Initial size of a table holding interrupt handlers. */	50	/** Initial size of a table holding interrupt handlers. */
51	#define IRQ_COUNT 8	51	#define IRQ_COUNT 8
52		52
53	/** Disable interrupts.	53	/** Disable interrupts.
54	*	54	*
55	* @return Old interrupt priority level.	55	* @return Old interrupt priority level.
56	*/	56	*/
57	ipl_t interrupts_disable(void)	57	ipl_t interrupts_disable(void)
58	{	58	{
59	ipl_t ipl = current_status_reg_read();	59	ipl_t ipl = current_status_reg_read();
60		60
61	current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT \| ipl);	61	current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT \| ipl);
62		62
63	return ipl;	63	return ipl;
64	}	64	}
65		65
66	/** Enable interrupts.	66	/** Enable interrupts.
67	*	67	*
68	* @return Old interrupt priority level.	68	* @return Old interrupt priority level.
69	*/	69	*/
70	ipl_t interrupts_enable(void)	70	ipl_t interrupts_enable(void)
71	{	71	{
72	ipl_t ipl = current_status_reg_read();	72	ipl_t ipl = current_status_reg_read();
73		73
74	current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);	74	current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
75		75
76	return ipl;	76	return ipl;
77	}	77	}
78		78
79	/** Restore interrupt priority level.	79	/** Restore interrupt priority level.
80	*	80	*
81	* @param ipl Saved interrupt priority level.	81	* @param ipl Saved interrupt priority level.
82	*/	82	*/
83	void interrupts_restore(ipl_t ipl)	83	void interrupts_restore(ipl_t ipl)
84	{	84	{
85	current_status_reg_control_write(	85	current_status_reg_control_write(
86	(current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) \|	86	(current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) \|
87	(ipl & STATUS_REG_IRQ_DISABLED_BIT));	87	(ipl & STATUS_REG_IRQ_DISABLED_BIT));
88	}	88	}
89		89
90	/** Read interrupt priority level.	90	/** Read interrupt priority level.
91	*	91	*
92	* @return Current interrupt priority level.	92	* @return Current interrupt priority level.
93	*/	93	*/
94	ipl_t interrupts_read(void)	94	ipl_t interrupts_read(void)
95	{	95	{
96	return current_status_reg_read();	96	return current_status_reg_read();
97	}	97	}
98		98
99	/** Initialize basic tables for exception dispatching	99	/** Initialize basic tables for exception dispatching
100	* and starts the timer.	100	* and starts the timer.
101	*/	101	*/
102	void interrupt_init(void)	102	void interrupt_init(void)
103	{	103	{
104	irq_init(IRQ_COUNT, IRQ_COUNT);	104	irq_init(IRQ_COUNT, IRQ_COUNT);
105	machine_timer_irq_start();	105	machine_timer_irq_start();
106	}	106	}
107		107
108	/** @}	108	/** @}
109	*/	109	*/
110		110